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Intel i960 Design Manual

Rm/rn i/o processor
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Intel
i960
RM/RN I/O Processor
Design Guide
April 2002
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Order Number:
273139-004

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Summary of Contents for Intel i960

  • Page 1 ® ® Intel i960 RM/RN I/O Processor Design Guide April 2002 Order Number: 273139-004...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    ® ® Intel i960 RM/RN I/O Processor Contents Introduction ........................... 9 ® Intel 80960RM/RN Processor Ball Map..................9 ® Intel 80960RM/RN Processor PBGA Signal Ball Map ..........10 Routing Guidelines ........................11 Trace Length Limits .......................11 ® Intel 80960RM/RN Processor Memory Subsystem ..............12 ROM, SRAM, or Flash Guidelines .................12...
  • Page 4 ® ® Intel i960 RM/RN I/O Processor 12.3 JTAG Connector and Test Interface ................48 ® ® 12.3.1 Intel i960 RM/RN I/O Processor JTAG Emulator ............. 48 ® ® 12.3.2 Intel i960 RM/RN I/O Processor Target Debug Interface Connector ....... 48 12.3.3 Connecting The Emulator To The Target ..............
  • Page 5 ® ® Intel i960 RM/RN I/O Processor Figures 540L H-PBGA Diagram (Bottom View)..................10 Examples of Stubless and Short Stub Traces ................11 4 Mbyte Flash Memory System ....................13 Dual-Bank SDRAM Memory Subsystem ..................15 SDRAM DIMM Layout Topology #1....................17 SDRAM DIMM Layout Topology #2....................17 Address and Control Topology for Two Discrete SDRAM Devices ..........18...
  • Page 6 ® ® Intel i960 RM/RN I/O Processor 15-50 Logic Analyzer I/F Schematic ..................... 81 15-51 SDRAM 168-Pin DIMM Schematic ..................... 82 15-52 Secondary PCI/80960 Core Schematic ..................83 15-53 Secondary PCI Bus 1/2 Schematic .................... 84 15-54 Secondary PCI Bus 3/4 Schematic .................... 85 15-55 SPCI Pull-Ups Schematic ......................
  • Page 7 ® Intel IQ80960RM Bill of Materials .....................72 ® Intel IQ80960RN Bill of Materials .....................88 ® ® 540-Lead H-PBGA Pinout — Intel i960 RM I/O Processor Processor........93 ® ® 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor ........98 Design Guide...

  • Page 8: Revision History

    ® ® Intel i960 RM/RN I/O Processor Revision History Date Description of Changes 04/2002 • Changed “Thermal Recommendations” section. 08/2000 • Added schematics. • Updated Trademarks and Branding. • Updated vendor tables. 06/2000 • Minor text rewrites. • Updated Pinout tables.

  • Page 9: Introduction

    The i960 RN I/O Processor is an Intel I/O processor supporting both 64-bit and 32-bit PCI operation. The i960 RM I/O Processor is an Intel I/O processor only supporting 32-bit PCI operation.

  • Page 10: Intel ® 80960Rm/Rn Processor Pbga Signal Ball Map

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Ball Map Figure 2-1. 540L H-PBGA Diagram (Bottom View) Secondary PCI Bus Signals 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32...

  • Page 11: Routing Guidelines

    Intel® i960® RM/RN I/O Processor Routing Guidelines Routing Guidelines The order in which signals are routed first and last varies from designer to designer. Some prefer to route all clock signals first, while others prefer to route all high speed bus signals first. Either order can be used, provided the guidelines listed here are followed.

  • Page 12: Intel ® 80960Rm/Rn Processor Memory Subsystem

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem ® Intel 80960RM/RN Processor Memory Subsystem RM/RN I/O processor integrates a memory controller to provide a direct interface between the RM/RN I/O processor and its local memory subsystem. The memory controller supports: •...

  • Page 13: Layout Guidelines

    DQ[7:0] Flash signal loading should not exceed 50 pF. If the system conforms to I O specification, then a minimum 16 Mbit Flash such as Intel’s 28F016SA is suggested. All traces between the RM/RN I/O processor and Flash/SRAM should not exceed 8 inches.

  • Page 14: Sdram Guidelines

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem SDRAM Guidelines RM/RN I/O processor memory controller supports up to two banks of 66 MHz, 72-bit SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128 Mbytes of ECC protected memory.

  • Page 15: Layout Guidelines

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem 4.2.1 Layout Guidelines The SDRAM subsystem may be implemented with: • up to two banks directly connected on the printed circuit board (32, 64, or 72 bits wide) •...

  • Page 16: Drive Strength Programmability Options

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem The drive strengths for the SDRAM signals are independently programmable using the SDCR register. Table 4-4 lists some example SDRAM configurations and how the SDCR should be programmed. The...

  • Page 17: Sdram Dimm Layout Topology #1

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-5. SDRAM DIMM Layout Topology #1 D IM M D IM M 1 to 8 in ches 0 to 0 .6 in ches Inte l® A dd ress, D ata and C on tro l...

  • Page 18: Address And Control Topology For Two Discrete Sdram Devices

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-7. Address and Control Topology for Two Discrete SDRAM Devices SDRAM 0 Signals m ust be 3 to 9.5 inches from the processor and each SDRAM device Intel®...

  • Page 19: Data And Dqm Topology For Discrete Sdram Devices

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-9. Data and DQM Topology for Discrete SDRAM Devices D a t a s ig n a ls m u s t b e 3 t o 8...

  • Page 20: Sdram Clocking And Clock Buffer Specifications

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem 4.2.2 SDRAM Clocking and Clock Buffer Specifications The MCU provides one clock (DCLKOUT) to the SDRAM memory subsystem with a 66 MHz frequency. The 72-bit, 2-bank SDRAM DIMM specification requires four clocks to distribute the loading across eighteen x8 SDRAM components.

  • Page 21: Dclkin Routing And Loading Requirements

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem DCLKOUT and the clock buffer outputs may be between 1 and 8 inches. Each of the four clock buffer outputs must be equal in length. Refer to Table 4-5 for the DCLKIN trace length and capacitance requirements.

  • Page 22: Clock Routing For A Two Device Sdram Subsystem

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Any memory configuration using four or more discrete SDRAM components directly on the board must adhere to the same routing requirements specified in the 4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification.

  • Page 23: Sdram Power Failure Guidelines

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem 4.2.3 SDRAM Power Failure Guidelines SDRAM technology provides a simple way of enabling data preservation through the self-refresh command. When the memory controller issues this command, the SDRAM refreshes itself autonomously with internal logic and timers.

  • Page 24: External Power Failure Logic In The System

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-13. External Power Failure Logic in the System Address, Data, and Control Memory SCKE SDRAM Controller SCKE[0] Subsystem External PLD PULLCKE P_RST# The implementation illustrated in Figure 4-13...

  • Page 25: Interrupt Routing

    Intel® i960® RM/RN I/O Processor Interrupt Routing Interrupt Routing As stated in the PCI Local Bus Specification, Revision 2.1 and the PCI-to-PCI Bridge Architecture Specification, Revision 1.0, interrupt routing is system-specific. In general, the BIOS maps the device’s interrupt line to the RM/RN I/O processor’s secondary bus INTx line.

  • Page 26: Intel ® 80960Rm/Rn Processor Implementation On An Add-In Card

    Intel® i960® RM/RN I/O Processor Interrupt Routing ® Intel 80960RM/RN Processor Implementation on an Add-in Card When designing the RM/RN I/O processor into an add-in card, refer to Figure 5-14 for Device ID address and interrupt routing. Figure 5-14. Example Secondary PCI Connector Interrupt Routing Intel®...

  • Page 27: Clocking Guidelines

    Intel® i960® RM/RN I/O Processor Clocking Guidelines Clocking Guidelines RM/RN I/O processor uses P_CLK (synchronous clock) input for clocking. All AC timings on the primary PCI bus and the secondary PCI bus are referenced to the P_CLK input. The system must provide clocks for any devices on the secondary PCI bus and ensure that system level goals for clock skew and jitter are met.

  • Page 28: Layout Guidelines For Motherboards

    Intel® i960® RM/RN I/O Processor Clocking Guidelines Layout Guidelines for Motherboards For motherboard implementations, the designer has much more flexibility with PCI clocking, primarily related to controlling the central clock resources. Skew requirements for the motherboard are more stringent due to the uncertainty of having PCI edge connectors on the secondary bus.

  • Page 29: Clock Vendors

    Intel® i960® RM/RN I/O Processor Clocking Guidelines Clock Vendors The low-skew clock buffer components in Table 6-8 are suggested. This is neither an endorsement nor a warranty of the performance of the listed product and/or company. Table 6-8. Low Skew Clock Buffer Information...

  • Page 30: Intel ® 80960Rm/Rn Processor Signals Requiring Pull-Up/Down Resistors

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 7-9 through Table 7-11 identify the signals that require pull-up and/or pull-down resistors and the recommended resistor values.

  • Page 31: Pci Signals

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 7-11. PCI Signals (Sheet 2 of 2) Resistor value Pull-up or Signal Comments (in Ohms) Pull-down S_ FRAME# 2.7K pull-up On Secondary Bus S_ STOP# 2.7K...

  • Page 32: Intel ® 80960Rm/Rn Processor Signals Requiring Pull-Up/Down Resistors

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 8-12 through Table 8-14 identify the signals that require pull-up and/or pull-down resistors and the recommended resistor values.
  • Page 33 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 8-14. PCI Signals (Sheet 2 of 2) (Sheet 2 of 2) Resistor value Pull-up or Signal Comments (in Ohms) Pull-down S_ FRAME# 2.7K pull-up On Secondary Bus S_ STOP# 2.7K...

  • Page 34: Intel ® 80960Rm/Rn Processor 5 V And 3.3 V Design Considerations

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations Providing 3.3 V in a 5 V System In most system board designs, the 5 V system power supply is routed to board components through a dedicated board layer.

  • Page 35: Creating A Power "Island

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations Figure 9-17. Creating a Power “Island” 3.3V island Gap in Plane Connection Point for 3.3V Source 5V Plane Design Guide...

  • Page 36: Choosing A Power Source

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations Choosing a Power Source The primary concern that must be addressed when selecting a power source is the maximum load current requirement. The processor power supply must maintain correct voltage regulation at a current of 5.0 A for the...

  • Page 37: Pci Adapter Card Power Source

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations PCI Adapter Card Power Source Currently, PCI Adapter card vendors cannot rely on the PCI connector to provide 3.3V. Hence, any adapter card designed with the RM/RN I/O processor must design an on-board 3.3V regulator for...

  • Page 38: Pullups And Pulldown Resistors

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations Pins Requirement CCPLL To reduce clock skew on the processor, the V pin for the Phase Lock Loop (PLL) circuit is C C P L L isolated on the pinout.

  • Page 39: Fail

    FAIL# pin is high (inactive) at 3.3 V, the LED can still be forward biased enough to glow. To ensure the LED extinguishes when FAIL# goes high, Intel recommends the circuit shown in Figure 9-22.

  • Page 40: Processor Power Supply Decoupling

    Intel® i960® RM/RN I/O Processor Processor Power Supply Decoupling 10.0 Processor Power Supply Decoupling Processor power supply decoupling is critical for reliable operation. With the 3.3 V ready system, two areas of concern are described in Section 10.1 Section 10.2: •...

  • Page 41: Bulk Decoupling Capacitance

    Intel® i960® RM/RN I/O Processor Processor Power Supply Decoupling Figure 10-23. High-Frequency Capacitor Values and Layout Legend: µ = 0.1 F Capacitor 10.2 Bulk Decoupling Capacitance Bulk, or low-frequency decoupling is needed on the RM/RN I/O processor. If the processor is on a separate power plane “island”, it is necessary to place capacitance on the processor “island.”...

  • Page 42: Intel 80960Rm/Rn Processor Based Reference Design

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Based Reference Design ® 11.0 Intel 80960RM/RN Processor Based Reference Design Appendix A through Appendix D for schematics and bill of material. OrCAD libraries for the RM/RN I/O processor are available and can be supplied upon request.

  • Page 43: Debug Connector Recommendations

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations 12.0 Debug Connector Recommendations This section describes debug hardware and connectors developed for the RM/RN I/O processor. This includes sockets, headers, logic analyzer interposer, Mictor* signal cross reference lists and JTAG emulator debug connector/pin assignments.

  • Page 44: L Pbga Socket

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-25. 540L PBGA Socket .340 inch .125 inch .05 inch Chamfer .812 inch .667 inch .312 inch .062 inch .193 inch .050 inch .062 inch 1.674 inch Side View Top View...

  • Page 45: Logic Analyzer Connectivity

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations 12.2 Logic Analyzer Connectivity The Mictor connector is the common connector used by the RM/RN I/O processor for logic analysis connectivity. The Cyclone evaluation board developed for the 80960RM/RN integrates five Mictor connectors to route the appropriate signals for logic analysis and probing. See Table 12-16.

  • Page 46: Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-26. Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View Packard-Hughes Interconnect Direct Mount Interposer 4.59 inch Mictor* Connectors 1.91 inch Flex Tape Socket Pin #1 * Other brands and names are the property of their respective owners.

  • Page 47: Flex Tape Interposer Application (Add-In Card)

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-28. Flex Tape Interposer Application (Add-In Card) Flex Tape Interposer Mictor 312 mm connector Top view of Flex Tape Interposer Add-in Card Pin #1 Side View PCI Connector Motherboard A5882-01 Figure 12-29. Flex Tape Interposer (Top View) Figure 12-30.

  • Page 48: Jtag Connector And Test Interface

    RM/RN I/O Processor Target Debug Interface Connector The i960 microprocessor target should have a 16-pin, two row header connector. Use 3M part number 2516-6002UG or equivalent. The header is made from a keyed plastic shroud with two rows of 8 pins and the spacing between adjacent pins and between the two rows is 0.100”. The...

  • Page 49: Rm/Rn I/O Processor Debug Connector Wiring

    Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-17 describes the interconnections required between the target debug interface connector and the pins/balls of the i960 RM/RN I/O processor family. ® Table 12-17. i960 RM/RN I/O Processor Debug Connector Wiring ®...

  • Page 50: Connecting The Emulator To The Target

    The emulation software uses the first Test Access Port (TAP) on the PC-1149.1/100F boundary-scan controller card to control the i960 RM/RN I/O processor. A cable should be connected from the boundary-scan controller to the i960 RM/RN I/O processor target debug interface connector as shown in the following tables.

  • Page 51: Other Tools

    12.3.4 Other Tools Other tools are available that are designed to complement the i960 family of JTAG emulators. These include a full complement of boundary-scan hardware and software for testing the 80960RM/RN for opens, shorts, and other manufacturing defects once it has been installed onto the target board.

  • Page 52: Design For Manufacturability

    Intel® i960® RM/RN I/O Processor Design for Manufacturability 13.0 Design for Manufacturability RM/RN I/O processor is offered in a high-thermal BGA (H-PBGA) package. PBGA ® packaging is explained extensively in the Intel Packaging Databook (Order Number 240800). Design Guide...

  • Page 53: Thermal Solutions

    Refer to the thermal sections of the Intel 80960 RM I/O Processor Datasheet (273156), the Intel ® 80960 RN I/O Processor Datasheet (273157), and the Intel 80960 RS I/O Processor Datasheet (273328) and to the thermal section of the Thermal Data for the 540-Lead PBGA Package Application Note (273390).

  • Page 54: 3-Dimensional View: Processor With Heat Sink Attached

    Intel® i960® RM/RN I/O Processor Thermal Solutions 14.2 3-Dimensional View: Processor with Heat Sink Attached To assist the board designer in component placement, hole placement and dimensions, Figure 14-33 Figure 14-34 detail specifics. Figure 14-33 details dimensions for board designs requiring a Passive Heat Sink.

  • Page 55: Pcb Heatsink Hole Dimensions

    Intel® i960® RM/RN I/O Processor Thermal Solutions 14.3 PCB Heatsink Hole Dimensions Figure 14-33. Hole Dimensions for Passive Heatsink 2.98 mm REF 4 Holes of diameter 3.175 ± 0.0508 mm 48.4632 mm 25.4 mm Outline of Passive Heat Sink Heat Slug of...

  • Page 56: Board Level Keep Out Areas

    Intel® i960® RM/RN I/O Processor Thermal Solutions Figure 14-34. Board Level Keep Out Areas Trace Keep-Out Areas Heat Sink Area Pin Keep-Out Area = 3.81 mm (Top and Bottom View) Clip Keep-Out Area = 9.2 mm (Bottom View) Mounting hole diameter 3.175 ± 0.0508 mm...

  • Page 57: Clearances Of Pci Board And Components

    Intel® i960® RM/RN I/O Processor Thermal Solutions 14.4 Clearances of PCI Board and Components Figure 14-35. Clearances of PCI Board and Components Add-in card #1 Heat sink mounted on the package Maximum Add-in card #2 allowable component dimension on the backside...

  • Page 58: Heat Sink Information

    Intel® i960® RM/RN I/O Processor Thermal Solutions 14.5 Heat Sink Information Table 14-21 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies.

  • Page 59: Shipping Tray Vendor

    Intel® i960® RM/RN I/O Processor Thermal Solutions 14.5.4 Shipping Tray Vendor Table 14-24. Shipping Tray Vendor Company Factory Rep Phone # Shipping Tray Part # Ron Goth 602-465-5381 7-0000-21001-184-167 14.5.5 Logic Analyzer Interposer Vendor Table 14-25. Logic Analyzer Interposer Vendor...

  • Page 60: References

    Intel® i960® RM/RN I/O Processor References 15.0 References 15.1 Related Documents Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. To obtain Intel literature: call 1-800-548-4725 or visit Intel’s website at http://www.intel.com Table 15-27. Related Documentation...

  • Page 61: Intel Rm I/O Processor Schematics

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics ® ® Intel i960 RM I/O Processor Schematics Schematics in this document supersede schematics in Document #AZ1-00886. Design Guide...

  • Page 62: Decoupling And 3.3 V Power Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-36. Decoupling and 3.3 V Power Schematic Design Guide...

  • Page 63: Primary Pci Interface Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-37. Primary PCI Interface Schematic Design Guide...

  • Page 64: Memory Controller Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-38. Memory Controller Schematic Design Guide...

  • Page 65: Flash Rom, Uart And Leds Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-39. Flash ROM, UART and LEDs Schematic Design Guide...

  • Page 66: Logic Analyzer I/F Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-40. Logic Analyzer I/F Schematic Design Guide...

  • Page 67: Sdram 168-Pin Dimm Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-41. SDRAM 168-Pin DIMM Schematic Design Guide...

  • Page 68: Secondary Pci/80960 Core Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-42. Secondary PCI/80960 Core Schematic Design Guide...

  • Page 69: Secondary Pci Bus 1/2 Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-43. Secondary PCI Bus 1/2 Schematic Design Guide...

  • Page 70: Secondary Pci Bus 3/4 Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-44. Secondary PCI Bus 3/4 Schematic Design Guide...

  • Page 71: Battery Monitor Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-45. Battery Monitor Schematic Design Guide...

  • Page 72: Intel Iq80960Rm Board Bill Of Material

    Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Intel IQ80960RM Board Bill of MaterialB This appendix identifies all components on the IQ80960RM Evaluation Platform (Table B-1). ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet 1 of 4)
  • Page 73 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet 2 of 4) Item Location Part Description Manufacturer Manufacturer Part # C1, C4, C5, C6, C7, C8, C9, C12,...
  • Page 74 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet 3 of 4) Item Location Part Description Manufacturer Manufacturer Part # R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT R/SM 1/10 W 5% 2.4 Kohm (0805)
  • Page 75 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet 4 of 4) Item Location Part Description Manufacturer Manufacturer Part # BT1, BT2, BT3, BT4, Battery AA NiCd @ 600 mA/Hour...

  • Page 76: Intel Rn I/O Processor Schematics

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics ® ® Intel i960 RN I/O Processor Schematics Schematics in this document supersede schematics in Document #AZ1-00886. Design Guide...

  • Page 77: Decoupling And 3.3 V Power Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-46. Decoupling and 3.3 V Power Schematic Design Guide...

  • Page 78: Primary Pci Interface Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-47. Primary PCI Interface Schematic Design Guide...

  • Page 79: Memory Controller Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-48. Memory Controller Schematic Design Guide...

  • Page 80: Flash Rom, Uart And Leds Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-49. Flash ROM, UART and LEDs Schematic Design Guide...

  • Page 81: Logic Analyzer I/F Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-50. Logic Analyzer I/F Schematic Design Guide...

  • Page 82: Sdram 168-Pin Dimm Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-51. SDRAM 168-Pin DIMM Schematic Design Guide...

  • Page 83: Secondary Pci/80960 Core Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-52. Secondary PCI/80960 Core Schematic Design Guide...

  • Page 84: Secondary Pci Bus 1/2 Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-53. Secondary PCI Bus 1/2 Schematic Design Guide...

  • Page 85: Secondary Pci Bus 3/4 Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-54. Secondary PCI Bus 3/4 Schematic Design Guide...

  • Page 86: Spci Pull-Ups Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-55. SPCI Pull-Ups Schematic Design Guide...

  • Page 87: Battery/Monitor Schematic

    Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-56. Battery/Monitor Schematic Design Guide...

  • Page 88: Intel Iq80960Rn Board Bill Of Material

    Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Intel IQ80960RN Board Bill of MaterialD This appendix identifies all components on the IQ80960RN Evaluation Platform (Table D-1). ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet 1 of 4)
  • Page 89 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet 2 of 4) Item Location Part Description Manufacturer Manufacturer Part # C1, C4, C5, C6, C7, C8, C9, C12,...
  • Page 90 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet 3 of 4) Item Location Part Description Manufacturer Manufacturer Part # R/SM 1/10 W 5% 330 ohm (0805) Dale...
  • Page 91 Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet 4 of 4) Item Location Part Description Manufacturer Manufacturer Part # CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2 C60, C75, CAP TANT SM 220 µF, 10 V (7343)

  • Page 92: Intel Iq80960Rm/Rn Sdram Battery Backup Pld Equations

    Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations ® Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations MODULE BATT //TITLE SDRAM Battery Backup Enable //PATTERN101-1809-01 //REVISION //AUTHORJ. Neumann //COMPANYCyclone Microsystems Inc. //DATE 10/30/97 //CHIP PALLV16V8Z-20JI // 1/20/98 Modify target device to PALLV16V8Z-20JI //Initial release.

  • Page 93: Intel 80960Rm/Rn Processor Pbga Signal Ball Map

    Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-1 details the ballout for the 80960RM processor. ® ® Table F-1. 540-Lead H-PBGA Pinout — Intel i960...
  • Page 94 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-1. 540-Lead H-PBGA Pinout — Intel i960 RM I/O Processor Processor (Sheet 2 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 95 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-1. 540-Lead H-PBGA Pinout — Intel i960 RM I/O Processor Processor (Sheet 3 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 96 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-1. 540-Lead H-PBGA Pinout — Intel i960 RM I/O Processor Processor (Sheet 4 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 97 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-1. 540-Lead H-PBGA Pinout — Intel i960 RM I/O Processor Processor (Sheet 5 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 98 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-2 details the ballout for the 80960RN processor. ® ® Table F-2. 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor (Sheet 1 of 5)
  • Page 99 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-2. 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor (Sheet 2 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 100 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-2. 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor (Sheet 3 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 101 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-2. 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor (Sheet 4 of 5) Ball # Signal Ball # Signal Ball # Signal...
  • Page 102 Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map ® ® Table F-2. 540-Lead H-PBGA Pinout — Intel i960 RN I/O Processor Processor (Sheet 5 of 5) Ball # Signal Ball # Signal Ball # Signal...

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