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CACHE AND ON-CHIP DATA RAM
Figure 4-1. Internal Data RAM and Register Cache
The remainder of the internal data RAM can always be written from supervisor mode. User mode
write protection is optionally selected for the rest of the data RAM (40H to 3FFH) by setting the
Bus Control Register RAM protection bit (BCON.irp). Writes to internal data RAM locations
while they are protected generate a TYPE.MISMATCH fault. See
(BCON) Register" (pg.
13-6), for the format of the BCON register.
®
Some versions of i960
processor compilers can take advantage of internal data RAM. Profiling
compilers, such as those offered by Intel, can allocate the most frequently used variables into this RAM.
4.2
LOCAL REGISTER CACHE
The i960 Jx processor provides fast storage of local registers for call and return operations by
using an internal local register cache (also known as a stack frame cache). Up to 7 local register
sets can be contained in the cache before sets must be saved in external memory. The register set is
all the local registers (i.e., r0 through r15). The processor uses a 128-bit wide bus to store local
register sets quickly to the register cache. An integrated procedure call mechanism saves the
current local register set when a call is executed. A local register set is saved into a frame in the
local register cache, one frame per register set. When the eighth frame is saved, the oldest set of
local registers is flushed to the procedure stack in external memory, which frees one frame.
Section 7.1.4, Caching Local Register Sets (pg. 7-7)
to the Procedure Stack" (pg. 7-11)
cache and the external procedure stack.
4-2
NMI
Optional Interrupt Vectors
Available for Data
and
section 7.1.5, "Mapping Local Registers
further discuss the relationship between the internal register
0000 0000H
0000 0004H
0000 0003FH
0000 03FFH
section 13.4.1, "Bus Control
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