Figure 14-16. Multi-Word Access To Big-Endian Memory Space; Table 14-10. Byte Ordering On Bus Transfers, Short-Word Data Type; Table 14-11. Byte Ordering On Bus Transfers, Byte Data Type - Intel i960 Jx Developer's Manual

Table 14-10. Byte Ordering on Bus Transfers, Short-Word Data Type

Short-Word Data Type
Addr
Bus
Bits Xfer
Width
A1, A0
00 1st
32 bit
10 1st
16 bit X0 1st
X0 1st
8 bit
X1 2nd

Table 14-11. Byte Ordering on Bus Transfers, Byte Data Type

Byte Data Type
Bus Addr Bits
Width A1, A0
00
01
32 bit
10
11
X0
16 bit
X1
8 bit XX
Registers
R3
R4 B B A A 9 9
F F E E D D C C
R5
R6

Figure 14-16. Multi-Word Access to Big-Endian Memory Space

Bus Pins (AD31:0)
Little Endian
31:24 23:16 15:8
-- -- CC
CC DD --
-- -- CC
-- -- --
--
Xfer
31:24
1st --
1st --
1st --
1st DD
1st --
1st --
1st --
...
8 8
...
EXTERNAL BUS
Big Endian
7:0 31:24 23:16
DD -- --
-- DD CC
DD -- --
DD -- --
CC -- --
Bus Pins (AD31:0)
Little and Big Endian
23:16 15:8 7:0
-- -- DD
-- DD --
DD -- --
-- -- --
-- -- DD
-- DD --
-- -- DD
Memory
B B
A A
stl r4,A
9 9
8 8
F F
E E
D D
C C
15:8 7:0
DD CC
-- --
DD CC
-- CC
-- DD
A
A+1
A+2
14
A+3
A+4
A+5
A+6
A+7
14-29