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CONSIDERATIONS FOR WRITING PORTABLE CODE
A.10.1 Data Control Peripheral Units
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The bus controller and interrupt controller are implementation-specific extensions to the core
architecture. Operation, setup and control of these units is not a part of the core architecture. Other
implementations of the i960 architecture are free to augment or modify such system integration features.
A.10.2 Timers
The i960 Jx processor contains two 32-bit timers that are implementation-specific extensions to the
i960 architecture. Code involving operation, setup and control of the timers may or may not be
directly portable to other i960 processors.
A.10.3 Fault Implementation
The architecture defines a subset of fault types and subtypes that apply to all implementations of
the architecture. Other fault types and subtypes may be defined by implementations to detect errant
conditions that relate to implementation-specific features. For example, the i960 Jx microprocessor
provides an OPERATION.UNALIGNED fault for detecting non-aligned memory accesses. Future
i960 processor implementations that generate this fault are expected to assign the same fault type
and subtype numbers to the fault.
A.11 BREAKPOINTS
Breakpoint registers are not defined in the i960 architecture. The i960 Jx processor implements
two instruction and two data breakpoint registers.
A-7
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