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TIMERS
Software can read or write the TCRx value whether the timer is running or stopped. This lets the
user monitor the count without using hardware interrupts. The TMRx.sup bit lets the programmer
allow or prevent user mode writes to TCRx, TMRx and TRRx.
When the TCRx value decrements to zero, the unit's interrupt request signals the processor's
interrupt controller. See
section 10.3, "TIMER INTERRUPTS" (pg. 10-11)
The timer checks the value of the timer reload bit (TMRx.reload) setting. When TMRx.reload. = 1,
the processor:
•
Automatically reloads TCRx with the value in the Timer Reload Register (TRRx).
•
Decrements TCRx until it equals 0 again.
This process repeats until software clears TMRx.reload or TMR.enable.
When TMRx.reload = 0, the timer stops running and sets the terminal count bit (TMRx.tc). This
bit remains set until user software reads or writes the TMRx register. Either access type clears the
bit. The timer ignores any value specified for TMRx.tc in a write request.
Table 10-4. Timer Mode Register Control Bit Summary
X
X
X
X
X
X
N
0
X
N
N
1
0
X
X
X
1
X
X
X
Notes:
X = don't care
N = a number between 1H and FFFF FFFFH
10-8
Timer disabled.
0
Timer enabled, TMRx.enable is cleared when TCRx decrements
1
to zero.
Timer and auto reload enabled,TMRx.enable remains set when
1
TCRx=0. When TCRx=0, TCRx equals the TRRx value.
No faults for user mode writes are generated.
X
TYPE.MISMATCH fault generated on user mode write.
X
for more information.
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