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EXTERNAL BUS
14.2.3.4
Wait States
Wait states lengthen the microprocessor's bus cycles, allowing data transfers with slow memory
and I/O devices. The 80960Jx supports three types of wait states: address-to-data, data-to-data
and turnaround or recovery. All three types are controlled through the processor's RDYRCV
(Ready/Recover) pin, a synchronous input.
The processor's bus states follow the state diagram in
Figure
14.1. After the Ta state, the processor
enters the Tw/Td state to perform a data transfer. If the memory (or I/O) system is fast enough to
allow the transfer to complete during this clock (i.e., "ready"), external logic asserts RDYRCV.
The processor samples RDYRCV low on the next rising clock edge, completing the transfer; the
state is a data state. If the memory system is too slow to complete the transfer during this clock,
external logic drives RDYRCV high and the state is an address-to-data wait state. Additional wait
states may be inserted in similar fashion.
If the bus transaction is a burst, the processor re-enters the Tw/Td state after the first data transfer.
The processor continues to sample RDYRCV on each rising clock edge, adding a data-to-data wait
state when RDYRCV is high and completing a transfer when RDYRCV is low. The process
continues until all transfers are finished, with RDYRCV assertion denoting every data acquisition.
Figure 14-10
illustrates a quad word burst write transaction with wait states. There are two
address-to-data wait states single data-to-data wait states between transfers.
14
14-17
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