Table of Contents
Advertisement
INITIALIZATION AND SYSTEM REQUIREMENTS
The i960 Jx microprocessor uses the reserved address range 0000 0000H through 0000 03FFH for
internal data RAM. This internal data RAM is used for storage of interrupt vectors plus general
purpose storage available for application software variable allocation or data structures. Loads and
stores directed to these addresses access internal memory; instruction fetches from these addresses
are not allowed for the i960 Jx microprocessor. See
DATA
RAM, for more details.
12.3.1
Initial Memory Image (IMI)
The IMI comprises the minimum set of data structures that the processor needs to initialize its
system. As shown in
Figure
control block (PRCB) and system data structures. The IBR is located at a fixed address in memory.
The other components are referenced directly or indirectly by pointers in the IBR and the PRCB.
The IMI performs three functions for the processor:
•
Provides initial configuration information for the core and integrated peripherals.
•
Provides pointers to the system data structures and the first instruction to be executed after
processor initialization.
•
Provides checksum words that the processor uses in its self test routine at startup.
Several data structures are typically included as part of the IMI because values in these data
structures are accessed by the processor during initialization. These data structures are usually
programmed in the systems's boot ROM, located in memory region 14_15 of the address space.
The required data structures are:
•
PRCB
•
IBR
•
System procedure table
•
Control table
•
Interrupt table
•
Fault table
To ensure proper processor operation, the PRCB, system procedure table, control table, interrupt
table, and fault table must not be located in architecturally reserved memory -- addresses reserved
for on-chip Data RAM and addresses at and above FEFF FF60H. In addition, each of these
structures must start at a word-aligned address; a System Error occurs if any of these structures are
not word-aligned (see
section
12-10
12-4, these structures are: the initialization boot record (IBR), process
12.2.2.3).
CHAPTER 4, CACHE AND ON-CHIP
Advertisement
Table of Contents
