Table of Contents
Advertisement
PROGRAMMING ENVIRONMENT
An address in memory is a 32-bit value in the range 0H to FFFF FFFFH. Depending on the
instruction, an address can reference in memory a single byte, short-word (2 bytes), word
(4 bytes), double-word (8 bytes), triple-word (12 bytes) or quad-word (16 bytes). Refer to load and
store instruction descriptions in
multiple-byte addressing information.
3.5.1
Memory Requirements
The architecture requires that external memory have the following properties:
•
Memory must be byte-addressable.
•
Physical memory must not be mapped to reserved addresses that are specifically used by the
processor implementation.
•
Memory must guarantee indivisible access (read or write) for addresses that fall within
16-byte boundaries.
•
Memory must guarantee atomic access for addresses that fall within 16-byte boundaries.
The latter two capabilities, indivisible and atomic access, are required only when multiple processors
or other external agents, such as DMA or graphics controllers, share a common memory.
indivisible access
Guarantees that a processor, reading or writing a set of memory locations,
complete the operation before another processor or external agent can read
or write the same location. The processor requires indivisible access within
an aligned 16-byte block of memory.
atomic access
A read-modify-write operation. Here the external memory system must
guarantee that once a processor begins a read-modify-write operation on an
aligned, 16-byte block of memory it is allowed to complete the operation
before another processor or external agent can access to the same location.
An atomic memory system can be implemented by using the LOCK signal
to qualify hold requests from external bus agents. The processor asserts
LOCK for the duration of an atomic memory operation.
The upper 16 Mbytes of the address space (addresses FF00 0000H through FFFF FFFFH) are
reserved for implementation-specific functions. Programs written for the i960 Jx processor cannot
use this address space except for accesses to memory-mapped registers. As shown in
the initialization boot record is located just below the i960 Jx processor's reserved memory.
The i960 Jx processor requires some special consideration when using the lower 1 Kbyte of
address space (addresses 0000H to 03FFH). Loads and stores directed to these addresses access
internal memory; instruction fetches from these addresses are not allowed by the processor. See
section 4.1, "INTERNAL DATA RAM" (pg.
address space.
3-14
CHAPTER 6, INSTRUCTION SET REFERENCE
4-1). No external bus cycles are generated to this
for
Figure
3-2,
Advertisement
Table of Contents
