Ieee Required Instructions; Table 15-2. Boundary Scan Instruction Set - Intel i960 Jx Developer's Manual

TEST FEATURES
15.3.3 Boundary Scan Instruction Set
The i960 Jx processor supports three mandatory boundary scan instructions
/ and
sample preload extest
idcode and runbist . Table 15-2

Table 15-2. Boundary Scan Instruction Set

Instruction Code
0000 2
0001 2
0010 2
0011 2
0100 2
0101 2
0110 2
0111 2
15.3.4

IEEE Required Instructions

Instruction
Opcode
/ Requisite
extest initiates testing of external circuitry, typically board-level interconnects
and off chip circuitry. extest connects the Boundary-Scan register between TDI
and TDO in the Shift_IR state only. When extest is selected, all output signal pin
extest
values are driven by values shifted into the Boundary-Scan register and may
0000 2 change only on the falling-edge of TCK in the Update_DR state. Also, when
IEEE 1149.1
extest is selected, all system input pin states must be loaded into the
Required
Boundary-Scan register on the rising-edge of TCK in the Capture_DR state.
Values shifted into input latches in the Boundary-Scan register are never used
by the processor's internal logic.
sample/preload performs two functions:
•
sampre
0001 2
IEEE 1149.1
•
Required
15-8
. The i960 Jx processor also contains two additional public instructions
lists the i960 Jx processor's boundary scan instruction codes.
Instruction Name Instruction Code
extest
sampre
idcode
not used
private
not used
not used
runbist
When the TAP controller is in the Capture-DR state, the sample instruction
occurs on the rising edge of TCK and provides a snapshot of the
component's normal operation without interfering with that normal operation.
The instruction causes Boundary-Scan register cells associated with outputs
to sample the value being driven by or to the processor.
When the TAP controller is in the Update-DR state, the preload instruction
occurs on the falling edge of TCK. This instruction causes the transfer of
data held in the Boundary-Scan cells to the slave register cells. Typically the
slave latched data is then applied to the system outputs by means of the
extest instruction.
Instruction Name
private
1000 2
not used
1001 2
not used
1010 2
private
1011 2
private
1100 2
not used
1101 2
1110 2 not used
bypass
1111 2
Description
,
bypass