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This chapter provides an overview of the i960
processor-specific instruction set extensions. Also discussed are the assembly-language and
instruction-encoding formats, various instruction groups and each group's instructions.
Chapter 6, INSTRUCTION SET REFERENCE
language syntax, and the action taken when the instruction executes and examples of how to use
the instruction.
5.1
INSTRUCTION FORMATS
The i960 Jx processor instructions may be described in two formats: assembly language and
instruction encoding. The following subsections briefly describe these formats.
5.1.1
Assembly Language Format
Throughout this manual, instructions are referred to by their assembly language mnemonics. For
example, the add ordinal instruction is referred to as
syntax consists of the instruction mnemonic followed by zero to three operands, separated by
commas. In the following assembly language statement, ordinal operands in global registers g5 and
g9 are added together, and the result is stored in g7:
addo g5, g9, g7
In the assembly language listings in this chapter, the following symbols are used:
g
global register
r
local register
#
precedes a comment
All numbers used as literals or in address expressions are assumed to be decimal. Hexadecimal
numbers are denoted with a "0x" prefix (e.g., 0xffff0012). Several assembly language instruction
statement examples follow. Additional assembly language examples are given in
"Addressing Mode Examples" (pg.
subi r3, r5, r6
#r6
setbit 13, g4, g5
#g5
lda 0xfab3, r12
#r12
ld (r4), g3
#g3
st g10, (r6)[r7*2]
#the value at memory location that r6+2*r7 points to = g10
INSTRUCTION SET OVERVIEW
®
microprocessor family's instruction set and i960 Jx
describes each instruction, including assembly
addo
. The Intel 80960 assembly language
# g7 = g9 + g5
2-8).
r5 - r3
g4 with bit 13 set
0xfab3
the value at memory location that r4 points to
CHAPTER 5
5
section 2.3.5,
5-1
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