Table 6-15. Icctl Operand Fields - Intel i960 Jx Developer's Manual

INSTRUCTION SET REFERENCE
6.2.33 icctl
Mnemonic: icctl
Format: icctl
Description: Performs management and control of the instruction cache including
disabling, enabling, invalidating, loading and locking, getting status, and
storing cache sets to memory. Operations are indicated by the value of src1.
Some operations also use src2 and src/dst. When needed by the operation, the
processor orders the effects of the operation with previous and subsequent
operations to ensure correct behavior. For specific function setup, see the
following tables and diagrams:
Function
Disable I-cache
Enable I-cache
Invalidate I-cache
Load and lock
I-cache
Get I-cache
status
Get I-cache
locking status
Store I-cache
sets to memory
6-58
Instruction-cache Control
src1, src2,
reg/lit reg/lit

Table 6-15. icctl Operand Fields

src1
0 NA
1 NA
2 NA
src : Starting
3 address of code
to lock.
4 NA
5 NA
Destination
6 address for cache
sets
src/dst
reg
src2 src/dst
NA
NA
NA
Number of ways
to lock.
dst: Receives
status (see
Figure 6-4).
dst: Receives
status (see
Figure 6-4)
src : I-cache set
#'s to be stored
(see Figure 6-4).