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The Bus Control Unit (BCU) includes logic to control many common types of memory subsystems
directly. Every bus access is "formatted" according to the BCU programming. The i960 Jx
processor's BCU programming model differs from schemes used in other i960 processors.
13.1
Memory Attributes
Every location in memory has associated physical and logical attributes. For example, a specific
location may have the following attributes:
•
Physical: Memory is an 8-bit wide ROM
•
Logical: Memory is ordered big-endian and data is non-cacheable
In the example above, physical attributes correspond to those parameters that indicate how to
physically access the data. The BCU uses physical attributes to determine the bus protocol and
signal pins to use when controlling the memory subsystem. The logical attributes tell the BCU how
to interpret, format and control interaction of on-chip data caches. The physical and logical
attributes for an individual location are independently programmable.
13.1.1
Physical Memory Attributes
The only programmable physical memory attribute for the i960 Jx microprocessor is the bus width,
which can be 8-, 16- or 32-bits wide.
For the purposes of assigning memory attributes, the physical address space is partitioned into 8,
fixed 512 Mbyte regions determined by the upper three address bits. The regions are numbered as
8 paired sections for consistency with other i960 processor implementations. Region 0_1 maps to
addresses 0000 0000H to 1FFF FFFFH and region 14_15 maps to addresses E000 0000H to
FFFF FFFFH. The physical memory attributes for each region are programmable through the
PMCON registers. The PMCON registers are loaded from the Control Table. The i960 Jx micro-
processor provides one PMCON register for each region.The descriptions of the PMCON registers
and instructions on programming them are found in
MEMORY CONFIGURATION
Section
13.3.
CHAPTER 13
13-1
13
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