Table of Contents
Advertisement
3.5.6
Data Cache
The i960 JT processor features a 4 Kbyte write-through direct-mapped data cache.The i960 JF and
JD processors feature a 2 Kbyte write-through direct-mapped data cache. The i960 JA processor
features a 1 Kbyte write-through direct-mapped data cache. For more information, see
CHAPTER 4, CACHE AND ON-CHIP DATA
3.6
LOCAL REGISTER CACHE
The i960 Jx processor provides fast storage of local registers for call and return operations by using
an internal local register cache (also known as a stack frame cache). Up to 7 local register sets can
be contained in the cache before sets must be saved in external memory. The register set is all the
local registers (i.e., r0 through r15).
3.7
PROCESSOR-STATE REGISTERS
The architecture defines four 32-bit registers that contain status and control information:
•
Instruction Pointer (IP) register
•
Process Controls (PC) register
3.7.1
Instruction Pointer (IP) Register
The IP register contains the address of the instruction currently being executed. This address is
32 bits long; however, since instructions are required to be aligned on word boundaries in memory,
the IP's two least-significant bits are always 0 (zero).
All i960 processor instructions are either one or two words long. The IP gives the address of the
lowest-order byte of the first word of the instruction.
The IP register cannot be read directly. However, the IP-with-displacement addressing mode lets
software use the IP as an offset into the address space. This addressing mode can also be used with
the
(load address) instruction to read the current IP value.
lda
When a break occurs in the instruction stream due to an interrupt, procedure call or fault, the
processor stores the IP of the next instruction to be executed in local register r2, which is usually
referred to as the return IP or RIP register. Refer to
further discussion.
PROGRAMMING ENVIRONMENT
RAM.
•
Arithmetic Controls (AC) register
•
Trace Controls (TC) register
CHAPTER 7, PROCEDURE CALLS
3
for
3-17
Advertisement
Table of Contents
