Table of Contents
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Trace Controls (TC) Register
registers
15-7
Boundary-Scan
13-6
Bus Control (BCON)
,
12-22
D-23
device ID
15-5
Instruction
1-5
Interrupt Control (ICON)
Interrupt Map Control (IMAP0-IMAP2)
1-5
Interrupt Mask (IMSK)
1-5
Interrupt Pending (IPND)
Logical Memory Templates (LMTs)
1-9
naming conventions
re-initialization
6-114
software
6-91
remainder integer instruction
6-91
remainder ordinal instruction
6-91
remi
6-91
remo
A-4
reserved locations
1-9
reserved memory
reserving frames in the local register cache
reset operation
12-5
register values
12-3
reset state
6-92
ret
Return Instruction Pointer (RIP)
3-3
location
7-7
return operation
7-5
return type field
RIP, see Return Instruction Pointer (RIP)
3-11
ROM
6-94
rotate
Run Built-In Self-Test (RUNBIST) register
S
A-4
SALIGN
11-17
saving the interrupt mask
6-95
scanbit
6-96
scanbyte
,
5-6
6-97
sele
select based on equal instruction
select based on less or equal instruction
select based on not equal instruction
select based on ordered instruction
,
3-23
9-2
Select Based on Unordered
select instructions
self test (STEST) pin
5-6
selg
selge
5-6
sell
5-6
selle
1-5
selne
selno
,
D-15
5-6
selo
13-13
setbit
shift instructions
6-100
shli
6-100
shlo
shrdi
6-100
shri
6-100
shro
sign extension
integers
ordinals
11-36
single processor as bus master
16-bit bus width byte enable encodings
16-bit wide data bus bursts
software re-initialization
SP, see Stack Pointer
7-4
spanbit
src/dst parameter encodings
2-2
st
stack frame
allocation
stack frame cache
Stack Pointer (SP)
15-7
location
stacks
STEST
2-2
stib
2-2
stis
3-15
stl
2-2
stob
store instructions
5-6
2-2
stos
5-6
3-16
stq
5-6
4-7
stt
5-6
6-108
subc
5-6
6-120
12-6
,
6-97
,
5-6
6-97
,
6-97
,
6-97
,
5-6
6-97
,
5-6
6-97
,
6-97
6-99
6-100
6-100
2-2
2-3
14-32
14-12
6-114
6-103
9-7
,
,
6-104
3-15
7-2
,
3-17
4-2
7-4
3-3
3-11
12-6
,
6-104
,
6-104
,
,
4-7
6-104
,
6-104
,
5-5
6-104
,
,
4-7
6-104
,
6-104
INDEX
14-8
Index-13
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