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11.6.8.3
Mixed Mode
In mixed mode, pins XINT0 through XINT4 are configured for expanded mode. These pins are
encoded for the five most-significant bits of an expanded-mode vector number; the three
least-significant bits of the vector number are set internally to 010
are configured for dedicated mode.
Do not write to the low-order four bits of IMAP0 as these bits are used to buffer the
expanded-mode interrupt internally. XINT[4:1] are placed in IMAP0[3:0]; XINT0 is latched in a
special register for use in further arbitrating the interrupt and in selecting the interrupt handler.
IMSK register bit 0 is a global mask for the expanded-mode interrupts; bits 5 through 7 mask the
dedicated interrupts from pins XINT5 through XINT7, respectively. IMSK register bits 1-4 must
be set to 0 in mixed mode. The IPND register posts interrupts from the dedicated-mode pins
XINT[7:5]. IPND register bits that correspond to expanded-mode inputs are not used.
11.6.9
Saving the Interrupt Mask
Whenever an interrupt requested by XINT[7:0] or by the internal timers is serviced, the IMSK
register is automatically saved in register r3 of the new local register set allocated for the interrupt
handler. After the mask is saved, the IMSK register is optionally cleared. This allows all interrupts
except NMIs to be masked while an interrupt is being serviced. Since the IMSK register value is
saved, the interrupt procedure can restore the value before returning. The option of clearing the
mask is selected by programming the ICON register as described in
Control Register (ICON)" (pg.
•
Mask unchanged
•
Cleared for dedicated-mode sources only
•
Cleared for expanded-mode sources only
•
Cleared for all hardware-requested interrupts (dedicated and expanded mode)
The second and third options are used in mixed mode, where both dedicated-mode and
expanded-mode inputs are allowed. Timer unit interrupts are always dedicated-mode interrupts.
Note that when the same interrupt is requested simultaneously by a dedicated- and an
expanded-mode source, the interrupt is considered an expanded-mode interrupt and the IMSK
register is handled accordingly.
11-22). Several options are provided for interrupt mask handling:
INTERRUPTS
. Pins XINT5 through XINT7
2
section 11.7.4, "Interrupt
11-17
11
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