B2.31 Cpupwrctlr_El1, Power Control Register, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
The CPUPWRCTLR_EL1 provides information about power control support for the core.
Bit field descriptions
CPUPWRCTLR_EL1 is a 32-bit register, and is part of the
group.
RES0, [31:10]
WFE_RET_CTRL, [9:7]
WFI_RET_CTRL, [6:4]
RES0, [3:1]
CORE_PWRDN_EN, [0]
c
The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention
entry request until this time.
100798_0300_00_en
31
0
RES
Reserved.
RES0
CPU WFE retention control:
Disable the retention circuit. This is the default value, see
000
Retention Control Field on page B2-188
CPU WFI retention control:
Disable the retention circuit. This is the default value, see
000
Retention Control Field on page B2-188
Reserved.
RES0
Indicates to the power controller using PACTIVE if the core wants to power down when it
enters WFI state.
No power down requested.
0
A power down is requested.
1
Encoding Number of counter ticks
000
001
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B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1

IMPLEMENTATION DEFINED
WFE_RET_CTRL
Figure B2-27 CPUPWRCTLR_EL1 bit assignments
for more retention control options.
for more retention control options.
Table B2-7 CPUPWRCTLR Retention Control Field
Disable the retention circuit
2
reserved.
Non-Confidential
B2 AArch64 system registers
registers functional
10 9 7 6 4 3
WFI_RET_CTRL
CORE_PWRDN_EN
Table B2-7 CPUPWRCTLR
Table B2-7 CPUPWRCTLR
c
Minimum retention entry delay
(System counter at 50MHz-10MHz)
Default Condition.
40ns-200ns
1 0
B2-188