User Manuals: ST STM32L4 Series Evaluation Board

Manuals and User Guides for ST STM32L4 Series Evaluation Board. We have 8 ST STM32L4 Series Evaluation Board manuals available for free PDF download: Programming Manual, Manual, User Manual, Application Note

ST STM32L4 Series Programming Manual (262 pages)

Brand: ST | Category: Computer Hardware | Size: 2 MB

Table 1. Applicable Products
1
Table of Contents
2
About this Document

12
The Cortex-M4 Processor

17
The STM32 Cortex-M4 Instruction Set

50
- Instruction Set Summary
  50
- Table 21. Cortex-M4 Instructions
  50
- CMSIS Intrinsic Functions
  58
- Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
  59
- Table 23. CMSIS Intrinsic Functions to Access the Special Registers
  59
- About the Instruction Descriptions
  60
  - Operands
    60
  - Restrictions When Using PC or SP
    60
  - Flexible Second Operand
    60
  - Shift Operations
    62
  - Figure 13. ASR #3
    62
  - Figure 14. LSR #3
    63
  - Figure 15. LSL #3
    63
  - Figure 16. ROR #3
    64
  - Figure 17. RRX #3
    64
  - Address Alignment
    65
  - PC-Relative Expressions
    65
  - Conditional Execution
    65
  - Table 24. Condition Code Suffixes
    67
  - Instruction Width Selection
    68
- Memory Access Instructions
  69
  - Table 25. Memory Access Instructions
    69
  - Adr
    70
  - LDR and STR, Immediate Offset
    71
  - Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
    72
  - LDR and STR, Register Offset
    73
  - LDR and STR, Unprivileged
    74
  - LDR, PC-Relative
    75
  - Table 27. Label-PC Offset Ranges
    75
  - LDM and STM
    76
  - PUSH and POP
    78
  - LDREX and STREX
    79
  - Clrex
    80
- General Data Processing Instructions
  81
  - Table 28. Data Processing Instructions
    81
  - ADD, ADC, SUB, SBC, and RSB
    83
  - AND, ORR, EOR, BIC, and ORN
    85
  - ASR, LSL, LSR, ROR, and RRX
    86
  - Clz
    87
  - CMP and CMN
    88
  - MOV and MVN
    89
  - Movt
    91
  - REV, REV16, REVSH, and RBIT
    92
  - SADD16 and SADD8
    93
  - SHADD16 and SHADD8
    94
  - SHASX and SHSAX
    95
  - SHSUB16 and SHSUB8
    96
  - SSUB16 and SSUB8
    97
  - SASX and SSAX
    98
  - TST and TEQ
    99
  - UADD16 and UADD8
    100
  - UASX and USAX
    101
  - UHADD16 and UHADD8
    102
  - UHASX and UHSAX
    103
  - UHSUB16 and UHSUB8
    104
  - Sel
    105
  - Usad8
    106
  - Usada8
    107
  - USUB16 and USUB8
    108
- Multiply and Divide Instructions
  109
  - Table 29. Multiply and Divide Instructions
    109
  - MUL, MLA, and MLS
    110
  - UMULL, UMAAL and UMLAL
    111
  - SMLA and SMLAW
    112
  - Smlad
    114
  - SMLAL and SMLALD
    115
  - SMLSD and SMLSLD
    117
  - SMMLA and SMMLS
    119
  - Smmul
    120
  - SMUAD and SMUSD
    121
  - SMUL and SMULW
    122
  - UMULL, UMLAL, SMULL, and SMLAL
    123
  - SDIV and UDIV
    124
- Saturating Instructions
  125
  - Table 30. Saturating Instructions
    125
  - SSAT and USAT
    126
  - SSAT16 and USAT16
    127
  - QADD and QSUB
    128
  - QASX and QSAX
    129
  - QDADD and QDSUB
    130
  - UQASX and UQSAX
    131
  - UQADD and UQSUB
    132
- Packing and Unpacking Instructions
  134
  - Table 31. Packing and Unpacking Instructions
    134
  - PKHBT and PKHTB
    135
  - SXT and UXT
    136
  - SXTA and UXTA
    137
- Bitfield Instructions
  138
  - Table 32. Instructions that Operate on Adjacent Sets of Bits
    138
  - BFC and BFI
    139
  - SBFX and UBFX
    140
  - SXT and UXT
    141
  - B, BL, BX, and BLX
    142
  - Branch and Control Instructions
    142
  - Table 33. Branch and Control Instructions
    142
  - Table 34. Branch Ranges
    143
  - CBZ and CBNZ
    144
  - TBB and TBH
    147
- Floating-Point Instructions
  149
  - Table 35. Floating-Point Instructions
    149
  - Vabs
    151
  - Vadd
    152
  - Vcmp, Vcmpe
    153
  - VCVT, VCVTR between Floating-Point and Integer
    154
  - VCVT between Floating-Point and Fixed-Point
    155
  - Vcvtb, Vcvtt
    156
  - VDIV
    157
  - Vfma, Vfms
    158
  - Vfnma, Vfnms
    159
  - Vldm
    160
  - Vldr
    161
  - Vlma, Vlms
    162
  - VMOV Immediate
    163
  - VMOV Register
    164
  - VMOV Scalar to Arm Core Register
    165
  - VMOV Arm Core Register to Single Precision
    166
  - VMOV Two Arm Core Registers to Two Single Precision
    167
  - VMOV Arm Core Register to Scalar
    168
  - Vmrs
    169
  - Vmsr
    170
  - Vmul
    171
  - Vneg
    172
  - Vnmla, Vnmls, Vnmul
    173
  - Vpop
    174
  - Vpush
    175
  - Vsqrt
    176
  - Vstm
    177
  - Vstr
    178
  - Vsub
    179
- Miscellaneous Instructions
  180
  - Table 36. Miscellaneous Instructions
    180
  - Bkpt
    181
  - Cps
    182
  - Dmb
    183
  - Dsb
    184
  - Isb
    185
  - Mrs
    186
  - Msr
    187
  - Nop
    188
  - Sev
    189
  - Svc
    190
  - Wfe
    191
  - Wfi
    192

ST STM32L4 Series Programming Manual (262 pages)

Brand: ST | Category: Computer Hardware | Size: 2 MB

Table 1. Applicable Products
1
Table of Contents
2
About this Document
12
Typographical Conventions
12
List of Abbreviations for Registers
12
About the STM32 Cortex-M4 Processor and Core Peripherals
13
Figure 1. STM32 Cortex-M4 Implementation
13
System Level Interface
14
Integrated Configurable Debug
14
Cortex-M4 Processor Features and Benefits Summary
15
Cortex-M4 Core Peripherals
16
The Cortex-M4 Processor
17
Programmers Model
17
Processor Mode and Privilege Levels for Software Execution
17
Stacks
17
Core Registers
18
Table 2. Summary of Processor Mode, Execution Privilege Level, and Stack Usage
18
Table 3. Core Register Set Summary
18
Figure 2. Processor Core Registers
18
Table 4. PSR Register Combinations
20
Figure 3. APSR, IPSR and EPSR Bit Assignment
20
Figure 4. PSR Bit Assignment
20
Table 5. APSR Bit Definitions
21
Table 6. IPSR Bit Definitions
22
Table 7. EPSR Bit Definitions
23
Table 8. PRIMASK Register Bit Definitions
24
Table 9. FAULTMASK Register Bit Definitions
24
Figure 5. PRIMASK Bit Assignment
24
Figure 6. FAULTMASK Bit Assignment
24
Table 10. BASEPRI Register Bit Assignment
25
Table 11. CONTROL Register Bit Definitions
25
Figure 7. BASEPRI Bit Assignment
25
Exceptions and Interrupts
26
Data Types
26
The Cortex Microcontroller Software Interface Standard (CMSIS)
26
Memory Model
28
Figure 8. Memory Map
28
Memory Regions, Types and Attributes
29
Memory System Ordering of Memory Accesses
29
Table 12. Ordering of Memory Accesses
29
Behavior of Memory Accesses
30
Table 13. Memory Access Behavior
30
Software Ordering of Memory Accesses
31
Bit-Banding
32
Table 14. SRAM Memory Bit-Banding Regions
32
Table 15. Peripheral Memory Bit-Banding Regions
32
Figure 9. Bit-Band Mapping
33
Memory Endianness
34
Synchronization Primitives
34
Figure 10. Little-Endian Example
34
Programming Hints for the Synchronization Primitives
36
Table 16. CMSIS Functions for Exclusive Access Instructions
36
Exception Model
37
Exception States
37
Exception Types
37
Table 17. Properties of the Different Exception Types
38
Exception Handlers
39
Vector Table
40
Figure 11. Vector Table
40
Exception Priorities
41
Interrupt Priority Grouping
41
Exception Entry and Return
42
Figure 12. Cortex-M4 Stack Frame Layout
43
Fault Handling
44
Table 18. Exception Return Behavior
44
Fault Types
45
Table 19. Faults
45
Fault Escalation and Hard Faults
46
Fault Status Registers and Fault Address Registers
47
Lockup
47
Power Management
47
Table 20. Fault Status and Fault Address Registers
47
Entering Sleep Mode
48
Wakeup from Sleep Mode
48
External Event Input / Extended Interrupt and Event Input
49
Power Management Programming Hints
49
The STM32 Cortex-M4 Instruction Set
50
Instruction Set Summary
50
Table 21. Cortex-M4 Instructions
50
CMSIS Intrinsic Functions
58
Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
59
Table 23. CMSIS Intrinsic Functions to Access the Special Registers
59
About the Instruction Descriptions
60
Operands
60
Restrictions When Using PC or SP
60
Flexible Second Operand
60
Shift Operations
62
Figure 13. ASR #3
62
Figure 14. LSR #3
63
Figure 15. LSL #3
63
Figure 16. ROR #3
64
Figure 17. RRX #3
64
Address Alignment
65
PC-Relative Expressions
65
Conditional Execution
65
Table 24. Condition Code Suffixes
67
Instruction Width Selection
68
Memory Access Instructions
69
Table 25. Memory Access Instructions
69
Adr
70
LDR and STR, Immediate Offset
71
Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
72
LDR and STR, Register Offset
73
LDR and STR, Unprivileged
74
LDR, PC-Relative
75
Table 27. Label-PC Offset Ranges
75
LDM and STM
76
PUSH and POP
78
LDREX and STREX
79
Clrex
80
General Data Processing Instructions
81
Table 28. Data Processing Instructions
81
ADD, ADC, SUB, SBC, and RSB
83
AND, ORR, EOR, BIC, and ORN
85
ASR, LSL, LSR, ROR, and RRX
86
Clz
87
CMP and CMN
88
MOV and MVN
89
Movt
91
REV, REV16, REVSH, and RBIT
92
SADD16 and SADD8
93
SHADD16 and SHADD8
94
SHASX and SHSAX
95
SHSUB16 and SHSUB8
96
SSUB16 and SSUB8
97
SASX and SSAX
98
TST and TEQ
99
UADD16 and UADD8
100
UASX and USAX
101
UHADD16 and UHADD8
102
UHASX and UHSAX
103
UHSUB16 and UHSUB8
104
Sel
105
Usad8
106
Usada8
107
USUB16 and USUB8
108
Multiply and Divide Instructions
109
Table 29. Multiply and Divide Instructions
109
MUL, MLA, and MLS
110
UMULL, UMAAL and UMLAL
111
SMLA and SMLAW
112
Smlad
114
SMLAL and SMLALD
115
SMLSD and SMLSLD
117
SMMLA and SMMLS
119
Smmul
120
SMUAD and SMUSD
121
SMUL and SMULW
122
UMULL, UMLAL, SMULL, and SMLAL
123
SDIV and UDIV
124
Saturating Instructions
125
Table 30. Saturating Instructions
125
SSAT and USAT
126
SSAT16 and USAT16
127
QADD and QSUB
128
QASX and QSAX
129
QDADD and QDSUB
130
UQASX and UQSAX
131
UQADD and UQSUB
132
Packing and Unpacking Instructions
134
Table 31. Packing and Unpacking Instructions
134
PKHBT and PKHTB
135
SXT and UXT
136
SXTA and UXTA
137
Bitfield Instructions
138
Table 32. Instructions that Operate on Adjacent Sets of Bits
138
BFC and BFI
139
SBFX and UBFX
140
SXT and UXT
141
Branch and Control Instructions
142
B, BL, BX, and BLX
142
Table 33. Branch and Control Instructions
142
Table 34. Branch Ranges
143
CBZ and CBNZ
144
TBB and TBH
147
Floating-Point Instructions
149
Table 35. Floating-Point Instructions
149
Vabs
151
Vadd
152
Vcmp, Vcmpe
153
VCVT, VCVTR between Floating-Point and Integer
154
VCVT between Floating-Point and Fixed-Point
155
Vcvtb, Vcvtt
156
VDIV
157
Vfma, Vfms
158
Vfnma, Vfnms
159
Vldm
160
Vldr
161
Vlma, Vlms
162
VMOV Immediate
163
VMOV Register
164
VMOV Scalar to Arm Core Register
165
VMOV Arm Core Register to Single Precision
166
VMOV Two Arm Core Registers to Two Single Precision
167
VMOV Arm Core Register to Scalar
168
Vmrs
169
Vmsr
170
Vmul
171
Vneg
172
Vnmla, Vnmls, Vnmul
173
Vpop
174
Vpush
175
Vsqrt
176
Vstm
177
Vstr
178
Vsub
179
Miscellaneous Instructions
180
Table 36. Miscellaneous Instructions
180
Bkpt
181
Cps
182
Dmb
183
Dsb
184
Isb
185
Mrs
186
Msr
187
Nop
188
Sev
189
Svc
190

ST STM32L4 Series User Manual (110 pages)

Brand: ST | Category: Microcontrollers | Size: 1 MB

1 About this Document

2
2 Device Development Process

4
3 Reference Safety Architecture

5
- Safety Architecture Introduction
  5
- Compliant Item
  5
- Safety Analysis Assumptions
  8
  - Safety Requirement Assumptions
    8
- Electrical Specifications and Environment Limits
  9
- Systematic Safety Integrity
  9
- Hardware and Software Diagnostics
  9
  - Table 2. SS1 and SS2 Safe State Details
    9
  - Arm Cortex -M4 CPU
    10
  - Table 3. CPU_SM_0
    10
  - Table 4. CPU_SM_1
    11
  - Table 5. CPU_SM_2
    12
  - Table 6. CPU_SM_3
    12
  - Table 7. CPU_SM_4
    13
  - Table 8. CPU_SM_5
    13
  - Table 10. CPU_SM_7
    14
  - Table 9. CPU_SM_6
    14
  - Table 11. CPU_SM_8
    15
  - Table 12. MPU_SM_0
    15
  - System Bus Architecture/Busmatrix
    16
  - Table 13. MPU_SM_1
    16
  - Table 14. BUS_SM_0
    16
  - Embedded SRAM
    17
  - Table 15. BUS_SM_1
    17
  - Table 16. RAM_SM_0
    17
  - Table 17. RAM_SM_1
    18
  - Table 18. RAM_SM_2
    19
  - Table 19. RAM_SM_3
    19
  - Table 20. RAM_SM_4
    20
  - Table 21. RAM_SM_5
    20
  - Embedded Flash Memory
    21
  - Table 22. RAM_SM_6
    21
  - Table 23. FLASH_SM_0
    21
  - Table 24. FLASH_SM_1
    22
  - Table 25. FLASH_SM_2
    22
  - Table 26. FLASH_SM_3
    23
  - Table 27. FLASH_SM_4
    23
  - Table 28. FLASH_SM_5
    23
  - Table 29. FLASH_SM_6
    24
  - Table 30. FLASH_SM_7
    24
  - Table 31. FLASH_SM_8
    25
  - Firewall (FW)
    26
  - Power Controller (PWR)
    26
  - Table 32. FLASH_SM_9
    26
  - Table 33. FWR_SM_0
    26
  - Table 34. VSUP_SM_0
    26
  - Table 35. VSUP_SM_1
    27
  - Table 36. VSUP_SM_2
    27
  - Table 37. VSUP_SM_3
    28
  - Table 38. VSUP_SM_4
    28
  - Reset and Clock Controller (RCC)
    29
  - Table 39. VSUP_SM_5
    29
  - Table 40. CLK_SM_0
    29
  - Table 41. CLK_SM_1
    30
  - Table 42. CLK_SM_2
    30
  - General-Purpose Input/Output (GPIO)
    31
  - Table 43. CLK_SM_3
    31
  - Table 44. GPIO_SM_0
    31
  - Table 45. GPIO_SM_1
    32
  - Table 46. GPIO_SM_2
    32
  - Debug System or Peripheral Control
    33
  - Table 47. GPIO_SM_3
    33
  - Table 48. DBG_SM_0
    33
  - Table 49. LOCK_SM_0
    33
  - System Configuration Controller (SYSCFG)
    34
  - Table 50. SYSCFG_SM_0
    34
  - Table 51. DIAG_SM_0
    34
  - Direct Memory Access Controller (DMA/ DMA2D/ DMAMUX))
    35
  - Table 52. DMA_SM_0
    35
  - Table 53. DMA_SM_1
    35
  - Table 54. DMA_SM_2
    36
  - Table 55. DMA_SM_3
    36
  - Table 56. DMA_SM_4
    37
  - Chrom-Art Accelerator Controller (DMA2D)
    38
  - Table 57. DMA2D_SM_0
    38
  - Table 58. DMA2D_SM_1
    38
  - Chrom-GRC™ (GFXMMU)
    39
  - Table 59. DMA2D_SM_2
    39
  - Table 60. GFX_SM_0
    39
  - Extended Interrupt and Events Controller (EXTI)
    40
  - Table 61. GFX_SM_1
    40
  - Table 62. NVIC_SM_0
    40
  - Cyclic Redundancy-Check Calculation Unit (CRC)
    41
  - Table 63. NVIC_SM_1
    41
  - Table 64. CRC_SM_0
    41
  - Flexible Static Memory Controller (FSMC)
    42
  - Table 65. FSMC_SM_0
    42
  - Table 66. FSMC_SM_1
    42
  - Table 67. FSMC_SM_2
    43
  - Table 68. FSMC_SM_3
    43
  - Quad-SPI Interface and Octo-SPI Interface (QUADSPI/OCTOSPI)
    44
  - Table 69. QSPI_SM_0
    44
  - Table 70. QSPI_SM_1
    44
  - Analog-To-Digital Converter (ADC)
    45
  - Table 71. QSPI_SM_2
    45
  - Table 72. ADC_SM_0
    45
  - Table 73. ADC_SM_1
    46
  - Table 74. ADC_SM_2
    46
  - Table 75. ADC_SM_3
    47
  - Table 76. ADC_SM_4
    47
  - Digital-To-Analog Converter (DAC)
    48
  - Table 77. DAC_SM_0
    48
  - Table 78. DAC_SM_1
    48
  - Comparator (COMP)
    49
  - Table 79. VREF_SM_0
    49
  - Table 80. VREF_SM_1
    49
  - Table 81. COMP_SM_0
    49
  - Voltage Reference Buffer (VREFBUF)
    49
  - Table 82. COMP_SM_1
    50
  - Table 83. COMP_SM_2
    50
  - Table 84. COMP_SM_3
    51
  - Table 85. COMP_SM_4
    51
  - Digital Filter for Sigma Delta Modulators (DFSDM)
    52
  - Operational Amplifiers (OPAMP)
    52
  - Table 86. AMP_SM_0
    52
  - Table 87. DFS_SM_0
    52
  - Table 88. DFS_SM_1
    53
  - Table 89. DFS_SM_2
    53
  - Table 90. DFS_SM_3
    53
  - Digital Camera Interface (DCMI)
    54
  - Table 91. DCMI_SM_0
    54
  - Table 92. DCMI_SM_1
    54
  - LCD-TFT Display Controller (LTDC)
    55
  - Table 93. LCD_SM_0
    55
  - Table 94. LCD_SM_1
    55
  - DSI Host (DSI)
    56
  - Table 95. DSI_SM_0
    56
  - Table 96. DSI_SM_1
    56
  - Table 97. TSC_SM_0
    57
  - Table 98. TSC_SM_1
    57
  - Touch Sensing Controller (TSC)
    57
  - HASH Processor (HASH)
    58
  - Table 100. HASH_SM_0
    58
  - Table 101. HASH_SM_1
    58
  - Table 99. TSC_SM_2
    58
  - Table 102. RNG_SM_0
    59
  - Table 103. RNG_SM_1
    59
  - True Random Number Generator (RNG)
    59
  - Advanced Encryption Standard Hardware Accelerator (AES)
    60
  - Table 104. AES_SM_0
    60
  - Table 105. AES_SM_1
    60
  - Advanced, General, and Low-Power Timer (TIM1/2/3/4/5/8/15/16/17 LPTIM1/2)
    61
  - Table 106. AES_SM_2
    61
  - Table 107. ATIM_SM_0
    62
  - Table 108. ATIM_SM_1
    62
  - Table 109. ATIM_SM_2
    63
  - Table 110. ATIM_SM_3
    63
  - Basic Timers (TIM6/7)
    64
  - Table 111. ATIM_SM_4
    64
  - Table 112. GTIM_SM_0
    64
  - Real-Time Clock Module (RTC)
    65
  - Table 113. GTIM_SM_1
    65
  - Table 114. RTC_SM_0
    65
  - Table 115. RTC_SM_1
    66
  - Table 116. RTC_SM_2
    66
  - Inter-Integrated Circuit (I2C)
    67
  - Table 117. RTC_SM_3
    67
  - Table 118. IIC_SM_0
    67
  - Table 119. IIC_SM_1
    67
  - Table 120. IIC_SM_2
    68
  - Table 121. IIC_SM_3
    68
  - Table 122. IIC_SM_4
    69
  - Table 123. UART_SM_0
    69
  - Universal Synchronous/Asynchronous Receiver/Transmitter and Low Power Universal Asychronous Receiver/Transmitter (USART1/2/3/4/5/6/7/8 and LPUART)
    69
  - Table 124. UART_SM_1
    70
  - Table 125. UART_SM_2
    70
  - Table 126. UART_SM_3
    71
  - Serial Peripheral Interface (SPI)
    72
  - Table 127. SPI_SM_0
    72
  - Table 128. SPI_SM_1
    72
  - Table 129. SPI_SM_2
    72
  - Table 130. SPI_SM_3
    73
  - Table 131. SPI_SM_4
    73
  - Serial Audio Interface (SAI)
    74
  - Table 132. SAI_SM_0
    74
  - Table 133. SAI_SM_1
    74
  - Single Wire Protocol Master Interface (SWPMI)
    75
  - Table 134. SAI_SM_2
    75
  - Table 135. SWPMI_SM_0
    75
  - Table 136. SWPMI_SM_1
    76
  - Table 137. SWPMI_SM_2
    76
  - SD/SDIO/MMC Card Host Interface (SDMMC)
    77
  - Table 138. SWPMI_SM_3
    77
  - Table 139. SDIO_SM_0
    77
  - Table 140. SDIO_SM_1
    78
  - Table 141. SDIO_SM_2
    78
  - Controller Area Network (Bxcan)
    79
  - Table 142. CAN_SM_0
    79
  - Table 143. CAN_SM_1
    79
  - Table 144. CAN_SM_2
    80
  - Table 145. USB_SM_0
    80
  - Universal Serial Bus Full-Speed Device Interface (OTG_FS)
    80
  - Table 146. USB_SM_1
    81
  - Table 147. USB_SM_2
    81
  - Part Separation (no Interference)
    82
  - Table 148. USB_SM_3
    82
  - Table 149. FFI_SM_0
    82
- Conditions of Use
  83
- Table 150. FFI_SM_1
  83
- Table 151. List of Safety Recommendations
  84

ST STM32L4 Series Manual (213 pages)

Simplifying Microsoft Azure Connectivity with Discovery Kit IoT Node

Brand: ST | Category: Microcontrollers | Size: 14 MB

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