Embedded Sram; Flash Memory Overview - ST STM32F410 Reference Manual

RM0401
APB1
2.3

Embedded SRAM

STM32F410 devices feature 32 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state.
The CPU can access the embedded SRAM1, through the System Bus or through the I-
Code/D-Code buses when boot from SRAM is selected or when physical remap is selected
(Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)
controller). To get the max performance on SRAM execution, physical remap should be
selected (boot or software selection).
2.4

Flash memory overview

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
Table 1. Register boundary addresses (continued)
Bus Boundary address
0x4000 7800 - 0x4000 FFFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6400 - 0x4000 6FFF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1400 - 0x4000 27FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0000 - 0x4000 0BFF
RM0401 Rev 3
Peripheral
Reserved
DAC
PWR
Reserved
I2C4 FM+
Reserved
I2C2
I2C1
Reserved
USART2
Reserved
SPI2 / I2S2
Reserved
IWDG
WWDG
RTC & BKP Registers
Reserved
TIM6
TIM5
Reserved
in the SYSCFG
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