Battery Charge Monitoring; Adc Interrupts; Table 47. Adc Interrupts - ST STM32F410 Reference Manual

Analog-to-digital converter (ADC)
Note: The sensor has a startup time after waking from power down mode before it can output
V at the correct level. The ADC also has a startup time after power-on, so to minimize
SENSE
the delay, the ADON and TSVREFE bits should be set at the same time.
The temperature sensor output voltage changes linearly with temperature. The offset of this
linear function depends on each chip due to process variation (up to 45 °C from one chip to
another).
The internal temperature sensor is more suited for applications that detect temperature
variations instead of absolute temperatures. If accurate temperature reading is required, an
external temperature sensor should be used.
11.10

Battery charge monitoring

The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the
V voltage could be higher than V
BAT
V pin is internally connected to a bridge divider.
BAT
When the VBATE is set, the bridge is automatically enabled to connect:
•
VBAT/4 to the ADC1_IN18 and ADC1_IN16 input channels
Note: The VBAT and temperature sensor are connected to the same ADC internal channels
(ADC1_IN18 and ADC1_IN16). Only one conversion, either temperature sensor or VBAT,
must be selected at a time. When both conversion are enabled simultaneously, only the
VBAT conversion is performed.
11.11

ADC interrupts

An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
•
JSTRT (Start of conversion for channels of an injected group)
•
STRT (Start of conversion for channels of a regular group)
End of conversion of a regular group
End of conversion of an injected group
Analog watchdog status bit is set
Overrun
228/771
, to ensure the correct operation of the ADC, the
DDA

Table 47. ADC interrupts

Interrupt event
RM0401 Rev 3
Event flag Enable control bit
EOC EOCIE
JEOC JEOCIE
AWD AWDIE
OVR OVRIE
RM0401