Adc Interrupts; Table 79. Adc Interrupts - ST STM32F423 Reference Manual

Analog-to-digital converter (ADC)
13.11

ADC interrupts

An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
•
JSTRT (Start of conversion for channels of an injected group)
•
STRT (Start of conversion for channels of a regular group)
End of conversion of a regular group
End of conversion of an injected group
Analog watchdog status bit is set
Overrun
350/1324

Table 79. ADC interrupts

Interrupt event
RM0430 Rev 8
Event flag Enable control bit
EOC EOCIE
JEOC JEOCIE
AWD AWDIE
OVR OVRIE
RM0430