Exti Registers; Interrupt Mask Register (Exti_Imr); Event Mask Register (Exti_Emr); Rising Trigger Selection Register (Exti_Rtsr) - ST STM32F40 Series Reference Manual

RM0090
10.3 registers
EXTI
Refer to
10.3.1

Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
10.3.2

Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
10.3.3

Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Section 1.1 on page 47
28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
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28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
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28 27 26 25
Reserved
Doc ID 018909 Rev 4
for a list of abbreviations used in register descriptions.
24 23 22
MR22 MR21
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8 7 6
MR8 MR7 MR6 MR5
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24 23 22
MR22 MR21
rw
8 7 6
MR8 MR7 MR6 MR5
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24 23 22
TR22 TR21
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Interrupts and events
21 20 19 18
MR20 MR19 MR18
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5 4 3 2
MR4 MR3 MR2
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21 20 19 18
MR20 MR19 MR18
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5 4 3 2
MR4 MR3 MR2
rw rw rw rw
21 20 19 18
TR20 TR19 TR18
rw rw rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
TR17 TR16
rw rw
260/1422