Exti Registers; Interrupt Mask Register (Exti_Imr); Event Mask Register (Exti_Emr) - ST STM32F410 Reference Manual

Interrupts and events
9.3 registers
EXTI
Refer to
register descriptions.
9.3.1

Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Bits 20-19 Reserved, must be kept at reset value.
Bits 18:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
9.3.2

Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
Bits 20-19 Reserved, must be kept at reset value.
Bits 18:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
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Section 1.2: List of abbreviations for registers
28 27 26 25
Res. Res. Res.
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
24 23 22
Res. Res. MR22 MR21
rw
8 7 6
MR8 MR7 MR6 MR5
rw rw rw
24 23 22
Res. Res. MR22 MR21
rw
8 7 6
MR8 MR7 MR6 MR5
rw rw rw
RM0401 Rev 3
for a list of abbreviations used in
21 20 19 18
Res. Res. MR18
rw rw
5 4 3 2
MR4 MR3 MR2
rw rw rw rw
21 20 19 18
Res. Res. MR18
rw rw
5 4 3 2
MR4 MR3 MR2
rw rw rw rw
RM0401
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw