Exti Registers; Interrupt Mask Register (Exti_Imr); Event Mask Register (Exti_Emr) - ST STM32F102 Series Reference Manual

Interrupts and events
8.3 registers
EXTI
Refer to
8.3.1

Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
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Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0 MRx: Interrupt Mask on line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
8.3.2

Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0 MRx: Event Mask on line x
0: Event request from Line x is masked
1: Event request from Line x is not masked
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Section 1.1 on page 32
28 27 26 25
Reserved
Res.
12 11 10 9
MR11 MR10 MR9
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28 27 26 25
Reserved
Res.
12 11 10 9
MR11 MR10 MR9
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for a list of abbreviations used in register descriptions.
24 23 22
8 7 6
MR8 MR7 MR6 MR5
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24 23 22
8 7 6
MR8 MR7 MR6 MR5
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21 20 19 18
MR18
rw
5 4 3 2
MR4 MR3 MR2
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21 20 19 18
MR18
rw
5 4 3 2
MR4 MR3 MR2
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RM0008
17 16
MR17 MR16
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1 0
MR1 MR0
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17 16
MR17 MR16
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1 0
MR1 MR0
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