Rcc Registers; Clock Control Register (Rcc_Cr) - ST STM32F102 Series Reference Manual

RM0008
6.3

RCC registers

Refer to
6.3.1

Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31 30 29
Reserved
Res.
15 14 13
r r r
Bits 31:26 Reserved, always read as 0.
Bit 25 PLLRDY PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON PLL enable
Set and reset by software to enable PLL.
Reset by hardware when entering Stop and Standby mode. This bit can not be reset if the PLL clock
is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, always read as 0.
Bit 19 CSSON Clock Security System enable
Set and reset by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 1-25 MHz oscillator is ready.
Bit 18 HSEBYP External High Speed clock Bypass
Set and reset by software in debug for bypassing oscillator with external clock. This bit can be
written only if the external 1-25 MHz oscillator is disabled.
0: external 1-25 MHz oscillator not bypassed
1: external 1-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY External High Speed clock ready flag
Set by hardware to indicate that external 1-25 MHz oscillator is stable. This bit needs 6 cycles of
external 1-25 MHz oscillator clock to fall down after HSEON reset.
0: external 1-25 MHz oscillator not ready
1: external 1-25 MHz oscillator ready
Section 1.1 on page 32
28 27 26 25
PLL
RDY
r
12 11 10 9
HSICAL[7:0]
r r r r
for a list of abbreviations used in register descriptions.
24 23 22
PLLON Reserved
rw Res.
8 7 6
HSITRIM[4:0]
r rw rw
Reset and clock control (RCC)
21 20 19 18
CSS HSE
ON BYP
rw rw
5 4 3 2
Res.
rw rw rw
17 16
HSE HSE
RDY ON
r rw
1 0
HSI
HSION
RDY
r rw
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