Performance Versus Vcore Ranges; Peripheral Access Configuration; Table 13. Performance Versus Vcore Ranges; Table 14. Rcc Registers Used For Peripheral Access Configuration - ST STM32L1 Series Application Note

AN4612
4.5.1 Performance versus V
The maximum system clock frequency and Flash memory wait state depend on the selected
voltage range V
different clock source frequencies depending on the product voltage range.
CPU
Power
performance
performance
High Low
Medium Medium
Low High
High Medium
Medium High
4.5.2

Peripheral access configuration

Since the address mapping of some peripherals has been changed in the STM32L4 Series
versus the STM32L1 Series, different registers need to be used to [enable/disable] or
[enter/exit] the peripheral [clock] or [from reset mode].

Table 14. RCC registers used for peripheral access configuration

Register
Bus
L1 series
RCC_AHBRSTR
AHB RCC_AHBENR
RCC_AHBLPENR
RCC_APB1RSTR
APB1 RCC_APB1ENR
RCC_APB1LPENR
ranges
CORE
and also on V
CORE DD
Table 13. Performance versus V CORE ranges
Typical
V
CORE
Value
range
(V)
STM32L1
1 1.8
2 1.5
3 1.2
STM32L4
1 1.2
2 1.0
Register
L4 series
RCC_AHB1RSTR (AHB1)
RCC_AHB2RSTR (AHB2)
RCC_AHB3RSTR (AHB3)
RCC_AHB1ENR (AHB1)
RCC_AHB2ENR (AHB2)
RCC_AHB3ENR (AHB3)
RCC_AHB1SMENR (AHB1)
RCC_AHB2SMENR (AHB2)
RCC_AHB3SMENR (AHB3)
RCC_APB1RSTR1
RCC_APB1RSTR2
RCC_APB1ENR1
(1)
RCC_APB1ENR2
RCC_APB1SMENR1
RCC_APB1SMENR2
DocID027094 Rev 3
for STM32L1 Series. The following table gives the
Max frequency
(MHz)
4 WS 3 WS 2 WS
- - -
- - -
- - -
80 64 48
26 26 18
Used to [enter/exit] the AHB peripheral from
reset
(1)
Used to [enable/disable] the AHB peripheral
clock
(1)
Used to [enable/disable] the AHB peripheral
clock in sleep mode
(1)
Used to [enter/exit] the APB1 peripheral from
(1)
reset
Used to [enable/disable] the APB1 peripheral
clock
Used to [enable/disable] the APB1 peripheral
(1)
clock in sleep mode
Peripheral migration
V
DD
1 WS 0 WS
32 16 2.0 - 3.6
16 8
1.65 - 3.6
4 2
32 16
12 6
Comments
range
NA
NA
31/58
57