Addressing Modes And Effective Address Calculation; Addressing Mode - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

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Addressing Modes and Effective Address Calculation

The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset

of these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit-manipulation instructions use register direct, register

indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR,

BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in

the operand.

Table 2.11 Addressing Modes

Addressing Mode

Absolute address

Program-counter relative

Memory indirect

(1) Register Direct–Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register

containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0

to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as

32-bit registers.

(2) Register Indirect–@Ern

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand in memory. If the address is a program instruction address, the lower

24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

(3) Register Indirect with Displacement–@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register

(ERn) specified by the register field of the instruction, and the sum gives the address of a

memory operand. A 16-bit displacement is sign-extended when added.

@(d:16,ERn)/@(d:32,ERn)

@aa:8/#@aa:16/@aa:24/@aa:32

#xx:8/#xx:16/#xx:32

@(d:8,PC)/@(d:16,PC)

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