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STM32F107xx series
ST STM32F107xx series Manuals
Manuals and User Guides for ST STM32F107xx series. We have
3
ST STM32F107xx series manuals available for free PDF download: Reference Manual, Programming Manual
ST STM32F107xx series Reference Manual (1096 pages)
advanced ARM-based 32-bit MCUs
Brand:
ST
| Category:
Controller
| Size: 10 MB
Table of Contents
Table of Contents
2
Overview of the Manual
40
Table 1. Sections Related to each Stm32F10Xxx Product
40
Table
40
Table 2. Sections Related to each Peripheral
43
Documentation Conventions
46
List of Abbreviations for Registers
46
Glossary
46
Peripheral Availability
46
Memory and Bus Architecture
47
System Architecture
47
Figure 1. System Architecture
47
Figure 2. System Architecture in Connectivity Line Devices
48
Memory Organization
49
Memory Map
50
Register Boundary Addresses
50
Embedded SRAM
53
Bit Banding
53
Embedded Flash Memory
54
Table
54
Flash Module Organization (Low-Density Devices)
54
Table 5. Flash Module Organization (Medium-Density Devices)
55
Table 6. Flash Module Organization (High-Density Devices)
56
Table 7. Flash Module Organization (Connectivity Line Devices)
57
Table 8. XL-Density Flash Module Organization
57
Boot Configuration
60
Table 9. Boot Modes
60
CRC Calculation Unit
62
CRC Introduction
62
CRC Main Features
62
Figure 3. CRC Calculation Unit Block Diagram
62
CRC Functional Description
63
CRC Registers
63
Data Register (CRC_DR)
63
Independent Data Register (CRC_IDR)
63
Control Register (CRC_CR)
64
CRC Register Map
64
Table 10. CRC Calculation Unit Register Map and Reset Values
64
Power Control (PWR)
65
Power Supplies
65
Independent A/D and D/A Converter Supply and Reference Voltage
66
Figure 4. Power Supply Overview
66
Battery Backup Domain
67
Voltage Regulator
68
Power Supply Supervisor
68
Power on Reset (Por)/Power down Reset (PDR)
68
Programmable Voltage Detector (PVD)
68
Figure 5. Power on Reset/Power down Reset Waveform
68
Figure 6. PVD Thresholds
69
Low-Power Modes
70
Slowing down System Clocks
70
Table 11. Low-Power Mode Summary
70
Peripheral Clock Gating
71
Sleep Mode
71
Stop Mode
72
Table 12. Sleep-Now
72
Table 13. Sleep-On-Exit
72
Standby Mode
73
Table 14. Stop Mode
73
Table 15. Standby Mode
74
Auto-Wakeup (AWU) from Low-Power Mode
75
Power Control Registers
75
Power Control Register (PWR_CR)
75
Power Control/Status Register (PWR_CSR)
77
PWR Register Map
78
Table 16. PWR Register Map and Reset Values
78
Backup Registers (BKP)
79
BKP Introduction
79
BKP Main Features
79
BKP Functional Description
80
Tamper Detection
80
RTC Calibration
80
BKP Registers
81
Backup Data Register X (Bkp_Drx) (X = 1
81
RTC Clock Calibration Register (BKP_RTCCR)
81
Backup Control Register (BKP_CR)
82
Backup Control/Status Register (BKP_CSR)
82
BKP Register Map
83
Table 17. BKP Register Map and Reset Values
83
Low-, Medium-, High- and XL-Density Reset and Clock Control (RCC)
87
Reset
87
System Reset
87
Power Reset
88
Backup Domain Reset
88
Figure 7. Simplified Diagram of the Reset Circuit
88
Clocks
89
Figure 8. Clock Tree
90
Figure 9. HSE/ LSE Clock Sources
91
HSE Clock
91
HSI Clock
92
Pll
92
LSE Clock
93
LSI Clock
93
Clock Security System (CSS)
94
RTC Clock
94
System Clock (SYSCLK) Selection
94
Clock-Out Capability
95
Watchdog Clock
95
RCC Registers
96
Clock Control Register (RCC_CR)
96
Clock Configuration Register (RCC_CFGR)
98
Clock Interrupt Register (RCC_CIR)
101
APB2 Peripheral Reset Register (RCC_APB2RSTR)
103
APB1 Peripheral Reset Register (RCC_APB1RSTR)
106
AHB Peripheral Clock Enable Register (RCC_AHBENR)
108
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
109
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
111
Backup Domain Control Register (RCC_BDCR)
115
Control/Status Register (RCC_CSR)
117
RCC Register Map
119
Table 18. RCC Register Map and Reset Values
119
Connectivity Line Devices: Reset and Clock Control (RCC)
120
Reset
120
System Reset
120
Power Reset
121
Figure 10. Simplified Diagram of the Reset Circuit
121
Backup Domain Reset
122
Clocks
122
Figure 11. Clock Tree
123
HSE Clock
124
Figure 12. HSE/ LSE Clock Sources
125
HSI Clock
125
LSE Clock
126
Plls
126
LSI Clock
127
System Clock (SYSCLK) Selection
127
Clock Security System (CSS)
128
RTC Clock
128
Watchdog Clock
128
Clock-Out Capability
129
RCC Registers
129
Clock Control Register (RCC_CR)
129
Clock Configuration Register (RCC_CFGR)
131
Clock Interrupt Register (RCC_CIR)
134
APB2 Peripheral Reset Register (RCC_APB2RSTR)
137
APB1 Peripheral Reset Register (RCC_APB1RSTR)
138
AHB Peripheral Clock Enable Register (RCC_AHBENR)
141
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
142
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
144
Backup Domain Control Register (RCC_BDCR)
146
Control/Status Register (RCC_CSR)
148
AHB Peripheral Clock Reset Register (RCC_AHBRSTR)
149
Clock Configuration Register2 (RCC_CFGR2)
150
RCC Register Map
152
Table 19. RCC Register Map and Reset Values
152
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
154
GPIO Functional Description
154
Figure 13. Basic Structure of a Standard I/O Port Bit
155
Figure 14. Basic Structure of a Five-Volt Tolerant I/O Port Bit
155
Atomic Bit Set or Reset
156
General-Purpose I/O (GPIO)
156
Table 20. Port Bit Configuration Table
156
Table 21. Output MODE Bits
156
Alternate Functions (AF)
157
External Interrupt/Wakeup Lines
157
GPIO Locking Mechanism
157
Software Remapping of I/O Alternate Functions
157
Figure 15. Input Floating/Pull Up/Pull down Configurations
158
Input Configuration
158
Output Configuration
158
Alternate Function Configuration
159
Figure 16. Output Configuration
159
Analog Configuration
160
Figure 17. Alternate Function Configuration
160
GPIO Configurations for Device Peripherals
161
Table 22. Advanced Timers TIM1/TIM8
161
Table 23. General-Purpose Timers TIM2/3/4/5
161
Usarts
161
Figure 18. High Impedance-Analog Configuration
161
Table 25. SPI
162
Table 26. I2S
162
Table 27. I2C
163
Table 28. Bxcan
163
Usb
163
Table 30. OTG_FS Pin Configuration
163
Sdio
164
Fsmc
164
Figure 19. ADC / DAC
164
Table 31. SDIO
164
Table 33. Other Ios
164
GPIO Registers
165
Port Configuration Register Low (Gpiox_Crl) (X=A..g
165
Port Configuration Register High (Gpiox_Crh) (X=A..g
166
Port Input Data Register (Gpiox_Idr) (X=A..g
166
Port Output Data Register (Gpiox_Odr) (X=A
167
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
167
Port Bit Reset Register (Gpiox_Brr) (X=A
168
Port Configuration Lock Register (Gpiox_Lckr) (X=A
168
Alternate Function I/O and Debug Configuration (AFIO)
169
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
169
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
169
CAN1 Alternate Function Remapping
170
CAN2 Alternate Function Remapping
170
JTAG/SWD Alternate Function Remapping
170
Table 34. CAN1 Alternate Function Remapping
170
Table 35. CAN2 Alternate Function Remapping
170
Table 36. Debug Interface Signals
170
ADC Alternate Function Remapping
171
Table 37. Debug Port Mapping
171
Table 38. ADC1 External Trigger Injected Conversion Alternate Function Remapping
171
Table 39. ADC1 External Trigger Regular Conversion Alternate Function Remapping
171
Table 40. ADC2 External Trigger Injected Conversion Alternate Function Remapping
171
Table 41. ADC2 External Trigger Regular Conversion Alternate Function Remapping
172
Table 42. TIM5 Alternate Function Remapping
172
Table 44. TIM3 Alternate Function Remapping
172
Timer Alternate Function Remapping
172
Table 46. TIM1 Alternate Function Remapping
173
Table 47. TIM9 Remapping
173
Table 48. TIM10 Remapping
173
Table 49. TIM11 Remapping
174
Table 50. TIM13 Remapping
174
Table 51. TIM14 Remapping
174
Table 52. USART3 Remapping
174
Table 53. USART2 Remapping
174
USART Alternate Function Remapping
174
Ethernet Alternate Function Remapping
175
I2C1 Alternate Function Remapping
175
SPI1 Alternate Function Remapping
175
SPI3/I2S3 Alternate Function Remapping
175
Table 54. USART1 Remapping
175
Table 55. I2C1 Remapping
175
Table 56. SPI1 Remapping
175
Table 57. SPI3/I2S3 Remapping
175
AFIO Registers
176
Table 58. ETH Remapping
176
Event Control Register (AFIO_EVCR)
177
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
178
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
184
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
184
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
185
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
185
AF Remap and Debug I/O Configuration Register2 (AFIO_MAPR2)
186
GPIO and AFIO Register Maps
187
Table 59. GPIO Register Map and Reset Values
187
Table 60. AFIO Register Map and Reset Values
187
Interrupts and Events
189
Nested Vectored Interrupt Controller (NVIC)
189
Systick Calibration Value Register
189
Interrupt and Exception Vectors
189
Table 61. Vector Table for Connectivity Line Devices
189
Table 62. Vector Table for XL-Density Devices
192
Table 63. Vector Table for Other Stm32F10Xxx Devices
195
External Interrupt/Event Controller (EXTI)
197
Main Features
197
Block Diagram
197
Wakeup Event Management
198
Functional Description
198
Figure 20. External Interrupt/Event Controller Block Diagram
198
External Interrupt/Event Line Mapping
199
Figure 21. External Interrupt/Event GPIO Mapping
200
EXTI Registers
201
Interrupt Mask Register (EXTI_IMR)
201
Event Mask Register (EXTI_EMR)
201
Rising Trigger Selection Register (EXTI_RTSR)
202
Falling Trigger Selection Register (EXTI_FTSR)
202
Software Interrupt Event Register (EXTI_SWIER)
203
Pending Register (EXTI_PR)
203
EXTI Register Map
204
Table 64. External Interrupt/Event Controller Register Map and Reset Values
204
Analog-To-Digital Converter (ADC)
205
ADC Introduction
205
ADC Main Features
206
ADC Functional Description
206
Figure 22. Single ADC Block Diagram
207
Table 65. ADC Pins
208
ADC Clock
209
ADC On-Off Control
209
Channel Selection
209
Single Conversion Mode
209
Continuous Conversion Mode
210
Figure 23. Timing Diagram
210
Timing Diagram
210
Analog Watchdog
211
Figure 24. Analog Watchdog Guarded Area
211
Scan Mode
211
Table 66. Analog Watchdog Channel Selection
211
Figure 25. Injected Conversion Latency
212
Injected Channel Management
212
Discontinuous Mode
213
Calibration
213
Data Alignment
214
Figure 26. Calibration Timing Diagram
214
Figure 27. Right Alignment of Data
214
Figure 28. Left Alignment of Data
214
Channel-By-Channel Programmable Sample Time
215
Conversion on External Trigger
215
Table 67. External Trigger for Regular Channels for ADC1 and ADC2
215
Table 68. External Trigger for Injected Channels for ADC1 and ADC2
216
Table 69. External Trigger for Regular Channels for ADC3
216
Table 70. External Trigger for Injected Channels for ADC3
216
DMA Request
217
Dual ADC Mode
218
Figure 29. Dual ADC Block Diagram
219
Figure 30. Injected Simultaneous Mode on 4 Channels
220
Injected Simultaneous Mode
220
Regular Simultaneous Mode
220
Fast Interleaved Mode
221
Figure 31. Regular Simultaneous Mode on 16 Channels
221
Figure 32. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
221
Slow Interleaved Mode
221
Alternate Trigger Mode
222
Figure 33. Slow Interleaved Mode on 1 Channel
222
Figure 34. Alternate Trigger: Injected Channel Group of each ADC
222
Combined Regular Simultaneous + Alternate Trigger Mode
223
Combined Regular/Injected Simultaneous Mode
223
Figure 35. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
223
Independent Mode
223
Combined Injected Simultaneous + Interleaved
224
Figure 36. Alternate + Regular Simultaneous
224
Figure 37. Case of Trigger Occurring During Injected Conversion
224
Figure 38. Interleaved Single Channel with Injected Sequence CH11, CH12
224
Temperature Sensor
225
Figure 39. Temperature Sensor and VREFINT Channel Block Diagram
225
ADC Interrupts
226
Table 71. ADC Interrupts
226
ADC Registers
227
ADC Status Register (ADC_SR)
227
ADC Control Register 1 (ADC_CR1)
228
ADC Control Register 2 (ADC_CR2)
230
ADC Sample Time Register 1 (ADC_SMPR1)
234
ADC Sample Time Register 2 (ADC_SMPR2)
235
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
235
ADC Watchdog High Threshold Register (ADC_HTR)
236
ADC Watchdog Low Threshold Register (ADC_LTR)
236
ADC Regular Sequence Register 1 (ADC_SQR1)
237
ADC Regular Sequence Register 2 (ADC_SQR2)
238
ADC Regular Sequence Register 3 (ADC_SQR3)
239
ADC Injected Sequence Register (ADC_JSQR)
240
ADC Injected Data Register X (Adc_Jdrx) (X= 1
240
ADC Regular Data Register (ADC_DR)
241
11.12.15 ADC Register Map
241
Table 72. ADC Register Map and Reset Values
241
Digital-To-Analog Converter (DAC)
243
DAC Introduction
243
DAC Main Features
243
Table 73. DAC Pins
244
Figure 40. DAC Channel Block Diagram
244
DAC Functional Description
245
DAC Channel Enable
245
DAC Output Buffer Enable
245
DAC Data Format
245
DAC Conversion
246
Figure 41. Data Registers in Single DAC Channel Mode
246
Figure 42. Data Registers in Dual DAC Channel Mode
246
DAC Output Voltage
247
DAC Trigger Selection
247
Table 74. External Triggers
247
Figure 43. Timing Diagram for Conversion with Trigger Disabled TEN = 0
247
DMA Request
248
Noise Generation
248
Figure 44. DAC LFSR Register Calculation Algorithm
248
Triangle-Wave Generation
249
Figure 45. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
249
Figure 46. DAC Triangle Wave Generation
249
Dual DAC Channel Conversion
250
Independent Trigger Without Wave Generation
250
Figure 47. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
250
Independent Trigger with same LFSR Generation
251
Independent Trigger with Different LFSR Generation
251
Independent Trigger with same Triangle Generation
251
Independent Trigger with Different Triangle Generation
252
Simultaneous Software Start
252
Simultaneous Trigger Without Wave Generation
252
Simultaneous Trigger with same LFSR Generation
253
Simultaneous Trigger with Different LFSR Generation
253
Simultaneous Trigger with same Triangle Generation
253
Simultaneous Trigger with Different Triangle Generation
254
DAC Registers
254
DAC Control Register (DAC_CR)
254
DAC Software Trigger Register (DAC_SWTRIGR)
257
DAC Channel1 12-Bit Right-Aligned Data Holding Register
258
(Dac_Dhr12R1)
258
DAC Channel1 12-Bit Left Aligned Data Holding Register
258
(Dac_Dhr12L1)
258
DAC Channel1 8-Bit Right Aligned Data Holding Register
258
(Dac_Dhr8R1)
258
DAC Channel2 12-Bit Right Aligned Data Holding Register
259
(Dac_Dhr12R2)
259
DAC Channel2 12-Bit Left Aligned Data Holding Register
259
(Dac_Dhr12L2)
259
DAC Channel2 8-Bit Right-Aligned Data Holding Register
259
(Dac_Dhr8R2)
259
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
260
DUAL DAC 12-Bit Left Aligned Data Holding Register
260
(Dac_Dhr12Ld)
260
DUAL DAC 8-Bit Right Aligned Data Holding Register
261
(Dac_Dhr8Rd)
261
DAC Channel1 Data Output Register (DAC_DOR1)
261
DAC Channel2 Data Output Register (DAC_DOR2)
261
DAC Register Map
262
Table 75. DAC Register Map
262
DMA Controller (DMA)
263
DMA Introduction
263
DMA Main Features
263
Figure 48. DMA Block Diagram in Connectivity Line Devices
264
DMA Functional Description
265
DMA Transactions
265
Figure 49. DMA Block Diagram in Low-, Medium- High- and XL-Density Devices
265
Arbiter
266
DMA Channels
266
Programmable Data Width, Data Alignment and Endians
268
Table 76. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
268
Error Management
269
Interrupts
269
Table 77. DMA Interrupt Requests
269
DMA Request Mapping
270
Figure 50. DMA1 Request Mapping
270
Table 78. Summary of DMA1 Requests for each Channel
271
Table 79. Summary of DMA2 Requests for each Channel
272
Figure 51. DMA2 Request Mapping
272
DMA Registers
273
DMA Interrupt Status Register (DMA_ISR)
273
DMA Interrupt Flag Clear Register (DMA
274
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
275
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
276
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
277
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
277
DMA Register Map
278
Table 80. DMA Register Map and Reset Values
278
Advertisement
ST STM32F107xx series Reference Manual (959 pages)
ARM-based 32-bit MCUs
Brand:
ST
| Category:
Microcontrollers
| Size: 15 MB
Table of Contents
Table of Contents
2
Documentation Conventions
36
List of Abbreviations for Registers
36
Glossary
36
Peripheral Availability
36
Memory and Bus Architecture
37
System Architecture
37
Figure 1. System Architecture
37
Figure 2. System Architecture in Connectivity Line Devices
38
Memory Organization
39
Memory Map
40
Table 1. Register Boundary Addresses
40
Embedded SRAM
41
Bit Banding
42
Embedded Flash Memory
42
Table 2. Flash Module Organization (Low-Density Devices)
43
Table 3. Flash Module Organization (Medium-Density Devices)
44
Table 4. Flash Module Organization (High-Density Devices)
44
Table 5. Flash Module Organization (Connectivity Line Devices)
45
Boot Configuration
46
Table 6. Boot Modes
46
CRC Calculation Unit
48
CRC Introduction
48
CRC Main Features
48
Figure 3. CRC Calculation Unit Block Diagram
48
CRC Functional Description
49
CRC Registers
49
Data Register (CRC_DR)
49
Independent Data Register (CRC_IDR)
50
Control Register (CRC_CR)
50
CRC Register Map
50
Table 7. CRC Calculation Unit Register Map and Reset Values
50
Power Control (PWR)
51
Power Supplies
51
Figure 4. Power Supply Overview
51
Battery Backup Domain
52
Independent A/D Converter Supply and Reference Voltage
52
Voltage Regulator
53
Power Supply Supervisor
53
Power on Reset (Por)/Power down Reset (PDR)
53
Programmable Voltage Detector (PVD)
54
Figure 5. Power on Reset/Power down Reset Waveform
54
Figure 6. PVD Thresholds
54
Low-Power Modes
55
Slowing down System Clocks
55
Table 8. Low-Power Mode Summary
55
Peripheral Clock Gating
56
Sleep Mode
56
Stop Mode
57
Table 9. Sleep-Now
57
Table 10. Sleep-On-Exit
57
Standby Mode
58
Table 11. Stop Mode
58
Table 12. Standby Mode
59
Auto-Wakeup (AWU) from Low-Power Mode
60
Power Control Registers
60
Power Control Register (PWR_CR)
60
Power Control/Status Register (PWR_CSR)
62
PWR Register Map
63
Table 13. PWR - Register Map and Reset Values
63
Backup Registers (BKP)
64
BKP Introduction
64
BKP Main Features
64
BKP Functional Description
65
Tamper Detection
65
RTC Calibration
65
BKP Registers
66
Backup Data Register X (Bkp_Drx) (X = 1
66
RTC Clock Calibration Register (BKP_RTCCR)
66
Backup Control Register (BKP_CR)
67
Backup Control/Status Register (BKP_CSR)
68
BKP Register Map
69
Table 14. BKP Register Map and Reset Values
69
Low-, Medium- and High-Density Reset and Clock Control (RCC)
72
Reset
72
System Reset
72
Power Reset
73
Backup Domain Reset
73
Figure 7. Reset Circuit
73
Clocks
74
Figure 8. Clock Tree
75
Figure 9. HSE/ LSE Clock Sources
76
HSE Clock
76
HSI Clock
77
Pll
77
LSE Clock
78
LSI Clock
78
Clock Security System (CSS)
79
RTC Clock
79
System Clock (SYSCLK) Selection
79
Clock-Out Capability
80
Watchdog Clock
80
RCC Registers
80
Clock Control Register (RCC_CR)
81
Clock Configuration Register (RCC_CFGR)
82
Clock Interrupt Register (RCC_CIR)
85
APB2 Peripheral Reset Register (RCC_APB2RSTR)
87
APB1 Peripheral Reset Register (RCC_APB1RSTR)
89
AHB Peripheral Clock Enable Register (RCC_AHBENR)
91
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
93
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
95
Backup Domain Control Register (RCC_BDCR)
97
Control/Status Register (RCC_CSR)
99
RCC Register Map
100
Table 15. RCC - Register Map and Reset Values
100
Connectivity Line Devices: Reset and Clock Control (RCC)
102
Reset
102
System Reset
102
Power Reset
103
Backup Domain Reset
103
Figure 10. Reset Circuit
103
Clocks
104
Figure 11. Clock Tree
105
HSE Clock
106
Figure 12. HSE/ LSE Clock Sources
107
HSI Clock
107
LSE Clock
108
Plls
108
LSI Clock
109
System Clock (SYSCLK) Selection
109
Clock Security System (CSS)
110
RTC Clock
110
Watchdog Clock
110
Clock-Out Capability
111
RCC Registers
111
Clock Control Register (RCC_CR)
111
Clock Configuration Register (RCC_CFGR)
113
Clock Interrupt Register (RCC_CIR)
116
APB2 Peripheral Reset Register (RCC_APB2RSTR)
119
APB1 Peripheral Reset Register (RCC_APB1RSTR)
120
AHB Peripheral Clock Enable Register (RCC_AHBENR)
123
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
124
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
126
Backup Domain Control Register (RCC_BDCR)
129
Control/Status Register (RCC_CSR)
130
AHB Peripheral Clock Reset Register (RCC_AHBRSTR)
132
Clock Configuration Register2 (RCC_CFGR2)
133
RCC Register Map
135
Table 16. RCC Register Map and Reset Values
135
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
137
GPIO Functional Description
137
Figure 13. Basic Structure of a Standard I/O Port Bit
138
Figure 14. Basic Structure of a Five-Volt Tolerant I/O Port Bit
138
Atomic Bit Set or Reset
139
General-Purpose I/O (GPIO)
139
Table 18. Output MODE Bits
139
Alternate Functions (AF)
140
External Interrupt/Wakeup Lines
140
GPIO Locking Mechanism
140
Software Remapping of I/O Alternate Functions
140
Figure 15. Input Floating/Pull Up/Pull down Configurations
141
Input Configuration
141
Output Configuration
141
Alternate Function Configuration
142
Figure 16. Output Configuration
142
Analog Input Configuration
143
Figure 17. Alternate Function Configuration
143
Figure 18. High Impedance-Analog Input Configuration
143
GPIO Registers
144
Port Configuration Register Low (Gpiox_Crl) (X=A..g
144
Table 17. Port Bit Configuration Table
144
Port Configuration Register High (Gpiox_Crh) (X=A..g
145
Port Input Data Register (Gpiox_Idr) (X=A..g
145
Port Output Data Register (Gpiox_Odr) (X=A
146
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
146
Port Bit Reset Register (Gpiox_Brr) (X=A..g
147
Port Configuration Lock Register (Gpiox_Lckr) (X=A..g
147
Alternate Function I/O and Debug Configuration (AFIO)
148
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
148
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
148
CAN1 Alternate Function Remapping
149
CAN2 Alternate Function Remapping
149
JTAG/SWD Alternate Function Remapping
149
Table 19. CAN1 Alternate Function Remapping
149
Table 20. CAN2 Alternate Function Remapping
149
Table 21. Debug Interface Signals
149
ADC Alternate Function Remapping
150
Table 22. Debug Port Mapping
150
Table 23. ADC1 External Trigger Injected Conversion Alternate Function Remapping
150
Table 24. ADC1 External Trigger Regular Conversion Alternate Function Remapping
150
Table 25. ADC2 External Trigger Injected Conversion Alternate Function Remapping
150
Timer Alternate Function Remapping
151
Table 26. ADC2 External Trigger Regular Conversion Alternate Function Remapping
151
Table 27. Timer 5 Alternate Function Remapping
151
Table 28. Timer 4 Alternate Function Remapping
151
Table 29. Timer 3 Alternate Function Remapping
151
USART Alternate Function Remapping
152
Table 30. Timer 2 Alternate Function Remapping
152
Table 31. Timer 1 Alternate Function Remapping
152
Table 32. USART3 Remapping
152
I2C 1 Alternate Function Remapping
153
SPI 1 Alternate Function Remapping
153
SPI 3 Alternate Function Remapping
153
Table 33. USART2 Remapping
153
Table 34. USART1 Remapping
153
Table 35. I2C1 Remapping
153
Table 36. SPI1 Remapping
153
Ethernet Alternate Function Remapping
154
AFIO Registers
154
Event Control Register (AFIO_EVCR)
154
Table 37. SPI3 Remapping
154
Table 38. ETH Remapping
154
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
155
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
158
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
159
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
159
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
160
GPIO and AFIO Register Maps
160
Table 39. GPIO Register Map and Reset Values
160
Table 40. AFIO Register Map and Reset Values
161
Interrupts and Events
162
Nested Vectored Interrupt Controller (NVIC)
162
Systick Calibration Value Register
162
Interrupt and Exception Vectors
162
Table 41. Vector Table for Connectivity Line Devices
163
Table 42. Vector Table for Other Stm32F10Xxx Devices
165
External Interrupt/Event Controller (EXTI)
167
Main Features
168
Block Diagram
168
Wakeup Event Management
168
Figure 19. External Interrupt/Event Controller Block Diagram
168
Functional Description
169
External Interrupt/Event Line Mapping
169
Figure 20. External Interrupt/Event GPIO Mapping
170
EXTI Registers
171
Interrupt Mask Register (EXTI_IMR)
171
Event Mask Register (EXTI_EMR)
171
Rising Trigger Selection Register (EXTI_RTSR)
172
Falling Trigger Selection Register (EXTI_FTSR)
172
Software Interrupt Event Register (EXTI_SWIER)
173
Pending Register (EXTI_PR)
173
EXTI Register Map
174
Table 43. External Interrupt/Event Controller Register Map and Reset Values
174
DMA Controller (DMA)
175
DMA Introduction
175
DMA Main Features
175
DMA Functional Description
176
DMA Transactions
176
Figure 21. DMA Block Diagram in Connectivity Line Devices
176
Arbiter
177
DMA Channels
177
Programmable Data Width, Data Alignment and Endians
179
Error Management
180
Interrupts
180
DMA Request Mapping
180
Table 45. DMA Interrupt Requests
180
Figure 22. DMA1 Request Mapping
181
Table 46. Summary of DMA1 Requests for each Channel
182
Table 47. Summary of DMA2 Requests for each Channel
183
Figure 23. DMA2 Request Mapping
183
DMA Registers
184
DMA Interrupt Status Register (DMA_ISR)
184
DMA Interrupt Flag Clear Register (DMA
185
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
186
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
187
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
188
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
188
DMA Register Map
189
Table 48. DMA Register Map and Reset Values
189
Analog-To-Digital Converter (ADC)
191
ADC Introduction
191
ADC Main Features
191
ADC Functional Description
192
Figure 24. Single ADC Block Diagram
193
ADC Clock
194
ADC On-Off Control
194
Channel Selection
194
Table 49. ADC Pins
194
Continuous Conversion Mode
195
Single Conversion Mode
195
Timing Diagram
195
Analog Watchdog
196
Figure 25. Timing Diagram
196
Figure 26. Analog Watchdog Guarded Area
196
Table 50. Analog Watchdog Channel Selection
196
Injected Channel Management
197
Scan Mode
197
Discontinuous Mode
198
Figure 27. Injected Conversion Latency
198
Calibration
199
Data Alignment
199
Figure 28. Calibration Timing Diagram
199
Channel-By-Channel Programmable Sample Time
200
Conversion on External Trigger
200
Figure 29. Right Alignment of Data
200
Figure 30. Left Alignment of Data
200
Table 51. External Trigger for Regular Channels for ADC1 and ADC2
201
Table 52. External Trigger for Injected Channels for ADC1 and ADC2
201
DMA Request
202
Table 53. External Trigger for Regular Channels for ADC3
202
Table 54. External Trigger for Injected Channels for ADC3
202
Dual ADC Mode
203
Figure 31. Dual ADC Block Diagram
204
Figure 32. Injected Simultaneous Mode on 4 Channels
205
Injected Simultaneous Mode
205
Regular Simultaneous Mode
205
Fast Interleaved Mode
206
Figure 33. Regular Simultaneous Mode on 16 Channels
206
Figure 34. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
206
Slow Interleaved Mode
206
Alternate Trigger Mode
207
Figure 35. Slow Interleaved Mode on 1 Channel
207
Figure 36. Alternate Trigger: Injected Channel Group of each ADC
207
Combined Regular Simultaneous + Alternate Trigger Mode
208
Combined Regular/Injected Simultaneous Mode
208
Figure 37. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
208
Independent Mode
208
Combined Injected Simultaneous + Interleaved
209
Figure 38. Alternate + Regular Simultaneous
209
Figure 39. Case of Trigger Occurring During Injected Conversion
209
Figure 40. Interleaved Single Channel with Injected Sequence CH11, CH12
209
Temperature Sensor
210
Figure 41. Temperature Sensor and VREFINT Channel Block Diagram
210
ADC Interrupts
211
Table 55. ADC Interrupts
211
ADC Registers
212
ADC Status Register (ADC_SR)
212
ADC Control Register 1 (ADC_CR1)
213
ADC Control Register 2 (ADC_CR2)
215
ADC Sample Time Register 1 (ADC_SMPR1)
218
ADC Sample Time Register 2 (ADC_SMPR2)
219
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
219
ADC Watchdog High Threshold Register (ADC_HTR)
220
ADC Watchdog Low Threshold Register (ADC_LTR)
220
ADC Regular Sequence Register 1 (ADC_SQR1)
220
ADC Regular Sequence Register 2 (ADC_SQR2)
221
ADC Regular Sequence Register 3 (ADC_SQR3)
222
ADC Injected Sequence Register (ADC_JSQR)
222
ADC Injected Data Register X (Adc_Jdrx) (X= 1
223
ADC Regular Data Register (ADC_DR)
223
11.12.15 ADC Register Map
224
Table 56. ADC Register Map and Reset Values
224
Digital-To-Analog Converter (DAC)
226
DAC Introduction
226
DAC Main Features
226
Table 57. DAC Pins
227
Figure 42. DAC Channel Block Diagram
227
DAC Functional Description
228
DAC Channel Enable
228
DAC Output Buffer Enable
228
DAC Data Format
228
DAC Conversion
229
Figure 43. Data Registers in Single DAC Channel Mode
229
Figure 44. Data Registers in Dual DAC Channel Mode
229
DAC Output Voltage
230
DAC Trigger Selection
230
Table 58. External Triggers
230
Figure 45. Timing Diagram for Conversion with Trigger Disabled TEN = 0
230
DMA Request
231
Noise Generation
231
Figure 46. DAC LFSR Register Calculation Algorithm
231
Triangle-Wave Generation
232
Figure 47. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
232
Figure 48. DAC Triangle Wave Generation
232
Dual DAC Channel Conversion
233
Independent Trigger Without Wave Generation
233
Figure 49. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
233
Independent Trigger with same LFSR Generation
234
Independent Trigger with Different LFSR Generation
234
Independent Trigger with same Triangle Generation
234
Independent Trigger with Different Triangle Generation
235
Simultaneous Software Start
235
Simultaneous Trigger Without Wave Generation
235
Simultaneous Trigger with same LFSR Generation
236
Simultaneous Trigger with Different LFSR Generation
236
Simultaneous Trigger with same Triangle Generation
236
Simultaneous Trigger with Different Triangle Generation
237
DAC Registers
237
DAC Control Register (DAC_CR)
237
DAC Software Trigger Register (DAC_SWTRIGR)
240
DAC Channel1 12-Bit Right-Aligned Data Holding Register
240
(Dac_Dhr12R1)
240
DAC Channel1 12-Bit Left Aligned Data Holding Register
241
(Dac_Dhr12L1)
241
DAC Channel1 8-Bit Right Aligned Data Holding Register
241
(Dac_Dhr8R1)
241
DAC Channel2 12-Bit Right Aligned Data Holding Register
241
(Dac_Dhr12R2)
241
DAC Channel2 12-Bit Left Aligned Data Holding Register
242
(Dac_Dhr12L2)
242
DAC Channel2 8-Bit Right-Aligned Data Holding Register
242
(Dac_Dhr8R2)
242
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
242
DUAL DAC 12-Bit Left Aligned Data Holding Register
243
(Dac_Dhr12Ld)
243
DUAL DAC 8-Bit Right Aligned Data Holding Register
243
(Dac_Dhr8Rd)
243
DAC Channel1 Data Output Register (DAC_DOR1)
244
DAC Channel2 Data Output Register (DAC_DOR2)
244
DAC Register Map
245
Table 59. DAC Register Map
245
ST STM32F107xx series Programming Manual (31 pages)
STM32F10xxx Flash memory microcontrollers
Brand:
ST
| Category:
Controller
| Size: 0 MB
Table of Contents
Table of Contents
2
Overview
6
Features
6
Flash Module Organization
6
Table 1. Flash Module Organization (Low-Density Devices)
7
Table 2. Flash Module Organization (Medium-Density Devices)
8
Table 3. Flash Module Organization (High-Density Devices)
8
Table 4. Flash Module Organization (Connectivity Line Devices)
9
Reading/Programming the Embedded Flash Memory
11
Introduction
11
Read Operation
11
Instruction Fetch
11
D-Code Interface
12
Flash Access Controller
12
Flash Program and Erase Controller (FPEC)
12
Key Values
12
Unlocking the Flash Memory
13
Main Flash Memory Programming
13
Flash Memory Erase
14
Option Byte Programming
16
Protections
17
Read Protection
17
Write Protection
18
Table 5. Flash Memory Protection Status
18
Option Byte Block Write Protection
19
Option Byte Description
19
Table 6. Option Byte Format
19
Table 7. Option Byte Organization
20
Table 8. Description of the Option Bytes
20
Register Descriptions
23
Flash Access Control Register (FLASH_ACR)
23
Table 9. Abbreviations
23
FPEC Key Register (FLASH_KEYR)
24
Flash OPTKEY Register (FLASH_OPTKEYR)
24
Flash Status Register (FLASH_SR)
25
Flash Control Register (FLASH_CR)
26
Flash Address Register (FLASH_AR)
27
Option Byte Register (FLASH_OBR)
27
Write Protection Register (FLASH_WRPR)
28
Flash Register Map
29
Table 10. Flash Interface - Register Map and Reset Values
29
Revision History
30
Table 11. Document Revision History
30
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