ST STM32F101 series Reference Manual page 1043

Ethernet (ETH): media access control (MAC) with DMA controller
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Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
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Ethernet MMC received frames with alignment error counter register
(ETH_MMCRFAECR)
Address offset: 0x0198
Reset value: 0x0000 0000
This register contains the number of frames received with alignment (dribble) error.
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Bits 31:0 RFAEC: Received frames alignment error counter
MMC received good unicast frames counter register (ETH_MMCRGUFCR)
Address offset: 0x01C4
Reset value: 0x0000 0000
This register contains the number of good unicast frames received.
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Bits 31:0 RGUFC: Received good unicast frames counter
1043/1128
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Bits 31:0 TGFC: Transmitted good frames counter
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Bits 31:0 RFCEC: Received frames CRC error counter
Received frames with CRC error counter
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Received frames with alignment error counter
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TGFC
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RFCEC
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RFAEC
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RGUFC
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DocID13902 Rev 15
9 8 7 6 5
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9 8 7 6 5
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9 8 7 6 5
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9 8 7 6 5
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RM0008
4 3 2 1 0
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4 3 2 1 0
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4 3 2 1 0
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4 3 2 1 0
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