ST STM32F101 series Reference Manual page 1045

Ethernet (ETH): media access control (MAC) with DMA controller
This register contains the 8-bit value by which the subsecond register is incremented. In
Coarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to
the system time every clock cycle of HCLK. In Fine update mode, the value in this register is
added to the system time whenever the accumulator gets an overflow.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 STSSI: System time subsecond increment
For example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2A).
Ethernet PTP time stamp high register (ETH_PTPTSHR)
Address offset: 0x0708
Reset value: 0x0000 0000
This register contains the most significant (higher) 32 time bits. This read-only register
contains the seconds system time value. The Time stamp high register, along with Time
stamp low register, indicates the current value of the system time maintained by the MAC.
Though it is updated on a continuous basis.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 STS: System time second
Ethernet PTP time stamp low register (ETH_PTPTSLR)
Address offset: 0x070C
Reset value: 0x0000 0000
This register contains the least significant (lower) 32 time bits. This read-only register
contains the subsecond system time value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r
1045/1128
Reserved
The value programmed in this register is added to the contents of the subsecond value of the
system time in every update.
r r r r r r
The value in this field indicates the current value in seconds of the System Time maintained
by the core.
r r r r r r r
STS
r r r r r r r
STSS
r r r r r r r
DocID13902 Rev 15
9 8 7 6 5
rw rw rw rw rw rw rw rw
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
RM0008
4 3 2 1 0
STSSI
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r