ST STM32F101 series Reference Manual page 1041

Ethernet (ETH): media access control (MAC) with DMA controller
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt mask register maintains the masks for interrupts
generated when the receive statistic counters reach half their maximum value. (MSB of the
counter is set.) It is a 32-bit wide register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Reserved
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 RGUFM: Received good unicast frames mask
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 RFAEM: Received frames alignment error mask
Bit 5 RFCEM: Received frame CRC error mask
Bits 4:0 Reserved, must be kept at reset value.
Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
Address offset: 0x0110
Reset value: 0x0000 0000
The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts
generated when the transmit statistic counters reach half their maximum value. (MSB of the
counter is set). It is a 32-bit wide register.
31 30 29 28 27 26 25 24 23 22
Reserved
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TGFM: Transmitted good frames mask
Bits 20:16 Reserved, must be kept at reset value.
1041/1128
Setting this bit masks the interrupt when the received, good unicast frames, counter
reaches half the maximum value.
Setting this bit masks the interrupt when the received frames, with alignment error, counter
reaches half the maximum value.
Setting this bit masks the interrupt when the received frames, with CRC error, counter
reaches half the maximum value.
21 20 19 18 17 16
Reserved
rw
Setting this bit masks the interrupt when the transmitted, good frames, counter reaches half
the maximum value.
17 16 15 14 13 12 11 10
Reserved
rw
15 14 13 12 11 10
rw rw
DocID13902 Rev 15
9 8 7 6 5 4 3
Reserved
rw rw
9 8 7 6 5 4 3
Reserved
RM0008
2 1 0
2 1 0