ST STM32F101 series Reference Manual page 1025

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MAC frame filter register (ETH_MACFFR)
Address offset: 0x0004
Reset value: 0x0000 0000
The MAC frame filter register contains the filter controls for receiving frames. Some of the
controls from this register go to the address check block of the MAC, which performs the
first level of address filtering. The second level of filtering is performed on the incoming
frame, based on other controls such as pass bad frames and pass control frames.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RA
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Bit 31 RA: Receive all
Bits 30:11 Reserved, must be kept at reset value.
Bit 10 HPF: Hash or perfect filter
Bit 9 SAF: Source address filter
Bit 8 SAIF: Source address inverse filtering
Bits 7:6 PCF: Pass control frames
Bit 5 BFD: Broadcast frames disable
1025/1128
Reserved
When this bit is set, the MAC receiver passes all received frames on to the application,
irrespective of whether they have passed the address filter. The result of the SA/DA filtering
is updated (pass or fail) in the corresponding bits in the receive status word. When this bit is
reset, the MAC receiver passes on to the application only those frames that have passed the
SA/DA address filter.
When this bit is set and if the HM or HU bit is set, the address filter passes frames that
match either the perfect filtering or the hash filtering.
When this bit is cleared and if the HU or HM bit is set, only frames that match the Hash filter
are passed.
The MAC core compares the SA field of the received frames with the values programmed in
the enabled SA registers. If the comparison matches, then the SAMatch bit in the RxStatus
word is set high. When this bit is set high and the SA filter fails, the MAC drops the frame.
When this bit is reset, the MAC core forwards the received frame to the application. It also
forwards the updated SA Match bit in RxStatus depending on the SA address comparison.
When this bit is set, the address check block operates in inverse filtering mode for the SA
address comparison. The frames whose SA matches the SA registers are marked as failing
the SA address filter.
When this bit is reset, frames whose SA does not match the SA registers are marked as
failing the SA address filter.
These bits control the forwarding of all control frames (including unicast and multicast
PAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE
in Flow Control Register[2].
00 or 01: MAC prevents all control frames from reaching the application
10: MAC forwards all control frames to application even if they fail the address filter
11: MAC forwards control frames that pass the address filter.
When this bit is set, the address filters filter all incoming broadcast frames.
When this bit is reset, the address filters pass all received broadcast frames.
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