ST STM32F101 series Reference Manual page 1036

RM0008
Bits 29:24 MBC: Mask byte control
– Bit 29: ETH_MACA1HR [15:8]
– Bit 28: ETH_MACA1HR [7:0]
– Bit 27: ETH_MACA1LR [31:24]
...
– Bit 24: ETH_MACA1LR [7:0]
Bits 23:16 Reserved, must be kept at reset value.
Bits 15:0 MACA1H: MAC address1 high [47:32]
Ethernet MAC address1 low register (ETH_MACA1LR)
Address offset: 0x004C
Reset value: 0xFFFF FFFF
The MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MACA1L: MAC address1 low [31:0]
Ethernet MAC address 2 high register (ETH_MACA2HR)
Address offset: 0x0050
Reset value: 0x0000 FFFF
The MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA MBC
rw rw rw rw rw rw rw rw
Ethernet (ETH): media access control (MAC) with DMA controller
These bits are mask control bits for comparison of each of the MAC address1 bytes. When
they are set high, the MAC core does not compare the corresponding byte of received
DA/SA with the contents of the MAC address1 registers. Each bit controls the masking of the
bytes as follows:
This field contains the upper 16 bits (47:32) of the 6-byte second MAC address.
This field contains the lower 32 bits of the 6-byte MAC address1. The content of this field is
undefined until loaded by the application after the initialization process.
Reserved
DocID13902 Rev 15
MACA1L
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
9 8 7 6 5 4 3
9 8 7 6 5 4 3
MACA2H
2 1 0
2 1 0
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