ST STM32F101 series Reference Manual page 1042

RM0008
Bit 15 TGFMSCM: Transmitted good frames more single collision mask
Bit 14 TGFSCM: Transmitted good frames single collision mask
Bits 13:0 Reserved, must be kept at reset value.
Ethernet MMC transmitted good frames after a single collision counter
Address offset: 0x014C
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after a single collision
in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 TGFSCC: Transmitted good frames single collision counter
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a
single collision in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
Ethernet (ETH): media access control (MAC) with DMA controller
Setting this bit masks the interrupt when the transmitted good frames after more than a
single collision counter reaches half the maximum value.
Setting this bit masks the interrupt when the transmitted good frames after a single collision
counter reaches half the maximum value.
register (ETH_MMCTGFSCCR)
r r r r r r
Transmitted good frames after a single collision counter.
r r r r r r
Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter
Transmitted good frames after more than a single collision counter
TGFSCC
r r r r r r r
TGFMSCC
r r r r r r r
DocID13902 Rev 15
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