Page 1 For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical Reference Manual. Related documents Available from www.arm.com: ■ Cortex™-M3 Technical Reference Manual Available from www.st.com: ■ STM32F101xx STM32F103xx datasheets ■ STM32F10xxx Flash programming manual September 2008 Rev 6 1/690 www.st.com...
Page 2: Table Of Contents
Contents RM0008 Contents Documentation conventions ....... . . 32 List of abbreviations for registers ....... 32 Glossary .
Page 3 RM0008 Contents Low-power modes ......... . 52 4.3.1 Slowing down system clocks .
Page 4 Contents RM0008 6.2.6 System clock (SYSCLK) selection ......75 6.2.7 Clock security system (CSS) ....... . . 75 6.2.8 RTC clock .
Page 5 RM0008 Contents 7.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) ..109 Alternate function I/O and debug configuration (AFIO) ... . . 110 7.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 .
Page 6 Contents RM0008 8.3.6 Pending register (EXTI_PR) ....... . 132 8.3.7 EXTI register map .
Page 7 RM0008 Contents 10.4 Calibration ..........156 10.5 Data alignment .
Page 8 Contents RM0008 11.2 DAC main features ......... 184 11.3 DAC functional description .
Page 9 RM0008 Contents 11.5.9 Dual DAC 12-bit Right-aligned Data Holding Register (DAC_DHR12RD) ........202 11.5.10 DUAL DAC 12-bit Left aligned Data Holding Register (DAC_DHR12LD) .
Page 10 Contents RM0008 12.4.3 Slave mode control register (TIMx_SMCR) ..... 250 12.4.4 DMA/Interrupt enable register (TIMx_DIER) ....253 12.4.5 Status register (TIMx_SR) .
Page 11 RM0008 Contents 13.3.14 Timers and external trigger synchronization ....300 13.3.15 Timer synchronization ........304 13.3.16 Debug mode .
Page 12 Contents RM0008 14.4.5 Event generation register (TIMx_EGR) ......339 14.4.6 Counter (TIMx_CNT) ........340 14.4.7 Prescaler (TIMx_PSC) .
Page 13 RM0008 Contents 16.4.5 IWDG register map ........359 Window watchdog (WWDG) .
Page 14 Contents RM0008 SDIO interface (SDIO) ........412 19.1 SDIO main features .
Page 15 RM0008 Contents 19.7.1 Command completion signal disable ......451 19.7.2 Command completion signal enable ......451 19.7.3 CE-ATA interrupt .
Page 16 Contents RM0008 20.5.2 Endpoint-specific registers ........490 20.5.3 Buffer descriptor table .
Page 17 RM0008 Contents 22.2.2 S features ..........545 22.3 SPI functional description .
Page 18 Contents RM0008 23.2 C main features ......... . 580 23.3 C functional description .
Page 19 RM0008 Contents 24.3.8 USART synchronous mode ....... . . 627 24.3.9 Single wire half duplex communication .
Page 20 Contents RM0008 26.6.2 Boundary scan TAP ........660 26.6.3 Cortex-M3 TAP .
Page 21 RM0008 Contents Revision history ......... . 680 21/690...
Page 22 List of tables RM0008 List of tables Table 1. Register boundary addresses ..........36 Table 2.
Page 23 RM0008 List of tables Table 49. ADC - register map and reset values ........182 Table 50.
Page 24 List of tables RM0008 Table 101. SDIO I/O definitions ........... . . 416 Table 102.
Page 25 RM0008 List of tables Table 153. Error calculation for programmed baud rates ........622 Table 154.
Page 26 List of figures RM0008 List of figures Figure 1. System architecture ............33 Figure 2.
Page 27 RM0008 List of figures Figure 49. Counter timing diagram with prescaler division change from 1 to 4 ....210 Figure 50. Counter timing diagram, internal clock divided by 1 ......211 Figure 51.
Page 28 List of figures RM0008 Figure 101. Counter timing diagram, internal clock divided by N......279 Figure 102.
Page 29 RM0008 List of figures Figure 151. RTC simplified block diagram ..........344 Figure 152.
Page 30 List of figures RM0008 Figure 203. Bit timing ............. . 515 Figure 204.
Page 31 RM0008 List of figures Figure 255. RTS flow control ............635 Figure 256.
Page 32: Documentation Conventions
Documentation conventions RM0008 Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value.
Page 33: Memory And Bus Architecture
RM0008 Memory and bus architecture Memory and bus architecture System architecture The main system consists of: ● Five masters: – Cortex™-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) ● Three slaves: –...
Page 34: Memory Organization
Memory and bus architecture RM0008 DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.
Page 35: Memory Map
RM0008 Memory and bus architecture Memory map Figure 2. Memory map Reserved 0xA000 1000 - 0xBFFF FFFF FSMC register 0xA000 0000 - 0xA000 0FFF FSMC bank4 PCCARD 0x9000 0000 - 0x9FFF FFFF FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4...
Page 36: Peripheral Memory Map
Memory and bus architecture RM0008 2.3.1 Peripheral memory map Table 1. Register boundary addresses Boundary address Peripheral Register map 0x4002 2400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF Section 3.4.4 on page 47 0x4002 2000 - 0x4002 23FF Flash memory interface 0x4002 1400 - 0x4002 1FFF Reserved...
Page 37 RM0008 Memory and bus architecture Table 1. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7800 - 0x4000 FFFF Reserved Section 11.5.14 on page 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF Power control PWR Section 4.4.3 on page 60 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 5.4.5 on page 66 0x4000 6800 - 0x4000 6BFF Reserved...
Page 38: Embedded Sram
Memory and bus architecture RM0008 2.3.2 Embedded SRAM The STM32F10xxx features 64 Kbytes of static SRAM. It can be accessed as bytes, half- words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. 2.3.3 Bit banding The Cortex™-M3 memory map includes two bit-band regions.
Page 39: Embedded Flash Memory
RM0008 Memory and bus architecture 2.3.4 Embedded Flash memory The high-performance Flash memory module has the following key features: ● Density of up to 512 Kbytes ● Memory organization: the Flash memory is organized as a main block and an information block: –...
Page 40: Table 3. Flash Module Organization (Medium-Density Devices)
Memory and bus architecture RM0008 Table 2. Flash module organization (low-density devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F Flash memory interface FLASH_CR...
Page 41: Table 4. Flash Module Organization (High-Density Devices)
RM0008 Memory and bus architecture Table 4. Flash module organization (High-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes Page 3 0x0800 1800 - 0x0800 1FFF...
Page 42 Memory and bus architecture RM0008 Reading Flash memory Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. Read accesses can be performed with the following configuration options: ●...
Page 43: Boot Configuration
Embedded boot loader The embedded boot loader is used to reprogram the Flash memory using the USART1 serial interface. This program is located in the System memory and is programmed by ST during production. For further details please refer to AN2606.
Page 44: Crc Calculation Unit
CRC calculation unit RM0008 CRC calculation unit Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 45: Crc Functional Description
RM0008 CRC calculation unit CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ●...
Page 46: Independent Data Register (Crc_Idr)
CRC calculation unit RM0008 3.4.2 Independent Data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved IDR[7:0] Reserved Bits 31:8 Reserved Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
Page 47: Crc Register Map
RM0008 CRC calculation unit 3.4.4 CRC register map The following table provides the CRC register map and reset values. Table 6. CRC calculation unit register map and reset values Offset Register 31-24 23-16 15-8 CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register...
Page 48: Power Control (Pwr)
Power control (PWR) RM0008 Power control (PWR) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 49: Independent A/D Converter Supply And Reference Voltage
RM0008 Power control (PWR) 4.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. ● The ADC voltage supply input is available on a separate V pin.
Page 50: Voltage Regulator
Power control (PWR) RM0008 When the backup domain is supplied by V (analog switch connected to V ), the following functions are available: ● PC14 and PC15 can be used as either GPIO or LSE pins ● PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 5: Backup registers (BKP) on page Note:...
Page 51: Programmable Voltage Detector (Pvd)
RM0008 Power control (PWR) Figure 5. Power on reset/power down reset waveform 40 mV hysteresis Temporization RSTTEMPO Reset 4.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR).
Page 52: Low-Power Modes
Power control (PWR) RM0008 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 53: Peripheral Clock Gating
RM0008 Power control (PWR) 4.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 54: Stop Mode
Power control (PWR) RM0008 Table 9. Sleep-on-exit Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 1 Refer to the Cortex™-M3 System Control register. Mode exit Interrupt: refer to Table 36: Vector table.
Page 55: Standby Mode
RM0008 Power control (PWR) When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. Table 10.
Page 56: Table 11. Standby Mode
Power control (PWR) RM0008 Exiting Standby mode The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR).
Page 57: Auto-Wakeup (Awu) From Low-Power Mode
RM0008 Power control (PWR) 4.3.6 Auto-wakeup (AWU) from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR):...
Page 58 Power control (PWR) RM0008 Bits 7:5 PLS[2:0]: PVD level selection. These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V Note: Refer to the electrical characteristics of the datasheet for more details.
Page 59: Power Control/Status Register (Pwr_Csr)
RM0008 Power control (PWR) 4.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved Res. Reserved EWUP Reserved PVDO...
Page 60: Pwr Register Map
Power control (PWR) RM0008 4.4.3 PWR register map The following table summarizes the PWR registers. Table 12. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reserved Reset value PWR_CSR 0x004 Reserved Reserved Reset value Refer to Table 1 on page 36 for the register boundary addresses.
Page 61: Backup Registers (Bkp)
RM0008 Backup registers (BKP) Backup registers (BKP) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 62: Bkp Functional Description
Backup registers (BKP) RM0008 BKP functional description 5.3.1 Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR).
Page 63: Bkp Registers
RM0008 Backup registers (BKP) BKP registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 D[15:0] Bits 15:0 D[15:0] Backup data.
Page 64: Backup Control Register (Bkp_Cr)
Backup registers (BKP) RM0008 Bit 8 ASOE Alarm or Second Output Enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set.
Page 65: Backup Control/Status Register (Bkp_Csr)
RM0008 Backup registers (BKP) 5.4.4 Backup control/status register (BKP_CSR) Address offset: 0x34 Reset value: 0x0000 0000 Reserved Reserved TPIE Res. Res. Bits 15:10 Reserved, always read as 0. Bit 9 TIF Tamper Interrupt Flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt).
Page 66: Bkp Register Map
Backup registers (BKP) RM0008 5.4.5 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 13. BKP - register map and reset values Offset Register 0x00 Reserved BKP_DR1 D[15:0] 0x04 Reserved Reset value BKP_DR2 D[15:0] 0x08...
Page 67 RM0008 Backup registers (BKP) Table 13. BKP - register map and reset values (continued) Offset Register BKP_DR12 D[15:0] 0x44 Reserved Reset value BKP_DR13 D[15:0] 0x48 Reserved Reset value BKP_DR14 D[15:0] 0x4C Reserved Reset value BKP_DR15 D[15:0] 0x50 Reserved Reset value BKP_DR16 D[15:0] 0x54...
Page 68 Backup registers (BKP) RM0008 Table 13. BKP - register map and reset values (continued) Offset Register 0x88 BKP_DR29 D[15:0] Reserved Reset value BKP_DR30 D[15:0] 0x8C Reserved Reset value BKP_DR31 D[15:0] 0x90 Reserved Reset value BKP_DR32 D[15:0] 0x94 Reserved Reset value BKP_DR33 D[15:0] 0x98...
Page 69: Reset And Clock Control (Rcc)
RM0008 Reset and clock control (RCC) Reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 70: Power Reset
Reset and clock control (RCC) RM0008 For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual. 6.1.2 Power reset A power reset is generated when one of the following events occurs: Power-on/power-down reset (POR/PDR reset) When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure...
Page 71: Figure 8. Clock Tree
RM0008 Reset and clock control (RCC) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Figure 8. Clock tree USBCLK 48 MHz to USB interface Prescaler /1, 1.5 I2S3CLK to I2S3 Peripheral clock I2S2CLK enable...
Page 72: Hse Clock
Reset and clock control (RCC) RM0008 configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The timer clock frequencies are automatically fixed by hardware. There are two cases: if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
Page 73: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 74: Lse Clock
Reset and clock control (RCC) RM0008 The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed. An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register...
Page 75: System Clock (Sysclk) Selection
RM0008 Reset and clock control (RCC) oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: Enable TIM5 timer and configure channel4 in input capture mode Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
Page 76: Watchdog Clock
Reset and clock control (RCC) RM0008 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 77: Rcc Registers
RM0008 Reset and clock control (RCC) RCC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 6.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access Reserved PLLON...
Page 78: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0008 Bit 16 HSEON External High Speed clock enable Set and reset by software. Reset by hardware to stop the external 1-25MHz oscillator when entering in Stop and Standby mode. This bit can not be reset if the external 1-25 MHz oscillator is used directly or indirectly as system clock or is selected to become the system clock.
Page 79 RM0008 Reset and clock control (RCC) Bits 31:26 Reserved, always read as 0. Bits 26:24 MCO Microcontroller clock output Set and reset by software. 0xx: No clock 100: System clock selected 101: Internal 8 MHz RC oscillator clock selected 110: External 1-25 MHz oscillator clock selected 111: PLL clock divided by 2 selected Note: This clock output could have some truncated cycle at startup or during MCO clock source switching.
Page 80 Reset and clock control (RCC) RM0008 Bits 14:14 ADCPRE ADC prescaler Set and reset by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by 8 Bits 13:11 PPRE2 APB high-speed prescaler (APB2) Set and reset by software to control APB High speed clocks division factor.
Page 81: Clock Interrupt Register (Rcc_Cir)
RM0008 Reset and clock control (RCC) 6.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved CSSC Reserved RDYC RDYC RDYC RDYC RDYC Res. Res. Reserved CSSF Reserved RDYIE RDYIE RDYIE...
Page 82 Reset and clock control (RCC) RM0008 Bit 16 LSIRDYC LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. 0: LSIRDYF not cleared 1: LSIRDYF cleared Bits 15:13 Reserved, always read as 0. Bit 12 PLLRDYIE PLL ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL lock.
Page 83: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0008 Reset and clock control (RCC) Bit 2 HSIRDYF HSI ready interrupt flag Reset by software by writing HSIRDYC. Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF LSE ready interrupt flag Reset by software by writing LSERDYC.
Page 84 Reset and clock control (RCC) RM0008 Bit 12 SPI1RST SPI 1 reset Set and reset by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST TIM1 timer reset Set and reset by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST ADC 2 interface reset Set and reset by software.
Page 85: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0008 Reset and clock control (RCC) Bit 2 IOPARST I/O port A reset Set and reset by software. 0: No effect 1: Reset I/O port A Bit 1 Reserved, always read as 0. Bit 0 AFIORST Alternate function I/O reset Set and reset by software.
Page 86 Reset and clock control (RCC) RM0008 Bit 23 USBRST USB reset Set and reset by software. 0: No effect 1: Reset USB Bit 22 I2C2RST I2C 2 reset Set and reset by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST I2C 1 reset Set and reset by software.
Page 87: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0008 Reset and clock control (RCC) Bit 5 TIM7RST Timer 7 reset Set and reset by software. 0: No effect 1: Reset timer 7 Bit 4 TIM6RST Timer 6 reset Set and reset by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST Timer 5 reset Set and reset by software.
Page 88: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0008 Bit 8 FSMCEN FSMC clock enable Set and reset by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN CRC clock enable Set and reset by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5...
Page 89 RM0008 Reset and clock control (RCC) Bits 31:16 Reserved, always read as 0. Bit 15 ADC3EN ADC 3 interface clock enable Set and reset by software. 0: ADC 3 interface clock disabled 1: ADC 3 interface clock enabled Bit 14 USART1EN USART1 clock enable Set and reset by software.
Page 90: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Reset and clock control (RCC) RM0008 Bit 4 IOPCEN I/O port C clock enable Set and reset by software. 0: I/O port C clock disabled 1:I/O port C clock enabled Bit 3 IOPBEN I/O port B clock enable Set and reset by software. 0: I/O port B clock disabled 1:I/O port B clock enabled Bit 2 IOPAEN I/O port A clock enable...
Page 91 RM0008 Reset and clock control (RCC) Bit 27 BKPEN Backup interface clock enable Set and reset by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 Reserved, always read as 0. Bit 25 CANEN CAN clock enable Set and reset by software.
Page 92 Reset and clock control (RCC) RM0008 Bit 14 SPI2EN SPI 2 clock enable Set and reset by software. 0: SPI 2 clock disabled 1: SPI 2 clock enabled Bits 13:12 Reserved, always read as 0. Bit 11 WWDGEN Window Watchdog clock enable Set and reset by software.
Page 93: Backup Domain Control Register (Rcc_Bdcr)
RM0008 Reset and clock control (RCC) 6.3.9 Backup domain control register (RCC_BDCR) Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register...
Page 94: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0008 Bit 2 LSEBYP External Low Speed oscillator Bypass Set and reset by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY External Low Speed oscillator Ready Set and reset by hardware to indicate when the external 32 kHz oscillator is stable.
Page 95 RM0008 Reset and clock control (RCC) Bit 28 SFTRSTF Software Reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF POR/PDR reset flag Reset by software by writing the RMVF bit.
Page 96: Rcc Register Map
Reset and clock control (RCC) RM0008 6.3.11 RCC register map The following table gives the RCC register map and the reset values. Table 14. RCC - register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x000 Reserved Reserved Reset value PPRE2 PPRE1 RCC_CFGR...
Page 97: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 98: Figure 10. Basic Structure Of A Standard I/O Port Bit
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 10. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode...
Page 99: General-Purpose I/O (Gpio)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 15. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 Register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull don’t care Alternate Function Table 16 output Open-drain don’t care...
Page 100: External Interrupt/Wakeup Lines
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to: ● Section 8.2: External interrupt/event controller (EXTI) on page 126 ●...
Page 101: Input Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.1.7 Input configuration When the I/O Port is programmed as Input: ● The Output Buffer is disabled ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): ●...
Page 102: Alternate Function Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 13. Output configuration Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Output driver Protection diode P-MOS Output control Read/write N-MOS Push-pull or Open-drain ai14784 1. V is a potential specific to five-volt tolerant I/Os and different from V DD_FT 7.1.9...
Page 103: Analog Input Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 14. Alternate function configuration Alternate Function Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Input driver I/O pin Write Output driver Protection diode P-MOS Output control N-MOS Read/write push-pull or...
Page 104: Figure 15. High Impedance-Analog Input Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 15. High impedance-analog input configuration Analog Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Protection diode Read/write From on-chip peripheral ai14786 104/690...
Page 105: Gpio Registers
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0] MODE7[1:0] CNF6[1:0]...
Page 106: Port Configuration Register High (Gpiox_Crh) (X=A..g
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, 23:22, CNFy[1:0]: Port x configuration bits (y= 8 ..
Page 107: Port Input Data Register (Gpiox_Idr) (X=A..g
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.2.3 Port input data register (GPIOx_IDR) (x=A..G) Address offset: 0x08h Reset value: 0x0000 XXXX Reserved IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Bits 31:16 Reserved, always read as 0.
Page 108: Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..g
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) Address offset: 0x10 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only.
Page 109: Port Configuration Lock Register (Gpiox_Lckr) (X=A..g
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
Page 110: Alternate Function I/O And Debug Configuration (Afio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Alternate function I/O and debug configuration (AFIO) To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR) on page...
Page 111: Table 18. Debug Interface Signals
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 18. Debug interface signals Alternate function GPIO port JTMS / SWDIO PA13 JTCK / SWCLK PA14 JTDI PA15 JTDO / TRACESWO JNTRST TRACECK TRACED0 TRACED1 TRACED2 TRACED3 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register...
Page 112: Adc Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.3.5 ADC alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 20. ADC1 external trigger injected conversion alternate function remapping Alternate function ADC1_ETRGINJ_REMAP = 0 ADC1_ETRGINJ_REMAP = 1 ADC1 external trigger injected ADC1 external trigger injected ADC1 external trigger injected...
Page 113: Table 25. Timer 4 Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 25. Timer 4 alternate function remapping Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1 TIM4_CH1 PD12 TIM4_CH2 PD13 TIM4_CH3 PD14 TIM4_CH4 PD15 1. Remap available only for 100-pin and for 144-pin package. Table 26.
Page 114: Usart Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 28. Timer 1 alternate function remapping Alternate functions TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = mapping “00” (no remap) “01” (partial remap) “11” (full remap) TIM1_ETR PA12 TIM1_CH1 TIM1_CH2 PE11 TIM1_CH3 PA10 PE13 TIM1_CH4 PA11...
Page 115: I2C 1 Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 31. USART1 remapping Alternate function USART1_REMAP = 0 USART1_REMAP = 1 USART1_TX USART1_RX PA10 7.3.8 I2C 1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 32. I2C1 remapping Alternate function I2C1_REMAP = 0...
Page 116: Event Control Register (Afio_Evcr)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.4.1 Event control register (AFIO_EVCR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved EVOE PORT[2:0] PIN[3:0] Res. Bits 31:8 Reserved Bit 7 EVOE Event Output Enable Set and cleared by software. When set the EVENTOUT Cortex output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.
Page 117: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 ADC2_ ADC2_ ADC1_ ADC1_ TIM5CH SWJ_ ETRGR ETRGIN ETRGR ETRGIN Reserved Reserved 4_IREM CFG[2:0] EG_RE J_REM EG_RE J_REM Res.
Page 118 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bit 15 PD01_REMAP Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT.
Page 119: External Interrupt Configuration Register 1 (Afio_Exticr1)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 5:4 USART3_REMAP[1:0] USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Page 120: External Interrupt Configuration Register 2 (Afio_Exticr2)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 7.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) Address offset: 0x0C Reset value: 0x0000 Reserved EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 121: External Interrupt Configuration Register 4 (Afio_Exticr4)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) Address offset: 0x14 Reset value: 0x0000 Reserved EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 122: Table 35. Afio Register Map And Reset Values
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 35. AFIO register map and reset values Offset Register AFIO_EVCR PORT[2:0] PIN[3:0] 0x00 Reserved Reset value AFIO_MAPR Reserved 0x04 Reserved Reset value AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0x08 Reserved Reset value AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0]...
Page 123: Interrupts And Events
RM0008 Interrupts and events Interrupts and events Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. This Section applies to the whole STM32F10xxx family, unless otherwise specified.
Page 124: Table 36. Vector Table
Interrupts and events RM0008 Table 36. Vector table (continued) Type of Acronym Description Address priority 0x0000_001C - Reserved 0x0000_002B System service call via SWI settable SVCall 0x0000_002C instruction settable Debug Monitor Debug Monitor 0x0000_0030 Reserved 0x0000_0034 settable PendSV Pendable request for system service 0x0000_0038 settable SysTick...
Page 125 RM0008 Interrupts and events Table 36. Vector table (continued) Type of Acronym Description Address priority settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4 TIM1 Trigger and Commutation settable TIM1_TRG_COM 0x0000_00A8 interrupts settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC settable TIM2...
Page 126: External Interrupt/Event Controller (Exti)
Interrupts and events RM0008 Table 36. Vector table (continued) Type of Acronym Description Address priority settable TIM7 TIM7 global interrupt 0x0000_011C settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128 DMA2 Channel4 and DMA2 settable...
Page 127: Wakeup Event Management
RM0008 Interrupts and events Figure 16. External interrupt/event controller block diagram AMBA APB bus PCLK2 Peripheral interface Rising Falling Software Interrupt Pending trigger trigger interrupt mask request selection selection event register register register register register To NVIC Interrupt Controller Edge detect Pulse Input circuit...
Page 128: External Interrupt/Event Line Mapping
Interrupts and events RM0008 An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Hardware interrupt selection To configure the 19 lines as interrupt sources, use the following procedure: ● Configure the mask bits of the 19 Interrupt lines (EXTI_IMR) ●...
Page 129: Figure 17. External Interrupt/Event Gpio Mapping
RM0008 Interrupts and events Figure 17. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 EXTI15 PD15 PE15 PF15 PG15 The three other EXTI lines are connected as follows: ●...
Page 130: Exti Registers
Interrupts and events RM0008 registers EXTI Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 8.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved MR18 MR17 MR16 Res. MR15 MR14 MR13 MR12...
Page 131: Rising Trigger Selection Register (Exti_Rtsr)
RM0008 Interrupts and events 8.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Reserved TR18 TR17 TR16 Res. TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:19 Reserved, must be kept at reset value (0). Bits 18:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 132: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0008 8.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER Reserved Res. SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:19 Reserved, must be kept at reset value (0).
Page 133: Exti Register Map
RM0008 Interrupts and events 8.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Table 37. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] 0x00 Reserved Reset value EXTI_EMR MR[18:0] 0x04 Reserved Reset value...
Page 134: Dma Controller (Dma)
DMA controller (DMA) RM0008 DMA controller (DMA) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 135: Dma Functional Description
RM0008 DMA controller (DMA) Figure 18. DMA block diagram ICode Flash FLITF DCode Cortex-M3 Sys tem SRAM DMA1 Ch.1 FSMC Ch.2 SDIO AHB S ystem Bridge 2 Ch.7 APB2 Bridge 1 APB1 Arbiter USART1 TIM2 USART2 DMA request SPI1 USART3 TIM3 AHB Slave ADC1...
Page 136: Arbiter
DMA controller (DMA) RM0008 In summary, each DMA transfer consists of three operations: ● A load from the peripheral data register or a location in memory addressed through the DMA_CMARx register ● A store of the data loaded to the peripheral data register or a location in memory addressed through the DMA_CMARx register ●...
Page 137: Error Management
RM0008 DMA controller (DMA) Channel configuration procedure The following sequence should be followed to configure a DMA channelx (where x is the channel number). Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. Set the memory address in the DMA_CMARx register.
Page 138: Interrupts
DMA controller (DMA) RM0008 9.3.5 Interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 38. DMA interrupt requests Interrupt event Event flag Enable Control bit HTIF HTIE...
Page 139: Figure 19. Dma1 Request Mapping
RM0008 DMA controller (DMA) Figure 19. DMA1 request mapping Fixed hardware priority Peripheral request signals High priority ADC1 HW request 1 Channel 1 TIM2_CH3 TIM4_CH1 SW trigger (MEM2MEM bit) Channel 1 EN bit USART3_TX TIM1_CH1 HW request 2 Channel 2 TIM2_UP TIM3_CH3 SW trigger (MEM2MEM bit)
Page 140: Table 39. Summary Of Dma1 Requests For Each Channel
DMA controller (DMA) RM0008 Table 39. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI/I SPI1_RX SPI1_TX SPI/I2S2_RX SPI/I2S2_TX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C2_TX I2C2_RX I2C1_TX...
Page 141: Table 40. Summary Of Dma2 Requests For Each Channel
RM0008 DMA controller (DMA) Figure 20. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 HIGH PRIORITY TIM5_TRIG HW request 1 Channel 1 TIM8_CH3 TIM8_UP SW trigger (MEM2MEM bit) SPI/I2S3_RX Channel 1 EN bit TIM8_CH4 HW request 2 TIM8_TRIG Channel 2 TIM8_COM TIM5_CH3...
Page 142: Dma Registers
DMA controller (DMA) RM0008 DMA registers Refer to Section 1.1 on page 32 for a list of abbreviations used in the register descriptions. Note: In the following registers, all bits relative to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels. 9.4.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00...
Page 143: Dma Interrupt Flag Clear Register (Dma
RM0008 DMA controller (DMA) 9.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF Reserved CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF...
Page 144: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
DMA controller (DMA) RM0008 9.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) Address offset: 0x08 + 20d × Channel number Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC TEIE HTIE TCIE Res. Bits 31:15 Reserved, always read as 0.
Page 145: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
RM0008 DMA controller (DMA) Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable...
Page 146: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
DMA controller (DMA) RM0008 9.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) Address offset: 0x10 + dx20 × Channel number Reset value: 0x0000 0000 Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. 9.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) Address offset: 0x14 + dx20 ×...
Page 147 RM0008 DMA controller (DMA) Table 41. DMA - register map and reset values (continued) Offset Register DMA_CPAR2 PA[31:0] 0x024 Reset value DMA_CMAR2 MA[31:0] 0x028 Reset value 0x02C Reserved PSIZE DMA_CCR3 SIZE [1:0] [1:0] 0x030 Reserved [1:0] Reset value DMA_CNDTR3 NDT[15:0] 0x034 Reserved Reset value...
Page 148 DMA controller (DMA) RM0008 Table 41. DMA - register map and reset values (continued) Offset Register PSIZE DMA_CCR6 SIZE [1:0] [1:0] 0x06C Reserved [1:0] Reset value DMA_CNDTR6 NDT[15:0] 0x070 Reserved Reset value DMA_CPAR6 PA[31:0] 0x074 Reset value DMA_CMAR6 MA[31:0] 0x078 Reset value 0x07C Reserved...
Page 149: Analog-To-Digital Converter (Adc)
RM0008 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 150: Adc Functional Description
Analog-to-digital converter (ADC) RM0008 10.3 ADC functional description Figure 21 shows a single ADC block diagrams and Table 42 gives the ADC pin description. Figure 21. Single ADC block diagram Interrupt Flags enable bits End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE...
Page 151: Adc On-Off Control
RM0008 Analog-to-digital converter (ADC) Table 42. ADC pins Name Signal type Remarks The higher/positive reference voltage for the ADC, Input, analog reference ≤ ≤ REF+ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤ ≤ 2.4 V (3.6 V) Input, analog reference...
Page 152: Single Conversion Mode
Analog-to-digital converter (ADC) RM0008 Temperature sensor/V internal channels REFINT The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage V is connected to ADCx_IN17. These two internal channels can be selected REFINT and converted as injected or regular channels. Note: The sensor and V are only available on the master ADC1 peripheral.
Page 153: Analog Watchdog
RM0008 Analog-to-digital converter (ADC) Figure 22. Timing diagram ADC_CLK SET ADON Start 1st conversion Start next conversion ADC power on ADC Conversion Next ADC Conversion STAB Conversion Time (total conv time) Software resets EOC bit 10.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold.
Page 154: Scan Mode
Analog-to-digital converter (ADC) RM0008 10.3.8 Scan mode This mode is used to scan a group of analog channels. Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels).
Page 155: Discontinuous Mode
RM0008 Analog-to-digital converter (ADC) Figure 24. Injected conversion latency ADC clock Inj. event Reset ADC max latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 10.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register.
Page 156: Calibration
Analog-to-digital converter (ADC) RM0008 Example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and EOC and JEOC events generated 4th trigger: channel 1 Note: When all injected channels are converted, the next trigger starts the conversion of the first injected channel.
Page 157: Channel-By-Channel Programmable Sample Time
RM0008 Analog-to-digital converter (ADC) Figure 26. Right alignment of data Injected group SEXT SEXT SEXT SEXT Regular group Figure 27. Left alignment of data Injected group SEXT Regular group 10.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us- ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers.
Page 158: Table 44. External Trigger For Regular Channels For Adc1 And Adc2
Analog-to-digital converter (ADC) RM0008 Table 44. External trigger for regular channels for ADC1 and ADC2 Source Type EXTSEL[2:0] TIM1_CC1 event TIM1_CC2 event TIM1_CC3 event Internal signal from on-chip timers TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event EXTI line11/TIM8_TRGO External pin/Internal signal from (1)(2) event on-chip timers...
Page 159: Dma Request
RM0008 Analog-to-digital converter (ADC) Table 46. External trigger for regular channels for ADC3 Source Connection type EXTSEL[2:0] TIM3_CC1 event TIM2_CC3 event TIM1_CC3 event Internal signal from on-chip TIM8_CC1 event timers TIM8_TRGO event TIM5_CC1 event TIM5_CC3 event SWSTART Software control bit Table 47.
Page 160: Dual Adc Mode
Analog-to-digital converter (ADC) RM0008 10.9 Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 28). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register.
Page 161: Figure 28. Dual Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 28. Dual ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers (4 x 16 bits) Regular ADC2 (Slave) channels injected channels internal triggers Regular data register (16 bits)* Injected data registers (4 x 16 bits) ADCx_IN0 Regular...
Page 162: Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0008 10.9.1 Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits ADC1_CR2 in the register). A simultaneous trigger is provided to ADC2. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
Page 163: Fast Interleaved Mode
RM0008 Analog-to-digital converter (ADC) Figure 30. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 10.9.3 Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1.
Page 164: Alternate Trigger Mode
Analog-to-digital converter (ADC) RM0008 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
Page 165: Independent Mode
RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: ● When the 1st trigger occurs, the first injected channel in ADC1 is converted. ● When the 2nd trigger arrives, the first injected channel in ADC2 are converted ●...
Page 166: Combined Injected Simultaneous + Interleaved
Analog-to-digital converter (ADC) RM0008 Figure 35. Alternate + Regular simultaneous 1st trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored.
Page 167: Temperature Sensor
RM0008 Analog-to-digital converter (ADC) 10.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs.
Page 168: Adc Interrupts
Analog-to-digital converter (ADC) RM0008 Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time of 17.1 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger).
Page 169: Adc Registers
RM0008 Analog-to-digital converter (ADC) 10.12 ADC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 10.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved STRT JSTRT JEOC Res.
Page 170: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0008 10.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 AWDE JAWD Reserved Reserved DUALMOD[3:0] Res. Res. JDISC DISC JAUT JEOC DISCNUM[2:0] SCAN AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software.
Page 171 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
Page 172: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0008 Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog Watchdog. 00000: ADC analog input Channel0 00001: ADC analog input Channel1 ..
Page 173 RM0008 Analog-to-digital converter (ADC) Bit 20 EXTTRIG: External Trigger Conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group:...
Page 174 Analog-to-digital converter (ADC) RM0008 Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event...
Page 175: Adc Sample Time Register 1 (Adc_Smpr1)
RM0008 Analog-to-digital converter (ADC) Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state. Conversion starts when this bit holds a value of 1 and a 1 is written to it.
Page 176: Adc Sample Time Register 2 (Adc_Smpr2)
Analog-to-digital converter (ADC) RM0008 10.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 177: Adc Watchdog High Threshold Register (Adc_Htr)
RM0008 Analog-to-digital converter (ADC) 10.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0000 Reserved Reserved HT[11:0] Res. Bits 31:12 Reserved, must be kept cleared. Bits 11:0 HT[11:0] Analog watchdog high threshold These bits are written by software to define the high threshold for the Analog Watchdog. 10.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28...
Page 178: Adc Regular Sequence Register 1 (Adc_Sqr1)
Analog-to-digital converter (ADC) RM0008 10.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 Reserved L[3:0] SQ16[4:1] Res. SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] Bits 31:24 Reserved, must be kept cleared. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence.
Page 179: Adc Regular Sequence Register 3 (Adc_Sqr3)
RM0008 Analog-to-digital converter (ADC) Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence 10.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 Reserved...
Page 180: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0008 10.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Reserved JL[1:0] JSQ4[4:1] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept cleared. Bits 21:20 JL[1:0]: Injected Sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 181: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0008 Analog-to-digital converter (ADC) 10.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 Reserved JDATA[15:0] Bits 31:16 Reserved, must be kept cleared. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 26 Figure...
Page 182: 10.12.15 Adc Register Map
Analog-to-digital converter (ADC) RM0008 10.12.15 ADC register map The following table summarizes the ADC registers. Table 49. ADC - register map and reset values Offset Register ADC_SR 0x00 Reserved Reset value DUALMOD DISC ADC_CR1 AWDCH[4:0] 0x04 Reserved [3:0] NUM [2:0] Reset value EXTSEL JEXTSEL...
Page 183 RM0008 Analog-to-digital converter (ADC) Table 49. ADC - register map and reset values (continued) Offset Register ADC_JDR1 JDATA[15:0] 0x3C Reserved Reset value ADC_JDR2 JDATA[15:0] 0x40 Reserved Reset value ADC_JDR3 JDATA[15:0] 0x44 Reserved Reset value ADC_JDR4 JDATA[15:0] 0x48 Reserved Reset value ADC_DR ADC2DATA[15:0] Regular DATA[15:0]...
Page 184: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0008 Digital-to-analog converter (DAC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 185: Table 50. Dac Pins
RM0008 Digital-to-analog converter (DAC) Figure 39. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 186: Dac Functional Description
Digital-to-analog converter (DAC) RM0008 11.3 DAC functional description 11.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 187: Dac Conversion
RM0008 Digital-to-analog converter (DAC) Figure 40. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 ● Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) –...
Page 188: Dac Output Voltage
Digital-to-analog converter (DAC) RM0008 Figure 42. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 11.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 189: Dma Request
RM0008 Digital-to-analog converter (DAC) Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to- DAC_DORx register transfer. 11.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
Page 190: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0008 Figure 44. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xD55 0xAAA SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. 11.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
Page 191: Dual Dac Channel Conversion
RM0008 Digital-to-analog converter (DAC) Figure 46. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 192: Independent Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0008 11.4.2 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 193: Independent Trigger With Different Triangle Generation
RM0008 Digital-to-analog converter (DAC) DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later).
Page 194: Simultaneous Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0008 11.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 195: Simultaneous Trigger With Different Triangle Generation
RM0008 Digital-to-analog converter (DAC) added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 11.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: ●...
Page 196: Dac Registers
Digital-to-analog converter (DAC) RM0008 11.5 DAC registers 11.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved MAMP2[3:0] WAVE2[1:0] TSEL2[2:0] TEN2 BOFF2 Reserved MAMP1[3:0] WAVE1[1:0] TSEL1[2:0] TEN1 BOFF1 Bits 31:29 Reserved. Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software.
Page 197 RM0008 Digital-to-analog converter (DAC) Bits 21:19 TSEL2[2:0]: DAC channel2 Trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
Page 198 Digital-to-analog converter (DAC) RM0008 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) Bits 5:3 TSEL1[2:0]: DAC channel1 Trigger selection These bits select the external event used to trigger DAC channel1 000: Timer 6 TRGO event...
Page 199: Dac Software Trigger Register (Dac_Swtrigr)
RM0008 Digital-to-analog converter (DAC) 11.5.2 DAC Software Trigger Register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved Reserved SWTRI SWTRI Bits 31:2 Reserved. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value...
Page 200: Dac Channel1 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0008 11.5.4 DAC channel1 12-bit Left aligned Data Holding Register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved. Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit Left aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved.
Page 201: Dac Channel2 12-Bit Right Aligned Data Holding Register
RM0008 Digital-to-analog converter (DAC) 11.5.6 DAC channel2 12-bit Right aligned Data Holding Register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved Reserved DACC2DHR[11:0] Bits 31:12 Reserved. DACC2DHR[11:0]: DAC channel2 12-bit Right aligned data Bits 11:0 These bits are written by software which specify 12-bit data for DAC channel2. 11.5.7 DAC channel2 12-bit Left aligned Data Holding Register (DAC_DHR12L2)
Page 202: Dac Channel2 8-Bit Right-Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0008 11.5.8 DAC channel2 8-bit Right-aligned Data Holding Register (DAC_DHR8R2) Address offset: 0x1C Reset value: 0x0000 0000 Reserved Reserved DACC2DHR[7:0] Bits 31:8 Reserved. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit Right aligned data These bits are written by software which specify 8-bit data for DAC channel2. 11.5.9 Dual DAC 12-bit Right-aligned Data Holding Register (DAC_DHR12RD)
Page 203: Dual Dac 12-Bit Left Aligned Data Holding Register
RM0008 Digital-to-analog converter (DAC) 11.5.10 DUAL DAC 12-bit Left aligned Data Holding Register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DACC2DHR[11:0]: DAC channel2 12-bit Left aligned data Bits 31:20 These bits are written by software which specify 12-bit data for DAC channel2. Bits 19:16 Reserved.
Page 204: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC) RM0008 11.5.12 DAC channel1 Data Output Register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Reserved Reserved DACC1DOR[11:0] Bits 31:12 Reserved. DACC1DOR[11:0]: DAC channel1 data output Bit 11:0 These bits are read only, they contain data output for DAC channel1. 11.5.13 DAC channel2 Data Output Register (DAC_DOR2) Address offset: 0x30...
Page 205: Dac Register Map
RM0008 Digital-to-analog converter (DAC) 11.5.14 DAC register map The following table summarizes the DAC registers. Table 52. DAC Register map dress Name offset TSEL2[2: TSEL1[2: 0x00 DAC_CR MAMP2[3:0] E2[2: MAMP1[3:0] E1[2: Reserved Reserved DAC_SWTRI 0x04 Reserved DAC_DHR12 0x08 Reserved DACC1DHR[11:0] DAC_DHR12 0x0C Reserved...
Page 206: Advanced-Control Timers (Tim1&Tim8)
Advanced-control timers (TIM1&TIM8) RM0008 Advanced-control timers (TIM1&TIM8) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 207 RM0008 Advanced-control timers (TIM1&TIM8) ● Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare –...
Page 208: Figure 47. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0008 Figure 47. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO Input Filter TIMx_ETR Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 209: Tim1&Tim8 Functional Description
RM0008 Advanced-control timers (TIM1&TIM8) 12.3 TIM1&TIM8 functional description 12.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 210: Counter Modes
Advanced-control timers (TIM1&TIM8) RM0008 Figure 48. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 49.
Page 211: Figure 51. Counter Timing Diagram, Internal Clock Divided By 2
RM0008 Advanced-control timers (TIM1&TIM8) preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 212: Figure 52. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0008 Figure 52. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 53. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 213: Figure 55. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0008 Advanced-control timers (TIM1&TIM8) Figure 55. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 214: Figure 56. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0008 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 56. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV)
Page 215: Figure 59. Counter Timing Diagram, Internal Clock Divided By N
RM0008 Advanced-control timers (TIM1&TIM8) Figure 59. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 60. Counter timing diagram, update event when repetition counter is not used CK_PSC Timer clock = CK_CNT...
Page 216: Figure 61. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0008 In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
Page 217 RM0008 Advanced-control timers (TIM1&TIM8) Figure 63. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 64.
Page 218: Repetition Counter
Advanced-control timers (TIM1&TIM8) RM0008 Figure 66. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 219: Figure 67. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0008 Advanced-control timers (TIM1&TIM8) Figure 67. Update rate examples depending on mode and TIMx_RCR register settings Center-aligned mode Edge-aligned mode Upcounting Downcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR re-synchronization (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated...
Page 220: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0008 12.3.4 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin ● External clock mode2: external trigger input ETR ● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 221: Figure 70. Control Circuit In External Clock Mode 1
RM0008 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 222: Capture/Compare Channels
Advanced-control timers (TIM1&TIM8) RM0008 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 223: Figure 73. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0008 Advanced-control timers (TIM1&TIM8) Figure 73. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P (from slave mode TIMx_CCMR1 TIMx_CCER controller) TI2F_rising...
Page 224: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 75. Output stage of capture/compare channel (channel 1 to 3) Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER OC1CE OC1M[2:0] DTG[7:0] CC1NE...
Page 225: Pwm Input Mode
RM0008 Advanced-control timers (TIM1&TIM8) The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: ● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register.
Page 226: Forced Output Mode
Advanced-control timers (TIM1&TIM8) RM0008 For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): ● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 227: Output Compare Mode
RM0008 Advanced-control timers (TIM1&TIM8) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 12.3.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 228: Pwm Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 78. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A B200 B201 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 12.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 229: Figure 79. Edge-Aligned Pwm Waveforms (Arr=8)
RM0008 Advanced-control timers (TIM1&TIM8) PWM edge-aligned mode ● Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 210. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 230 Advanced-control timers (TIM1&TIM8) RM0008 Figure 80. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10...
Page 231: Complementary Outputs And Dead-Time Insertion
RM0008 Advanced-control timers (TIM1&TIM8) 12.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 232: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0008 Figure 83. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 12.4.18: Break and dead-time register (TIMx_BDTR) on page 267 for delay calculation.
Page 233 RM0008 Advanced-control timers (TIM1&TIM8) When a break occurs (selected level on the break input): ● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
Page 234: Figure 84. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0008 Figure 84. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 235: Clearing The Ocxref Signal On An External Event
RM0008 Advanced-control timers (TIM1&TIM8) 12.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 236: 6-Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0008 12.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 237: One-Pulse Mode
RM0008 Advanced-control timers (TIM1&TIM8) 12.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 238: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0008 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 239: Table 53. Counting Direction Versus Encoder Signals
RM0008 Advanced-control timers (TIM1&TIM8) repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 240: Figure 88. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 88. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 89 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 89.
Page 241: Timer Input Xor Function
RM0008 Advanced-control timers (TIM1&TIM8) 12.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 242: Figure 90. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0008 written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). Figure 90 describes this example. Figure 90. Example of hall sensor interface TIH1 TIH2 TIH3...
Page 243: Timx And External Trigger Synchronization
RM0008 Advanced-control timers (TIM1&TIM8) 12.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 244: Figure 92. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0008 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 245: Figure 93. Control Circuit In Trigger Mode
RM0008 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 246: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0008 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source –...
Page 247: Tim1&Tim8 Registers
RM0008 Advanced-control timers (TIM1&TIM8) 12.4 TIM1&TIM8 registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 12.4.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 Reserved CKD[1:0] ARPE CMS[1:0] UDIS Res. Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD[1:0]: Clock division.
Page 248: Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0008 Bit 2 URS: Update request source. This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 249 RM0008 Advanced-control timers (TIM1&TIM8) Bit 9 OIS1N: Output Idle state 1 (OC1N output). 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register).
Page 250: Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0008 12.4.3 Slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity. This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 251 RM0008 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter. This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 252: Table 54. Timx Internal Trigger Connection
Advanced-control timers (TIM1&TIM8) RM0008 Bits 6:4 TS[2:0]: Trigger selection. This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 253: Dma/Interrupt Enable Register (Timx_Dier)
RM0008 Advanced-control timers (TIM1&TIM8) 12.4.4 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 COMD CC4D CC3D CC2D CC1D COMI Res. CC4IE CC3IE CC2IE CC1IE Res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable. 0: Trigger DMA request disabled.
Page 254: Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0008 Bit 3 CC3IE: Capture/Compare 3 interrupt enable. 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. Bit 2 CC2IE: Capture/Compare 2 interrupt enable. 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable. 0: CC1 interrupt disabled.
Page 255 RM0008 Advanced-control timers (TIM1&TIM8) Bit 5 COMIF: COM interrupt Flag. This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending.
Page 256: Event Generation Register (Timx_Egr)
Advanced-control timers (TIM1&TIM8) RM0008 12.4.6 Event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Reserved COMG CC4G CC3G CC2G CC1G Res. Bits 15:8 Reserved, always read as 0. Bit 7 BG: Break Generation. This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action.
Page 257: Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 Advanced-control timers (TIM1&TIM8) 12.4.7 Capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 258 Advanced-control timers (TIM1&TIM8) RM0008 Bits 6:4 OC1M: Output Compare 1 Mode. These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 259 RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC2F: Input Capture 2 Filter. Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler. Bits 9:8 CC2S: Capture/Compare 2 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 260: Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0008 12.4.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output Compare mode Bit 15 OC4CE: Output Compare 4 Clear Enable Bits 14:12 OC4M: Output Compare 4 Mode.
Page 261: Capture/Compare Enable Register (Timx_Ccer)
RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. Bits 9:8 CC4S: Capture/Compare 4 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output.
Page 262 Advanced-control timers (TIM1&TIM8) RM0008 Bit 7 CC2NP: Capture/Compare 2 Complementary output Polarity. refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 Complementary output enable. refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 Complementary output Polarity.
Page 263: Table 55. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0008 Advanced-control timers (TIM1&TIM8) Table 55. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=0, OCx_EN=0...
Page 264: Counter (Timx_Cnt)
Advanced-control timers (TIM1&TIM8) RM0008 12.4.10 Counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter Value. 12.4.11 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler Value. The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 265: Repetition Counter Register (Timx_Rcr)
RM0008 Advanced-control timers (TIM1&TIM8) 12.4.13 Repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Reserved REP[7:0] Res. Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition Counter Value. These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 266: Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1&TIM8) RM0008 12.4.15 Capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 Value. If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 267: Capture/Compare Register 4 (Timx_Ccr4)
RM0008 Advanced-control timers (TIM1&TIM8) 12.4.17 Capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare Value. If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 268 Advanced-control timers (TIM1&TIM8) RM0008 Bit 15 MOE: Main Output enable. This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 269: Dma Control Register (Timx_Dcr)
RM0008 Advanced-control timers (TIM1&TIM8) Bit 10 OSSI: Off-State Selection for Idle mode. This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 12.4.9: Capture/compare enable register (TIMx_CCER) on page 261). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1.
Page 270 Advanced-control timers (TIM1&TIM8) RM0008 Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA Burst Length. This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below).
Page 271: Dma Address For Full Transfer (Timx_Dmar)
RM0008 Advanced-control timers (TIM1&TIM8) 12.4.20 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses. A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)”...
Page 272 Advanced-control timers (TIM1&TIM8) RM0008 Table 56. TIM1&TIM8 Register map and reset values (continued) Offset Register TIMx_CCMR2 OC4M CC4S OC3M CC3S Output Compare [2:0] [1:0] [2:0] [1:0] Reserved mode Reset value 0x1C TIMx_CCMR2 CC4S CC3S IC4F[3:0] IC3F[3:0] Input Capture [1:0] [1:0] Reserved [1:0] [1:0]...
Page 273: General-Purpose Timer (Timx)
RM0008 General-purpose timer (TIMx) General-purpose timer (TIMx) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 274: Timx Main Features
General-purpose timer (TIMx) RM0008 13.2 TIMx main features General purpose TIMx (TIM2, TIM3, TIM4 and TIM5) timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65535. ●...
Page 275: Timx Functional Description
RM0008 General-purpose timer (TIMx) Figure 95. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity Selection & Edge Input Filter TIMx_ETR Detector & Prescaler TRGO ITR0 Trigger to other timers Controller ITR1 to DAC/ADC ITR2 TRGI Slave ITR3 Reset, Enable, Up/Down, Count,...
Page 276: Figure 96. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timer (TIMx) RM0008 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 277: Counter Modes
RM0008 General-purpose timer (TIMx) Figure 97. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 13.3.2...
Page 278: Figure 98. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timer (TIMx) RM0008 Figure 98. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 99.
Page 279: Figure 101. Counter Timing Diagram, Internal Clock Divided By N
RM0008 General-purpose timer (TIMx) Figure 101. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 102. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 280: Figure 103. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timer (TIMx) RM0008 Figure 103. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 281: Figure 104. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General-purpose timer (TIMx) Figure 104. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 105.
Page 282: Figure 107. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timer (TIMx) RM0008 Figure 107. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 108. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN...
Page 283: Figure 50. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General-purpose timer (TIMx) In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.
Page 284: Figure 63. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
General-purpose timer (TIMx) RM0008 Figure 111. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow (cnt_ovf) Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 112.
Page 285: Clock Selection
RM0008 General-purpose timer (TIMx) Figure 114. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 286: Figure 69. Ti2 External Clock Connection Example
General-purpose timer (TIMx) RM0008 Figure 115. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 287: Figure 71. External Trigger Input Block
RM0008 General-purpose timer (TIMx) The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 117. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 External clock source mode 2...
Page 288: Capture/Compare Channels
General-purpose timer (TIMx) RM0008 Figure 119. Control circuit in external clock mode 2 MASTER CNT_EN ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 13.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 289: Figure 121. Capture/Compare Channel 1 Main Circuit
RM0008 General-purpose timer (TIMx) Figure 121. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/Compare Preload Register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/Compare Shadow Register CC1S[0] TIMx_CCMR1 (from time...
Page 290: Input Capture Mode
General-purpose timer (TIMx) RM0008 13.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 291: Pwm Input Mode
RM0008 General-purpose timer (TIMx) 13.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ●...
Page 292: Output Compare Mode
General-purpose timer (TIMx) RM0008 To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) =>...
Page 293: Pwm Mode
RM0008 General-purpose timer (TIMx) Figure 124. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIMx_CNT 0039 003A 003B TIMx_CCR1 003A B201 OC1REF=OC1 Match detected on CCR1 Interrupt generated if enabled 13.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 294: Figure 125. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timer (TIMx) RM0008 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section : upcounting mode on page 277. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 295: Figure 126. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 General-purpose timer (TIMx) Figure 126. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10...
Page 296: One Pulse Mode
General-purpose timer (TIMx) RM0008 13.3.10 One pulse mode One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 297: Clearing The Ocxref Signal On An External Event
RM0008 General-purpose timer (TIMx) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 298: Encoder Interface Mode
General-purpose timer (TIMx) RM0008 Figure 128. Clearing TIMx OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR OCREF_CLR becomes high still high 13.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’...
Page 299: Table 57. Counting Direction Versus Encoder Signals
RM0008 General-purpose timer (TIMx) Table 57. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 300: Timer Input Xor Function
General-purpose timer (TIMx) RM0008 Figure 130. Example of encoder interface mode with IC1FP1 polarity inverted. forward jitter backward jitter forward Counter down down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 301: Figure 131. Control Circuit In Reset Mode
RM0008 General-purpose timer (TIMx) ● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge.
Page 302: Figure 132. Control Circuit In Gated Mode
General-purpose timer (TIMx) RM0008 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 303: Figure 133. Control Circuit In Trigger Mode
RM0008 General-purpose timer (TIMx) Figure 133. Control circuit in trigger mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 35 36 37 38 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode).
Page 304: Timer Synchronization
General-purpose timer (TIMx) RM0008 Figure 134. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 13.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 305: Figure 136. Gating Timer 2 With Oc1Ref Of Timer 1
RM0008 General-purpose timer (TIMx) Using one timer to enable another timer In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. Refer to Figure 135 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high.
Page 306: Figure 137. Gating Timer 2 With Enable Of Timer 1
General-purpose timer (TIMx) RM0008 timers. Timer 2 stops when Timer 1 is disabled by writing ‘0’ to the CEN bit in the TIM1_CR1 register: ● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). ●...
Page 307: Figure 138. Triggering Timer 2 With Update Of Timer 1
RM0008 General-purpose timer (TIMx) Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 135 for connections. Timer 2 starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
Page 308: Figure 139. Triggering Timer 2 With Enable Of Timer 1
General-purpose timer (TIMx) RM0008 Figure 139. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 135 for connections.
Page 309: Debug Mode
RM0008 General-purpose timer (TIMx) When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits).
Page 310: Timx Registers
General-purpose timer (TIMx) RM0008 13.4 TIMx registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 13.4.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD: Clock Division.
Page 311: Control Register 2 (Timx_Cr2)
RM0008 General-purpose timer (TIMx) Bit 2 URS: Update Request Source. This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 312: Slave Mode Control Register (Timx_Smcr)
General-purpose timer (TIMx) RM0008 Bits 6:4 MMS: Master Mode Selection. These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
Page 313 RM0008 General-purpose timer (TIMx) Bit 15 ETP: External Trigger Polarity. This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External Clock enable.
Page 314: Table 58. Timx Internal Trigger Connection
General-purpose timer (TIMx) RM0008 Bits 6:4 TS: Trigger Selection. This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). TIM1 001: Internal Trigger 1 (ITR1). TIM2 010: Internal Trigger 2 (ITR2). TIM3 011: Internal Trigger 3 (ITR3).
Page 315: Dma/Interrupt Enable Register (Timx_Dier)
RM0008 General-purpose timer (TIMx) 13.4.4 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC4IE CC3IE CC2IE CC1IE Res. Res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable. 0: Trigger DMA request disabled. 1: Trigger DMA request enabled.
Page 316: Status Register (Timx_Sr)
General-purpose timer (TIMx) RM0008 Bit 2 CC2IE: Capture/Compare 2 interrupt enable. 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable. 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable. 0: Update interrupt disabled.
Page 317: Event Generation Register (Timx_Egr)
RM0008 General-purpose timer (TIMx) Bit 2 CC2IF: Capture/Compare 2 interrupt Flag. refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt Flag. If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 318: Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timer (TIMx) RM0008 Bit 2 CC2G: Capture/compare 2 generation. refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation. This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 319 RM0008 General-purpose timer (TIMx) Bits 9:8 CC2S[1:0]: Capture/Compare 2 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 320 General-purpose timer (TIMx) RM0008 Bit 3 OC1PE: Output Compare 1 Preload enable. 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Page 321 RM0008 General-purpose timer (TIMx) Input capture mode Bits 15:12 IC2F: Input Capture 2 Filter. Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler. Bits 9:8 CC2S: Capture/Compare 2 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 322: Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timer (TIMx) RM0008 13.4.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output Compare mode Bit 15 OC4CE: Output Compare 4 Clear Enable Bits 14:12 OC4M: Output Compare 4 Mode.
Page 323: Capture/Compare Enable Register (Timx_Ccer)
RM0008 General-purpose timer (TIMx) Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. Bits 9:8 CC4S: Capture/Compare 4 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output.
Page 324: Counter (Timx_Cnt)
General-purpose timer (TIMx) RM0008 Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bits 3:2 Reserved, always read as 0. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations.
Page 325: Prescaler (Timx_Psc)
RM0008 General-purpose timer (TIMx) 13.4.11 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler Value. The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event. 13.4.12 Auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 326: Capture/Compare Register 2 (Timx_Ccr2)
General-purpose timer (TIMx) RM0008 13.4.14 Capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 Value. If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 327: Dma Control Register (Timx_Dcr)
RM0008 General-purpose timer (TIMx) Bits 15:0 CCR4[15:0]: Capture/Compare Value. 1/ if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 328: Dma Address For Full Transfer (Timx_Dmar)
General-purpose timer (TIMx) RM0008 13.4.18 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses. A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)”...
Page 329 RM0008 General-purpose timer (TIMx) Table 60. TIMx register map and reset values (continued) Offset Register TIMx_CCMR2 OC4M CC4S OC3M CC3S Output Compare [2:0] [1:0] [2:0] [1:0] Reserved mode Reset value 0x1C TIMx_CCMR2 CC4S CC3S IC4F[3:0] IC3F[3:0] Input Capture [1:0] [1:0] Reserved [1:0] [1:0]...
Page 330: Basic Timer (Tim6&7)
Basic timer (TIM6&7) RM0008 Basic timer (TIM6&7) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 331: Tim6&Tim7 Functional Description
RM0008 Basic timer (TIM6&7) Figure 141. Basic timer block diagram TRGO Trigger Internal clock (CK_INT) to DAC TIMxCLK from RCC controller Reset, Enable, Count, Controller Auto-reload Register Stop, Clear or up CK_PSC CK_CNT ± Prescaler COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt &...
Page 332: Figure 142. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timer (TIM6&7) RM0008 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Page 333: Counting Mode
RM0008 Basic timer (TIM6&7) 14.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 334: Figure 145. Counter Timing Diagram, Internal Clock Divided By 2
Basic timer (TIM6&7) RM0008 Figure 145. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 146. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT...
Page 335: Clock Source
RM0008 Basic timer (TIM6&7) Figure 148. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register...
Page 336: Debug Mode
Basic timer (TIM6&7) RM0008 Figure 150. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 14.3.4 Debug mode When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 337 RM0008 Basic timer (TIM6&7) Bit 2 URS: Update Request Source. This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 338: Control Register 2 (Timx_Cr2)
Basic timer (TIM6&7) RM0008 14.4.2 Control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Reserved MMS[2:0] Reserved Res. Res. Bits 15:7 Reserved, always read as 0. Bits 6:4 MMS: Master Mode Selection. These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 339: Status Register (Timx_Sr)
RM0008 Basic timer (TIM6&7) 14.4.4 Status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved Res. rc_w0 Bits 15:1 Reserved, always read as 0. Bit 0 UIF: Update interrupt flag. This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 340: Counter (Timx_Cnt)
Basic timer (TIM6&7) RM0008 14.4.6 Counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter Value. 14.4.7 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler Value. The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 341: Tim6&7 Register Map
RM0008 Basic timer (TIM6&7) 14.4.9 TIM6&7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 61. TIM6&7 - register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value...
Page 342: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0008 Real-time clock (RTC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 343: Rtc Main Features
RM0008 Real-time clock (RTC) 15.2 RTC main features ● Programmable prescaler: division factor up to 2 ● 32-bit programmable counter for long-term measurement ● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) ●...
Page 344: Figure 151. Rtc Simplified Block Diagram
Real-time clock (RTC) RM0008 Figure 151. RTC simplified block diagram APB1 bus PCLK1 APB1 interface not powered in Standby RTCCLK Backup domain RTC_CR RTC_PRL RTC_Second SECF 32-bit programmable Reload SECIE counter RTC_Overflow TR_CLK RTC_CNT RTC_DIV rising OWIE edge RTC_Alarm ALRF RTC prescaler ALRIE RTC_ALR...
Page 345: Resetting Rtc Registers
RM0008 Real-time clock (RTC) 15.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset.
Page 346: Rtc Flag Assertion
Real-time clock (RTC) RM0008 15.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000.
Page 347: Rtc Registers
RM0008 Real-time clock (RTC) 15.4 RTC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 15.4.1 RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 Reserved OWIE ALRIE SECIE Bits 15:3 Reserved, forced by hardware to 0. Bit 2 OWIE: OverfloW Interrupt Enable 0: Overflow interrupt is masked.
Page 348: Rtc Control Register Low (Rtc_Crl)
Real-time clock (RTC) RM0008 15.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 Reserved RTOFF ALRF SECF rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not.
Page 349: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
RM0008 Real-time clock (RTC) The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 15.3.4 on page 345).
Page 350: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
Real-time clock (RTC) RM0008 RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 15.3.4 on page 345) Reset value: 0x8000 PRL[15:0] Bits 15:0 PRL[15:0]: RTC Prescaler Reload Value Low These bits are used to define the counter clock frequency according to the following formula: /(PRL[19:0]+1) TR_CLK RTCCLK...
Page 351: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
RM0008 Real-time clock (RTC) 15.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 352: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
Real-time clock (RTC) RM0008 15.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 353: Rtc Register Map
RM0008 Real-time clock (RTC) 15.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 62. - register map and reset values Offset Register RTC_CRH 0x000 Reserved Reset value RTC_CRL 0x004 Reserved Reset value RTC_PRLH PRL[19:16]...
Page 354: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0008 Independent watchdog (IWDG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 355: Hardware Watchdog
RM0008 Independent watchdog (IWDG) 16.3.1 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count. 16.3.2 Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected.
Page 356: Iwdg Registers
Independent watchdog (IWDG) RM0008 The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy. For more details refer to LSI calibration on page 16.4 IWDG registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 16.4.1 Key register (IWDG_KR) Address offset: 0x00...
Page 357: Reload Register (Iwdg_Rlr)
RM0008 Independent watchdog (IWDG) Bits 31:3 Reserved, read as 0. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 16.3.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider.
Page 358: Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0008 16.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Reserved Reserved Bits 31:2 Reserved Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V voltage domain (takes up to 5 RC 40 kHz cycles).
Page 359: Iwdg Register Map
RM0008 Independent watchdog (IWDG) 16.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 64. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] 0x00 Reserved Reset value IWDG_PR PR[2:0] 0x04 Reserved Reset value IWDG_RLR RL[11:0] 0x08...
Page 360: Window Watchdog (Wwdg)
Window watchdog (WWDG) RM0008 Window watchdog (WWDG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 361: Figure 155. Watchdog Block Diagram
RM0008 Window watchdog (WWDG) Figure 155. Watchdog block diagram Watchdog Configuration Register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog Control Register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 362: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0008 17.4 How to program the watchdog timeout Figure 156 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 156.
Page 363: Debug Mode
RM0008 Window watchdog (WWDG) 17.5 Debug mode When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 26.15.2: Debug support for timers, watchdog, bxCAN and I2C.
Page 364: Status Register (Wwdg_Sr)
Window watchdog (WWDG) RM0008 Bit 31:10 Reserved Bit 9 EWI: Early Wakeup Interrupt When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer Base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK1 div 4096) div 1 01: CK Counter Clock (PCLK1 div 4096) div 2...
Page 365: Flexible Static Memory Controller (Fsmc)
RM0008 Flexible static memory controller (FSMC) Flexible static memory controller (FSMC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 366: Block Diagram
Flexible static memory controller (FSMC) RM0008 ● Write FIFO, 16 words long, each word 32 bits wide. This makes it possible to write to slow memories and free the AHB quickly for other transactions. If a new transaction is started to the FSMC, first the FIFO is drained The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up.
Page 367: Ahb Interface
RM0008 Flexible static memory controller (FSMC) 18.3 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 368: External Device Address Mapping
Flexible static memory controller (FSMC) RM0008 18.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 158): ● Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM regions with 4 dedicated Chip Select.
Page 369: Nand/Pc Card Address Mapping
RM0008 Flexible static memory controller (FSMC) HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 67.
Page 370: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0008 For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 69 below) located in the lower 256 Kbytes: ● Data section (first 64 Kbytes in the common/attribute memory space) ●...
Page 371: External Memory Interface Signals
RM0008 Flexible static memory controller (FSMC) The programmable memory parameters include access timings (see Table 70) and support for wrap and wait management (for PSRAM and NOR Flash accessed in burst mode). Table 70. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min.
Page 372: Table 72. Muxed I/O Nor Flash
Flexible static memory controller (FSMC) RM0008 NOR Flash, multiplexed I/Os Table 72. Muxed I/O NOR Flash FSMC signal name Function Clock (for synchronous burst) A[25:16] Address bus AD[15:0] 16-bit multiplexed, bidirectional address/data bus NE[x] Chip select, x = 1..4 Output enable Write enable Latch enable (this signal is called address valid, NADV, by some NOR NL(=NADV)
Page 373: Supported Memories And Transactions
RM0008 Flexible static memory controller (FSMC) 18.5.2 Supported memories and transactions Table 74 below displays the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the FSMC appear in gray. Table 74. NOR Flash/PSRAM supported memories and transactions Allowed/ Memory Device...
Page 374: General Timing Rules
Flexible static memory controller (FSMC) RM0008 18.5.3 General timing rules Signals synchronization ● All controller output signals change on the rising edge of the internal clock (HCLK) ● In synchronous write mode (PSRAM devices), the output data changes on the falling edge of the memory clock (CLK) 18.5.4 NOR Flash/PSRAM controller timing diagrams...
Page 375: Table 75. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 160. Mode1 write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721b The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge.
Page 376: Table 76. Fsmc_Tcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 76. FSMC_TCRx bit fields Bit name Value to set number 31-16 0x0000 Duration of the second access phase (DATAST+1 HCLK cycles) for 15-8 DATAST write accesses, DATAST+3 HCLK cycles for read accesses). This value cannot be 0 (minimum is 1) ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
Page 377: Table 77. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 162. ModeA write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721b The differences compared with mode1 are the toggling of NOE and the independent read and write timings.
Page 378: Table 78. Fsmc_Tcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 78. FSMC_TCRx bit fields Bit name Value to set number 31-30 29-28 ACCMOD 27-16 0x000 Duration of the second access phase (DATAST+3 HCLK cycles) in 15-8 DATAST read. This value cannot be 0 (minimum is 1) ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read.
Page 379: Figure 163. Mode2/B Read Accesses
RM0008 Flexible static memory controller (FSMC) Mode 2/B - NOR Flash Figure 163. Mode2/B read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles Data sampled Data strobe ai14724c Figure 164.
Page 380: Table 80. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Figure 165. ModeB write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai15110b The differences with mode1 are the toggling of NADV and the independent read and write timings when extended mode is set (Mode B).
Page 381: Table 81. Fsmc_Tcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 81. FSMC_TCRx bit fields Bit number Bit name Value to set 31-30 29-28 ACCMOD 0x1 if extended mode is set 27-16 0x000 Duration of the access second phase (DATAST+3 HCLK cycles) in 15-8 DATAST read.
Page 382: Figure 166. Modec Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode C - NOR Flash - OE toggling Figure 166. ModeC read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK cycles HCLK cycles HCLK cycles Data sampled Data strobe ai14725c...
Page 383: Table 83. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 83. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1. BURSTEN FACCEN Set according to memory support MWID As needed MTYP 10 (NOR Flash).
Page 384: Figure 168. Moded Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode D - asynchronous access with extended address Figure 168. ModeD read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles (ADDHLD + 1) HCLK cycles...
Page 385: Table 86. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) The differences with mode1 are the toggling of NADV, NOE that goes on toggling after NADV changes and the independent read and write timings. Table 86. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD...
Page 386: Figure 170. Muxed Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode muxed - asynchronous access muxed NOR Flash Figure 170. Muxed read accesses Memory transaction A[25:16] NADV High data driven AD[15:0] Lower address by memory 1HCLK cycle (ADDSET +1) (DATAST + 1) 2 HCLK (BUSTURN + 1) cycles HCLK cycles...
Page 387: Synchronous Burst Read
RM0008 Flexible static memory controller (FSMC) Table 89. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1. BURSTEN FACCEN Set according to memory support MWID As needed MTYP 10 (NOR) MUXEN...
Page 388 Flexible static memory controller (FSMC) RM0008 Data latency versus NOR Flash latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register.
Page 389: Table 91. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 172. Synchronous read mode - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG = 0) NWAIT (WAITCFG = 1) DATALAT CLK cycles inserted wait state A/D[15:0] Addr[15:0] data...
Page 390: Table 92. Fsmc_Tcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 91. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set WAITCFG to be set according to memory WRAPMOD to be set according to memory WAITPOL to be set according to memory BURSTEN FWPRLVL Set to protect memory from accidental write access...
Page 391: Figure 173. Synchronous Write Mode - Psram (Cram)
RM0008 Flexible static memory controller (FSMC) Figure 173. Synchronous write mode - PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) DATALAT CLK cycles inserted wait state A/D[15:0] Addr[15:0] data data data data...
Page 392: Table 93. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 93. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 0x0000 CBURSTRW 18-15 EXTMOD When high, the first data after latency period is taken as always WAITEN valid, regardless of the wait from memory value WREN no effect on synchronous read WAITCFG...
Page 393: Nor/Psram Controller Registers
RM0008 Flexible static memory controller (FSMC) 18.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DX This register contains the control information of each memory bank, used for SRAMs, ROMs and asynchronous or burst NOR Flash memories.
Page 394 Flexible static memory controller (FSMC) RM0008 Bit 10 WRAPMOD: Wrapped burst mode support. Defines whether the controller is splitting an AHB burst wrap access into two linear access or not, valid only when accessing Flash memories in burst mode 0: Direct wrapped burst is not enabled (default after reset), 1: Direct wrapped burst is enabled.
Page 395 RM0008 Flexible static memory controller (FSMC) SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 396 Flexible static memory controller (FSMC) RM0008 Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 157 Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: DATAST phase duration = 1 ×...
Page 397 RM0008 Flexible static memory controller (FSMC) SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 398: Nand Flash/Pc Card Controller
Flexible static memory controller (FSMC) RM0008 Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 157 Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: DATAST phase duration = 1 ×...
Page 399: External Memory Interface Signals
RM0008 Flexible static memory controller (FSMC) Table 95. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle to set up the address before the Read/Write time (HCLK) command assertion Minimum duration (HCLK clock AHB clock cycle...
Page 400: Nand Flash / Pc Card Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0008 16-bit NAND Flash Table 97. 16-bit NAND Flash FSMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus NOE(= NRE) Output enable (memory signal name: read enable, NRE) Write enable...
Page 401: Timing Diagrams For Nand, Ata And Pc Card
RM0008 Flexible static memory controller (FSMC) Table 99. Supported memories and transactions Memory Allowed/ Device Mode Comments data size data size not allowed Asynchronous Asynchronous Asynchronous Split into 2 FSMC accesses NAND 8-bit Asynchronous Split into 2 FSMC accesses Asynchronous Split into 4 FSMC accesses Asynchronous Split into 4 FSMC accesses...
Page 402: Figure 174. Nand Controller Timing For Common Memory Access
Flexible static memory controller (FSMC) RM0008 Figure 174. NAND controller timing for common memory access HCLK A[25:0] NCE3 NCE2 High NREG, NIOW, NIOR MEMxSET + 1 MEMxWAIT + 1 MEMxHOLD + 1 NWE, MEMxHIZ + 1 write_data read_data Valid ai14732 1.
Page 403: Nand-Flash Ready/Busy Management
RM0008 Flexible static memory controller (FSMC) STARTAD[24:17] and finally STARTAD[25] for 64 Mb x 8 bit NAND Flash) in the common memory or attribute space. The ALE input of the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations.
Page 404: Figure 175. Access To Non 'Ce Don't Care' Nand-Flash
Flexible static memory controller (FSMC) RM0008 Figure 175. Access to non ‘CE don’t care’ NAND-Flash NCE must stay low High I/O[7:0] 0x00 A7-A0 A16-A9 A24-A17 A25 R/NB ai14733 1. CPU wrote byte 0x00 at address 0x7001 0000. 2. CPU wrote byte A7~A0 at address 0x7002 0000. 3.
Page 405: Error Correction Code Computation Ecc (Nand Flash)
RM0008 Flexible static memory controller (FSMC) 18.6.5 Error correction code computation ECC (NAND Flash) The FSMC PC-Card controller includes two error correction code computation hardware blocks, one per memory bank. They are used to reduce the host CPU workload when processing the error correction code by software in the system.
Page 406 Flexible static memory controller (FSMC) RM0008 Bits 19:17 ECCPS: ECC page size. Defines the page size for the extended ECC: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes Bits 16:13 TAR: ALE to RE delay. Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Page 407 RM0008 Flexible static memory controller (FSMC) FIFO status and interrupt register 2..4 (FSMC_SR2..4) Address offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 Reset value: 0x0000 0040 This register contains information about FIFO status and interrupt. The FSMC has a FIFO that is used when writing to memories to store up to16 words of data from the AHB.
Page 408 Flexible static memory controller (FSMC) RM0008 Common memory space timing register 2..4 (FSMC_PMEM2..4) Address offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC Card or NAND Flash memory bank x, used for access to the common memory space of the 16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write access and data read/write access.
Page 409 RM0008 Flexible static memory controller (FSMC) Attribute memory space timing registers 2..4 (FSMC_PATT2..4) Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC Card or NAND Flash memory bank x, used for access to the attribute memory space of the 16-bit PC Card/CompactFlash, or to access the NAND Flash for last address write access if timing must differ from the other accesses (for Ready/Busy management, refer to...
Page 410 Flexible static memory controller (FSMC) RM0008 I/O space timing register 4 (FSMC_PIO4) Address offset: 0xA000 0000 + 0xB0 Reset value: 0xFCFCFCFC The FSMC_PIO4 read/write registers contain the timing information used to gain access to the I/O space of the 16-bit PC Card/CompactFlash. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IOHIZx IOHOLDx...
Page 411: Table 100. Ecc Result Relevant Bits
RM0008 Flexible static memory controller (FSMC) ECC result registers 2/3 (FSMC_ECCR2/3) Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 Reset value: 0x0000 0000 These registers contain the current error correction code value computed by the ECC computation modules of the FSMC controller (one module per NAND Flash memory bank).
Page 412: Sdio Interface (Sdio)
SDIO interface (SDIO) RM0008 SDIO interface (SDIO) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 413: Sdio Bus Topology
RM0008 SDIO interface (SDIO) The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 19.2 SDIO bus topology Communication over the bus is based on command and data transfers. The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction.
Page 414: Figure 178. Sdio (Multiple) Block Write Operation
SDIO interface (SDIO) RM0008 Figure 178. SDIO (multiple) block write operation From host to card From card to host Stop command stops data transfer Data from host to card Command Response Command Response SDIO_CMD SDIO_D Busy Data block crc Data block crc Busy Busy Optional cards Busy.
Page 415: Sdio Functional Description
RM0008 SDIO interface (SDIO) 19.3 SDIO functional description The SDIO consists of two parts: ● The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. ● The AHB interface accesses the SDIO adapter registers, and generates interrupt and DMA request signals.
Page 416: Sdio Adapter
SDIO interface (SDIO) RM0008 Table 101. SDIO I/O definitions Direction Description MultiMediaCard/SD/SDIO card clock. This pin is the clock from SDIO_CK Output host to card. MultiMediaCard/SD/SDIO card command. This pin is the SDIO_CMD Bidirectional bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the SDIO_D[7:0] Bidirectional bidirectional databus.
Page 417: Figure 183. Control Unit
RM0008 SDIO interface (SDIO) Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: ● power-off ● power-up ● power-on Figure 183. Control unit Control unit Power management Clock Adapter...
Page 418: Figure 184. Sdio Adapter Command Path
SDIO interface (SDIO) RM0008 Command path The command path unit sends commands to and receives responses from the cards. Figure 184. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDIO_CMDin Argument SDIO_CMDout Shift register To AHB interface Response...
Page 419: Figure 185. Command Path State Machine (Cpsm)
RM0008 SDIO interface (SDIO) Figure 185. Command path state machine (CPSM) CE-ATA Command On reset Completion signal Wait_CPL received or CPSM disabled or Command CRC failed CPSM Enabled and Idle Response received or Response Received in CE-ATA pending command disabled or command mode and no interrupt and CRC failed CPSM...
Page 420: Table 102. Command Format
SDIO interface (SDIO) RM0008 Figure 186. SDIO command transfer at least 8 SDIO_CK cycles Command Response Command SDIO_CK State Idle Send Wait Receive Idle Send SDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives ai14707 ● Command format – Command: a command is a token that starts an operation.
Page 421: Table 103. Short Response Format
RM0008 SDIO interface (SDIO) Table 103. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 104. Long response format Bit position Width Value Description Start bit Transmission bit [133:128] 111111...
Page 422: Figure 187. Data Path
SDIO interface (SDIO) RM0008 Data path The data path subunit transfers data to and from cards. Figure 187 shows a block diagram of the data path. Figure 187. Data path Data path Status Control Data To control unit flag logic timer Data FIFO SDIO_Din[7:0]...
Page 423: Figure 188. Data Path State Machine (Dpsm)
RM0008 SDIO interface (SDIO) Figure 188. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 424: Table 106. Data Token Format
SDIO interface (SDIO) RM0008 Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host. ●...
Page 425: Table 107. Transmit Fifo Status Flags
RM0008 SDIO interface (SDIO) Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted –...
Page 426: Sdio Ahb Interface
SDIO interface (SDIO) RM0008 Table 108. Receive FIFO status flags Flag Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data. This flag can be RXFIFOHF used as a DMA request.
Page 427: Card Functional Description
RM0008 SDIO interface (SDIO) Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK); WaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO card host enabled to send a command). Other fields are at their reset value. Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control register: DTEN with ‘1’...
Page 428: Card Identification Process
SDIO interface (SDIO) RM0008 19.4.4 Card identification process The card identification process differs for MultiMediaCards and SD cards. For MultiMediaCard cards, the identification process starts at clock rate F . The SDIO_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows: The bus is activated.
Page 429: Block Write
RM0008 SDIO interface (SDIO) SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. 19.4.5 Block write During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host.
Page 430: Stream Access, Stream Write And Stream Read (Multimediacard Only)
SDIO interface (SDIO) RM0008 If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the status register).
Page 431: Erase: Group Erase And Sector Erase
RM0008 SDIO interface (SDIO) The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register. 2 readbllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------ × TAAC R2WFACTOR ●...
Page 432: Protection Management
SDIO interface (SDIO) RM0008 19.4.10 Protection management Three write protection methods for the cards are supported in the SDIO card host module: internal card write protection (card responsibility) mechanical write protection switch (SDIO card host module responsibility only) password-protected card lock operation Internal card write protection Card data can be protected against write and erase.
Page 433 RM0008 SDIO interface (SDIO) The bit settings are as follows: ● ERASE: setting it forces an erase operation. All other bits must be zero, and only the command byte is sent ● LOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, however not with CLR_PWD ●...
Page 434 SDIO interface (SDIO) RM0008 Locking a card Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode (byte 0 in Table 122), the 8-bit PWD_LEN, and the number of bytes of the current password.
Page 435: Card Status Register
RM0008 SDIO interface (SDIO) Send LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including the 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero. When the ERASE bit is the only bit set in the data field, all card contents are erased, including the PWD and PWD_LEN fields, and the card is no longer locked.
Page 436: Table 109. Card Status
SDIO interface (SDIO) RM0008 Table 109. Card status Clear Bits Identifier Type Value Description condition The command address argument was out of the allowed range for this card. ’0’= no error ADDRESS_ A multiple block or stream read/write E R X OUT_OF_RANGE ’1’= error operation is (although started in a valid...
Page 437 RM0008 SDIO interface (SDIO) Table 109. Card status (continued) Clear Bits Identifier Type Value Description condition (Undefined by the standard) A generic ’0’= no error card error related to the (and detected ERROR ’1’= error during) execution of the last host command (e.g.
Page 438: Sd Status Register
SDIO interface (SDIO) RM0008 Table 109. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error Error in the sequence of the AKE_SEQ_ERROR ’1’= error authentication process Reserved for application specific commands Reserved for manufacturer test mode 19.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary...
Page 439 RM0008 SDIO interface (SDIO) Table 110. SD status (continued) Clear Bits Identifier Type Value Description condition In the future, the 8 LSBs will ’00xxh’= SD Memory Cards as be used to define different defined in Physical Spec Ver1.01- variations of an SD memory 2.00 (’x’= don’t care).
Page 440: Table 111. Speed Class Code Field
SDIO interface (SDIO) RM0008 Table 111. Speed class code field SPEED_CLASS Value definition Class 0 Class 2 Class 4 Class 6 04h – FFh Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps.
Page 441: Table 114. Maximum Au Size
RM0008 SDIO interface (SDIO) The maximum AU size, which depends on the card capacity, is defined in Table 114. The card can be set to any AU size between RU size and maximum AU size. Table 114. Maximum AU size Capacity 16 MB-64 MB 128 MB-256 MB...
Page 442: Sd I/O Mode
SDIO interface (SDIO) RM0008 ERASE_OFFSET This 2-bit field indicates T and one of four values can be selected. This field is OFFSET meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 117. Erase offset field ERASE_OFFSET Value definition 0 [sec] 1 [sec] 2 [sec]...
Page 443: Commands And Responses
RM0008 SDIO interface (SDIO) Waits for the completion of the higher priority transaction Restores the suspended transaction SD I/O ReadWait The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device.
Page 444: Table 118. Block-Oriented Write Commands
SDIO interface (SDIO) RM0008 Command types Both application-specific and general commands are divided into the four following types: ● broadcast command (BC): sent to all cards; no responses returned. ● broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously.
Page 445: Table 119. Block-Oriented Write Protection Commands
RM0008 SDIO interface (SDIO) Table 119. Block-oriented write protection commands Response Type Argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit [31:0] data CMD28 ac of the addressed group. The properties of SET_WRITE_PROT address write protection are coded in the card-...
Page 446: Response Formats
SDIO interface (SDIO) RM0008 Table 122. Lock card Response Type Argument Abbreviation Description index format Sets/resets the password or locks/unlocks CMD42 adtc [31:0] stuff bits the card. The size of the data block is set LOCK_UNLOCK by the SET_BLOCK_LEN command. CMD43 Reserved CMD54...
Page 447: R1B
RM0008 SDIO interface (SDIO) Table 124. R1 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] Command index [39:8] Card status [7:1] CRC7 End bit 19.5.2 It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.
Page 448: R4 (Fast I/O)
SDIO interface (SDIO) RM0008 Table 126. R3 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] ‘111111’ Reserved [39:8] OCR register [7:1] ‘1111111’ Reserved End bit 19.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content.
Page 449: R5 (Interrupt Request)
RM0008 SDIO interface (SDIO) Table 128. R4b response (continued) Bit position Width (bits Value Description [7:1] Reserved End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card.
Page 450: Sdio I/O Card-Specific Operations
SDIO interface (SDIO) RM0008 Table 130. R6 response (continued) Bit position Width (bits) Value Description [7:1] CRC7 End bit The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values: ●...
Page 451: Sdio Suspend/Resume Operation
RM0008 SDIO interface (SDIO) 19.6.3 SDIO suspend/resume operation While sending data to the card, the SDIO can suspend the write operation. the SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command. The CPSM analyzes the response and when the ACK is received from the card (suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC token of the current block.
Page 452: Ce-Ata Interrupt
SDIO interface (SDIO) RM0008 19.7.3 CE-ATA interrupt The command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static bit can be cleared with the clear bit SDIO_ICR[23]. The SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on the mask bit SDIO_MASKx[23].
Page 453: Sdi Clock Control Register (Sdio_Clkcr)
RM0008 SDIO interface (SDIO) Bits 31:2 Reserved, always read as 0. [1:0] PWRCTRL: Power supply control bits. These bits are used to define the current functional state of the card clock: 00: Power-off: the clock to card is stopped. 01: Reserved 10: Reserved power-up 11: Power-on: the card is clocked.
Page 454: Sdio Argument Register (Sdio_Arg)
SDIO interface (SDIO) RM0008 Bit 9 PWRSAV: Power saving configuration bit. For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV: 0: SDIO_CK clock is always enabled. 1: SDIO_CK is only enabled when the bus is active. Bit 8 CLKEN: Clock enable bit 0: SDIO_CK is disabled.
Page 455: Sdio Command Register (Sdio_Cmd)
RM0008 SDIO interface (SDIO) 19.9.4 SDIO Command Register (SDIO_CMD) Address offset: 0x0C Reset value: 0x0000 0000 The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
Page 456: Sdio Command Response Register (Sdio_Respcmd)
SDIO interface (SDIO) RM0008 19.9.5 SDIO Command Response Register (SDIO_RESPCMD) Address offset: 0x10 Reset value: 0x0000 0000 The SDIO_RESPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).
Page 457: Sdio Data Timer Register (Sdio_Dtimer)
RM0008 SDIO interface (SDIO) 19.9.7 SDIO Data Timer Register (SDIO_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDIO_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state.
Page 458: Sdio Data Control Register (Sdio_Dctrl)
SDIO interface (SDIO) RM0008 19.9.9 SDIO Data Control Register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Res.
Page 459: Sdio Data Counter Register (Sdio_Dcount)
RM0008 SDIO interface (SDIO) Bit 2 DTMODE: Data transfer mode selection 0: Block data transfer. 1: Stream data transfer. Bit 1 DTDIR: Data transfer direction selection 0: From controller to card. 1: From card to controller. [0] DTEN: Data transfer enabled bit. Data transfer starts if 1b is written to the DTEN bit.
Page 460: Sdio Status Register (Sdio_Sta)
SDIO interface (SDIO) RM0008 19.9.11 SDIO Status Register (SDIO_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDIO_STA register is a read-only register. It contains two types of flag: ● Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR) ●...
Page 461: Sdio Interrupt Clear Register (Sdio_Icr)
RM0008 SDIO interface (SDIO) Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout. The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 19.9.12 SDIO Interrupt Clear Register (SDIO_ICR)
Page 462 SDIO interface (SDIO) RM0008 Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit...
Page 463: Sdio Mask Register (Sdio_Mask)
RM0008 SDIO interface (SDIO) 19.9.13 SDIO Mask Register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Res.
Page 464 SDIO interface (SDIO) RM0008 Bit 16 TXFIFOFIE: Tx FIFO Full Interrupt Enable Set and reset by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO Half Full Interrupt Enable Set and reset by software to enable/disable interrupt caused by Rx FIFO half full.
Page 465: Sdio Fifo Counter Register (Sdio_Fifocnt)
RM0008 SDIO interface (SDIO) Bit 5 RXOVERRIE: Rx FIFO OverRun Error Interrupt Enable Set and reset by software to enable/disable interrupt caused by Rx FIFO overrun error. 0: Rx FIFO overrun error interrupt disabled 1: Rx FIFO overrun error interrupt enabled Bit 4 TXUNDERRIE: Tx FIFO UnderRun Error Interrupt Enable Set and reset by software to enable/disable interrupt caused by Tx FIFO underrun error.
Page 466: Sdio Data Fifo Register (Sdio_Fifo)
SDIO interface (SDIO) RM0008 19.9.15 SDIO Data FIFO Register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Page 467 RM0008 SDIO interface (SDIO) Table 132. SDIO Register map (continued) dress Name 31 30 29 28 27 26 25 24 23 22 21 23 19 18 17 16 15 14 13 12 11 10 9 offset 0x34 SDIO_STA 0x38 SDIO_ICR 0x3C SDIO_MASK 0x48...
Page 468: Usb Full Speed Device Interface (Usb)
USB full speed device interface (USB) RM0008 USB full speed device interface (USB) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 469: Figure 189. Usb Peripheral Block Diagram
RM0008 USB full speed device interface (USB) Figure 189. USB peripheral block diagram USB Clock (48MHz) Analog Transceiver PCLK1 Control Clock RX-TX registers & logic Recovery Suspend Timer Control Endpoint Interrupt Selection registers & logic S.I.E. Packet Buffer Endpoint Endpoint Interface Registers Registers...
Page 470: Description Of Usb Blocks
USB full speed device interface (USB) RM0008 proper handshake packet over the USB is generated or expected according to the direction of the transfer. At the end of the transaction, an endpoint-specific interrupt is generated, reading status registers and/or using different interrupt response routines. The microcontroller can determine: ●...
Page 471: Programming Considerations
RM0008 USB full speed device interface (USB) ● Control Registers: These are the registers containing information about the status of the whole USB peripheral and used to force some USB events, such as resume and power-down. ● Interrupt Registers: These contain the Interrupt masks and a record of the events. They can be used to inquire an interrupt reason, the interrupt status or to clear the status of a pending interrupt.
Page 472: System And Power-On Reset
USB full speed device interface (USB) RM0008 20.4.2 System and power-on reset Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB peripheral and subsequently de-assert its reset signal so to be able to access its registers.
Page 473 RM0008 USB full speed device interface (USB) clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB1 bus. Different clock configurations are possible where the APB1 clock frequency can be higher or lower than the USB peripheral one.
Page 474: Figure 190. Packet Buffer Areas With Examples Of Buffer Description Table Locations
USB full speed device interface (USB) RM0008 Figure 190. Packet buffer areas with examples of buffer description table locations Buffer for double-buffered IN Endpoint 3 0001_1110 (1E) COUNT3_TX_1 0001_1100 (1C) ADDR3_TX_1 0001_1010 (1A) COUNT3_TX_0 Buffer for double-buffered 0001_1000 (18) ADDR3_TX_0 OUT Endpoint 2 0001_0110 (16) COUNT2_RX_1...
Page 475 RM0008 USB full speed device interface (USB) NUM_BLOCK fields. Unidirectional endpoints, except Isochronous and double-buffered bulk endpoints, need to initialize only bits and registers related to the supported direction. Once the transmission and/or reception are enabled, register USB_EPnR and locations ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX (respectively), should not be modified by the application software, as the hardware can change their value on the fly.
Page 476 USB full speed device interface (USB) RM0008 software). Data bytes subsequently received by the USB peripheral are packed in words (the first byte received is stored as least significant byte) and then transferred to the packet buffer starting from the address contained in the internal ADDR register while BUF_COUNT is decremented and COUNT is incremented at each byte transfer.
Page 477 RM0008 USB full speed device interface (USB) OUT transactions from SETUP ones. A USB device can determine the number and direction of data stages by interpreting the data transferred in the SETUP stage, and is required to STALL the transaction in the case of errors. To do so, at all data stages before the last, the unused direction should be set to STALL, so that, if the host reverses the transfer direction too soon, it gets a STALL as a status stage.
Page 478: Double-Buffered Endpoints
USB full speed device interface (USB) RM0008 20.4.3 Double-buffered endpoints All different endpoint types defined by the USB standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations. When large portions of data are to be transferred between the host PC and the USB function, the bulk endpoint type is the most suited model.
Page 479: Table 133. Double-Buffering Buffer Flag Definition
RM0008 USB full speed device interface (USB) Table 133. Double-buffering buffer flag definition Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint DTOG DTOG_TX (USB_EPnRbit 6) DTOG_RX (USB_EPnRbit 14) SW_BUF USB_EPnR bit 14 USB_EPnR bit 6 The memory buffer which is currently being used by the USB peripheral is defined by DTOG buffer flag, while the buffer currently in use by application software is identified by SW_BUF buffer flag.
Page 480: Isochronous Transfers
USB full speed device interface (USB) RM0008 actual endpoint status will be masked as ‘10’ (NAK) when a buffer conflict between the USB peripheral and the application software is detected (this condition is identified by DTOG and SW_BUF having the same value, see Table 134 on page 479).
Page 481: Suspend/Resume Events
RM0008 USB full speed device interface (USB) Table 135. Isochronous memory buffers usage Endpoint DTOG bit Packet buffer used by the Packet buffer used by the Type value USB peripheral application software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 buffer description table buffer description table locations.
Page 482: Table 136. Resume Event Detection
USB full speed device interface (USB) RM0008 A brief description of a typical suspend procedure is provided below, focused on the USB- related aspects of the application software routine responding to the SUSP notification of the USB peripheral: Set the FSUSP bit in the USB_CNTR register to 1. This action activates the suspend mode within the USB peripheral.
Page 483: Usb Registers
RM0008 USB full speed device interface (USB) In this case, the resume sequence can be started by setting the RESUME bit in the USB_CNTR register to ‘1’ and resetting it to 0 after an interval between 1mS and 15mS (this interval can be timed using ESOF interrupts, occurring with a 1mS period when the system clock is running at nominal frequency).
Page 484 USB full speed device interface (USB) RM0008 Bit 15 CTRM: Correct Transfer Interrupt Mask 0: Correct Transfer (CTR) Interrupt disabled. 1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. Bit 14 PMAOVRM: Packet Memory Area Over / Underrun Interrupt Mask 0: PMAOVR Interrupt disabled.
Page 485 RM0008 USB full speed device interface (USB) Bit 2 LP_MODE: Low-power mode This mode is used when the suspend-mode power constraints require that all static power dissipation is avoided, except the one required to supply the external pull-up resistor. This condition should be entered when the application is ready to stop all system clocks, or reduce their frequency in order to meet the power consumption requirements of the USB suspend condition.
Page 486 USB full speed device interface (USB) RM0008 Only the bits related to events, which are serviced, are cleared. At the end of the service routine, another interrupt will be requested, to service the remaining conditions. To avoid spurious clearing of some bits, it is recommended to clear them with a load instruction where all bits which must not be altered are written with 1, and all bits to be cleared are written with ‘0’...
Page 487 RM0008 USB full speed device interface (USB) Bit 10 RESET: USB RESET request Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB peripheral, in response to a RESET, just resets its internal protocol state machine, generating an interrupt if RESETM enable bit in the USB_CNTR register is set.
Page 488 USB full speed device interface (USB) RM0008 USB frame number register (USB_FNR) Address offset: 0x48 Reset value: 0x0XXX where X is undefined RXDP RXDM LSOF[1:0] FN[10:0] Bit 15 RXDP: Receive Data + Line Status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event.
Page 489 RM0008 USB full speed device interface (USB) USB device address (USB_DADDR) Address offset: 0x4C Reset value: 0x0000 Reserved ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Res. Bits 15:8 Reserved Bit 7 EF: Enable Function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
Page 490: Endpoint-Specific Registers
USB full speed device interface (USB) RM0008 20.5.2 Endpoint-specific registers The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0.
Page 491 RM0008 USB full speed device interface (USB) Bit 15 CTR_RX: Correct Transfer for reception This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated.
Page 492 USB full speed device interface (USB) RM0008 Bits 10:9 EP_TYPE[1:0]: Endpoint type These bits configure the behavior of this endpoint as described in Table 138: Endpoint type encoding on page 493. Endpoint 0 must always be a control endpoint and each USB function must have at least one control endpoint which has address 0, but there may be other control endpoints if required.
Page 493: Table 137. Reception Status Encoding
RM0008 USB full speed device interface (USB) Bit 6 DTOG_TX: Data Toggle, for transmission transfers If the endpoint is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission.
Page 494: Buffer Descriptor Table
USB full speed device interface (USB) RM0008 Table 139. Endpoint kind meaning EP_TYPE[1:0] EP_KIND Meaning BULK DBL_BUF CONTROL STATUS_OUT Not used INTERRUPT Not used Table 140. Transmission status encoding STAT_TX[1:0] Meaning DISABLED: all transmission requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake.
Page 495 RM0008 USB full speed device interface (USB) Transmission buffer address n (USB_ADDRn_TX) Address offset: [USB_BTABLE] + n*16 USB local address: [USB_BTABLE] + n*8 ADDRn_TX[15:1] Bits 15:1 ADDRn_TX[15:1]: Transmission Buffer Address These bits point to the starting address of the packet buffer containing data to be transmitted by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Page 496 USB full speed device interface (USB) RM0008 Reception buffer address n (USB_ADDRn_RX) Address offset: [USB_BTABLE] + n*16 + 8 USB local Address: [USB_BTABLE] + n*8 + 4 ADDRn_RX[15:1] Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address These bits point to the starting address of the packet buffer, which will contain the data received by the endpoint associated with the USB_EPnR register at the next OUT/SETUP token addressed to it.
Page 497: Usb Register Map
RM0008 USB full speed device interface (USB) Note: Double-buffered and Isochronous IN Endpoints have two USB_COUNTn_TX registers: named USB_COUNTn_TX_1 and USB_COUNTn_TX_0 with the following content. BLSIZE NUM_BLOCK_1[4:0] COUNTn_RX_1[9:0] BLSIZE NUM_BLOCK_0[4:0] COUNTn_RX_0[9:0] Table 141. Definition of allocated buffer memory Value of Memory allocated Memory allocated NUM_BLOCK[4:0]...
Page 498 USB full speed device interface (USB) RM0008 Table 142. USB register map and reset values (continued) Offset Register STAT_ STAT_ USB_EP2R TYPE EA[3:0] 0x08 Reserved [1:0] [1:0] [1:0] Reset value STAT_ STAT_ USB_EP3R TYPE EA[3:0] 0x0C Reserved [1:0] [1:0] [1:0] Reset value STAT_ STAT_...
Page 499: Controller Area Network (Bxcan)
RM0008 Controller area network (bxCAN) Controller area network (bxCAN) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 500: General Description
Controller area network (bxCAN) RM0008 Management ● Maskable interrupts ● Software-efficient mailbox mapping at a unique address space Note: The USB and CAN share a dedicated 512-byte SRAM memory for data transmission and reception, and so they cannot be used concurrently (the shared SRAM is accessed through CAN and USB exclusively).
Page 501: Figure 192. Can Block Diagram
RM0008 Controller area network (bxCAN) Control, status and configuration registers The application uses these registers to: ● Configure CAN parameters, e.g. baud rate ● Request transmissions ● Handle receptions ● Manage interrupts ● Get diagnostic information Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages. The transmission Scheduler decides which mailbox has to be transmitted first.
Page 502: Bxcan Operating Modes
Controller area network (bxCAN) RM0008 Figure 193. bxCAN operating modes Reset Sleep SLAK= 1 INAK = 0 Normal Initialization INRQ . ACK SLAK= 0 SLAK= 0 INAK = 1 INAK = 0 INRQ . SYNC . SLEEP Note: ACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the CAN_MSR register SYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive bits have been monitored on CANRX...
Page 503: Normal Mode
RM0008 Controller area network (bxCAN) To initialize the registers associated with the CAN filter banks (mode, scale, FIFO assignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter initialization also can be done outside the initialization mode. Note: When FINIT=1, CAN reception is deactivated.
Page 504: Silent Mode
Controller area network (bxCAN) RM0008 21.3.5 Silent mode The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register. In Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot start a transmission.
Page 505: Bxcan Functional Description
RM0008 Controller area network (bxCAN) connected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected from the bxCAN and the CANTX pin is held recessive. Figure 196. bxCAN in combined mode bxCAN CANTX CANRX 21.4 bxCAN functional description 21.4.1 Transmission handling...
Page 506: Time Triggered Communication Mode
Controller area network (bxCAN) RM0008 request while the mailbox is in transmit state can have two results. If the mailbox is transmitted successfully the mailbox becomes empty with the TXOK bit set in the CAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the transmission is aborted and becomes empty with TXOK cleared.
Page 507: Reception Handling
RM0008 Controller area network (bxCAN) 21.4.3 Reception handling For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox.
Page 508: Identifier Filtering
Controller area network (bxCAN) RM0008 If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message.
Page 509 RM0008 Controller area network (bxCAN) Refer to Figure 199. Furthermore, the filters can be configured in mask mode or in identifier list mode. Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. Identifier list mode In identifier list mode, the mask registers are used as identifier registers.
Page 510: Figure 199. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0008 Figure 199. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8] CAN_FxR0[7:0] Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8]...
Page 511: Figure 200. Example Of Filter Numbering
RM0008 Controller area network (bxCAN) Figure 200. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit)
Page 512: Message Storage
Controller area network (bxCAN) RM0008 Figure 201. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier...
Page 513: Table 143. Transmit Mailbox Mapping
RM0008 Controller area network (bxCAN) Table 143. Transmit mailbox mapping Offset to transmit mailbox base Register name address CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 514: Error Management
Controller area network (bxCAN) RM0008 21.4.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 515: Figure 203. Bit Timing
RM0008 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 516: Bxcan Interrupts
Controller area network (bxCAN) RM0008 Figure 204. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame...
Page 517: Figure 205. Event Flags And Interrupt Generation
RM0008 Controller area network (bxCAN) Figure 205. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE RQCP0 & CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 FMPIE1 & FIFO 1 FMP1 INTERRUPT FFIE1 &...
Page 518: Can Registers
Controller area network (bxCAN) RM0008 ● The error and status change interrupt can be generated by the following events: – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. –...
Page 519 RM0008 Controller area network (bxCAN) Bit 7 TTCM: Time Triggered Communication Mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 21.4.2: Time triggered communication mode.
Page 520 Controller area network (bxCAN) RM0008 CAN master status register (CAN_MSR) Address offset: 0x04 Reset value: 0x0000 0C02 Reserved Res. Reserved SAMP Reserved SLAKI WKUI ERRI SLAK INAK Res. Res. rc_w1 rc_w1 rc_w1 Bits 31:12 Reserved, forced by hardware to 0. Bit 11 RX: CAN Rx Signal Monitors the actual value of the CAN_RX Pin.
Page 521 RM0008 Controller area network (bxCAN) Bit 2 ERRI: Error Interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set.
Page 522 Controller area network (bxCAN) RM0008 Bit 27 TME1: Transmit Mailbox 1 Empty This bit is set by hardware when no transmit request is pending for mailbox 1. Bit 26 TME0: Transmit Mailbox 0 Empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0]: Mailbox Code In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free.
Page 523 RM0008 Controller area network (bxCAN) Bit 8 RQCP1: Request Completed Mailbox1 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in CAN_TI1R register).
Page 524 Controller area network (bxCAN) RM0008 Bit 31:6 Reserved, forced by hardware to 0. Bit 5 RFOM0: Release FIFO 0 Output Mailbox Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect.
Page 525 RM0008 Controller area network (bxCAN) Bit 3 FULL1: FIFO 1 Full Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 Reserved, forced by hardware to 0. Bits 1:0 FMP1[1:0]: FIFO 1 Message Pending These bits indicate how many messages are pending in the receive FIFO1.
Page 526 Controller area network (bxCAN) RM0008 Bit 7 Reserved, forced by hardware to 0. Bit 6 FOVIE1: FIFO Overrun Interrupt Enable 0: No interrupt when FOVR is set. 1: Interrupt generation when FOVR is set. Bit 5 FFIE1: FIFO Full Interrupt Enable 0: No interrupt when FULL bit is set.
Page 527 RM0008 Controller area network (bxCAN) Bits 6:4 LEC[2:0]: Last Error Code This field is set by hardware and holds a code which indicates the error condition of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’.
Page 528: Mailbox Registers
Controller area network (bxCAN) RM0008 Bits 25:24 SJW[1:0]: Resynchronization Jump Width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization. x (SJW[1:0] + 1) Bit 23 Reserved, forced by hardware to 0.
Page 529 RM0008 Controller area network (bxCAN) TX mailbox identifier register (CAN_TIxR) (x=0..2) Address offsets: 0x180, 0x190, 0x1A0 Reset value: 0xXX where X is undefined (except bit 0, TXRQ = 0) Note: All TX registers are write protected when the mailbox is pending transmission (TMEx reset). This register also implements the TX request control (bit 0) - reset value 0.
Page 530 Controller area network (bxCAN) RM0008 Bits 31:16 TIME[15:0]: Message Time Stamp This field contains the 16-bit timer value captured at the SOF transmission. Bits 15:9 Reserved Bit 8 TGT: Transmit Global Time This bit is active only when the hardware is in the Time Trigger Communication mode, TTCM bit of the CAN_MCR register is set.
Page 531 RM0008 Controller area network (bxCAN) Mailbox data high register (CAN_TDHxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x18C, 0x19C, 0x1AC Reset value: 0xXX where X is undefined DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]...
Page 532 Controller area network (bxCAN) RM0008 Bit 2 IDE: Identifier Extension This bit defines the identifier type of message in the mailbox. 0: Standard identifier. 1: Extended identifier. Bit 1 RTR: Remote Transmission Request 0: Data frame 1: Remote frame Bit 0 Reserved Receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1)
Page 533 RM0008 Controller area network (bxCAN) Receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: 0xXX where X is undefined Note: All RX registers are write protected.
Page 534: Can Filter Registers
Controller area network (bxCAN) RM0008 Bits 23:16 DATA6[7:0]: Data Byte 6 Data byte 2 of the message. Bits 15:8 DATA5[7:0]: Data Byte 5 Data byte 1 of the message. Bits 7:0 DATA4[7:0]: Data Byte 4 Data byte 0 of the message. 21.6.4 CAN filter registers CAN filter master register (CAN_FMR)
Page 535 RM0008 Controller area network (bxCAN) Bits 31:14 Reserved. Forced to 0 by hardware. Bits 13:0 FBMx: Filter Mode Mode of the registers of Filter x. 0: Two 32-bit registers of filter bank x are in Identifier Mask mode. 1: Two 32-bit registers of filter bank x are in Identifier List mode. CAN filter scale register (CAN_FS1R) Address offset: 0x20C Reset value: 0x00...
Page 536 Controller area network (bxCAN) RM0008 Bits 31:14 Reserved, forced by hardware to 0. Bits 13:0 FFAx: Filter FIFO Assignment for Filter x The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 CAN filter activation register (CAN_FA1R) Address offset: 0x21C...
Page 537: Bxcan Register Map
RM0008 Controller area network (bxCAN) In all configurations: Bits 31:0 FB[31:0] Filter Bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not.
Page 538 Controller area network (bxCAN) RM0008 Table 145. bxCAN - register map and reset values (continued) Offset Register CAN_BTR TS2[2:0] TS1[3:0] BRP[9:0] 0x01C Reserved Reserved Reset value 0x020- Reserved 0x17F CAN_TI0R STID[10:0]/EXID[28:18] EXID[17:0] 0x180 Reset value CAN_TDT0R TIME[15:0] DLC[3:0] 0x184 Reserved Reserved Reset value CAN_TDL0R...
Page 539 RM0008 Controller area network (bxCAN) Table 145. bxCAN - register map and reset values (continued) Offset Register CAN_BTR TS2[2:0] TS1[3:0] BRP[9:0] 0x01C Reserved Reserved Reset value 0x020- Reserved 0x17F CAN_TI0R STID[10:0]/EXID[28:18] EXID[17:0] 0x180 Reset value CAN_TDT0R TIME[15:0] DLC[3:0] 0x184 Reserved Reserved Reset value CAN_TDL0R...
Page 540 Controller area network (bxCAN) RM0008 Table 145. bxCAN - register map and reset values (continued) Offset Register CAN_BTR TS2[2:0] TS1[3:0] BRP[9:0] 0x01C Reserved Reserved Reset value 0x020- Reserved 0x17F CAN_TI0R STID[10:0]/EXID[28:18] EXID[17:0] 0x180 Reset value CAN_TDT0R TIME[15:0] DLC[3:0] 0x184 Reserved Reserved Reset value CAN_TDL0R...
Page 541 RM0008 Controller area network (bxCAN) Table 145. bxCAN - register map and reset values (continued) Offset Register CAN_RDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x1B8 Reset value CAN_RDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x1BC Reset value CAN_RI1R STID[10:0]/EXID[28:18] EXID[17:0] 0x1C0 Reset value CAN_RDT1R TIME[15:0] FMI[7:0] DLC[3:0]...
Page 542 Controller area network (bxCAN) RM0008 Table 145. bxCAN - register map and reset values (continued) Offset Register CAN_F1R1 FB[31:0] 0x248 Reset value CAN_F1R2 FB[31:0] 0x24C Reset value CAN_F13R1 FB[31:0] 0x2A8 Reset value CAN_F13R2 FB[31:0] 0x2AC Reset value 542/690...
Page 543: Serial Peripheral Interface (Spi)
RM0008 Serial peripheral interface (SPI) Serial peripheral interface (SPI) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 544: Spi And I S Main Features
Serial peripheral interface (SPI) RM0008 22.2 SPI and I S main features 22.2.1 SPI features ● Full-duplex synchronous transfers on three lines ● Simplex synchronous transfers on two lines with or without a bidirectional data line ● 8- or 16-bit transfer frame format selection ●...
Page 545: I 2 S Features
RM0008 Serial peripheral interface (SPI) 22.2.2 S features ● Simplex communication (only transmitter or receiver) ● Master or slave operations ● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 48 kHz) ● Data format may be 16-bit, 24-bit or 32-bit ●...
Page 546: Spi Functional Description
Serial peripheral interface (SPI) RM0008 22.3 SPI functional description 22.3.1 General description The block diagram of the SPI is shown in Figure 206. Figure 206. SPI block diagram Address and data bus Read Rx buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE Shift register MISO...
Page 547: Figure 207. Single Master/ Single Slave Application
RM0008 Serial peripheral interface (SPI) Figure 207. Single master/ single slave application Master Slave MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI SPI clock generator Not used if NSS is managed by software ai14745 1.
Page 548 Serial peripheral interface (SPI) RM0008 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
Page 549: Figure 209. Data Clock Timing Diagram
RM0008 Serial peripheral interface (SPI) Figure 209. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MISO LSBit MSBit (from master) 8 or 16 bits depending on Data Frame Format (see SPI_CR1) MOSI LSBit MSBit (from slave) (to slave) Capture strobe CPHA =0...
Page 550: Spi Slave Mode
Serial peripheral interface (SPI) RM0008 22.3.2 SPI slave mode In slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate.
Page 551: Simplex Communication
RM0008 Serial peripheral interface (SPI) Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 209).
Page 552: Status Flags
Serial peripheral interface (SPI) RM0008 1 clock and 1 data wire (receive-only in full-duplex mode) In order to free an I/O pin so it can be used for other purposes, it is possible to disable the SPI output function by setting the RXONLY bit in the SPI_CR1 register. In this case, SPI will function in Receive-only mode.
Page 553: Spi Communication Using Dma (Direct Memory Addressing)
RM0008 Serial peripheral interface (SPI) Note: This SPI offers two kinds of CRC calculation standard which depend directly on the data frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data (CRC16-CCITT). CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR).
Page 554: Error Flags
Serial peripheral interface (SPI) RM0008 At the end of data and CRC transfers, the CRCERR flag in SPI_SR is set if corruption occurs during the transfer. 22.3.8 Error flags Master mode fault (MODF) Master mode fault occurs when the master device has its NSS pin pulled low (in hardware mode) or SSI bit low (in software mode), this automatically sets the MODF bit.
Page 555: Disabling The Spi
RM0008 Serial peripheral interface (SPI) 22.3.9 Disabling the SPI When transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by resetting the SPE bit. Disabling the SPI peripheral while the last data transfer is still ongoing does not affect the data reliability if the device is not in Master transmit mode.
Page 556: Figure 210. I 2 S Block Diagram
Serial peripheral interface (SPI) RM0008 Figure 210. I S block diagram Address and data bus Tx buffer BSY OVR MODF CRC TxE RxNE SIDE 16-bit MOSI/ SD Shift register MISO LSB first Communication 16-bit control Rx buffer NSS/WS I2SCFG I2SSTD CKPOL DATLEN [1:0]...
Page 557: Supported Audio Protocols
RM0008 Serial peripheral interface (SPI) An additional pin could be used when a master clock output is needed for some external audio devices: ● MCK: Master Clock (mapped separately) is used, when the I S is configured in master mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 ×...
Page 558: Figure 211. I 2 S Phillips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
Serial peripheral interface (SPI) RM0008 Figure 211. I S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) Transmission Reception May be 16-bit, 32-bit LSB MSB Channel left Channel right Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 559: Figure 214. Receiving 0X8Eaa33
RM0008 Serial peripheral interface (SPI) ● In reception mode: if data 0x8EAA33 is received: Figure 214. Receiving 0x8EAA33 Second read from Data register First read from Data register 0x8EAA 0x3300 Only the 8MSB are right The 8 LSB will always be 00 Figure 215.
Page 560: Figure 217. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
Serial peripheral interface (SPI) RM0008 MSB justified standard For this standard, the WS signal is generated at the same time as the first data bit, which is the MSBit. Figure 217. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 Transmission Reception May be 16-bit, 32-bit...
Page 561: Figure 220. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0
RM0008 Serial peripheral interface (SPI) LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats). Figure 220. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 Transmission Reception May be 16-bit, 32-bit LSB MSB...
Page 562: Figure 223. Operations Required To Receive 0X3478Ae
Serial peripheral interface (SPI) RM0008 Figure 223. Operations required to receive 0x3478AE Second read from Data register First read from Data register conditioned by RXNE = ‘1’ conditioned by RXNE = ‘1’ 0x0034 0x78AE Only the 8 LSB bits of the half-word are significant.
Page 563: Figure 226. Pcm Standard Waveforms (16-Bit)
RM0008 Serial peripheral interface (SPI) PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPI_I2SCFGR. Figure 226. PCM standard waveforms (16-bit) short frame up to 13-bit...
Page 564: Clock Generator
Serial peripheral interface (SPI) RM0008 22.4.3 Clock generator The I S bitrate determines the dataflow on the I S data line and the I S clock signal frequency. S bitrate = number of bits per channel × number of channels × sampling audio frequency For a 16-bit audio, left and right channel, the I S bitrate is calculated as follows: S bitrate = 16 ×...
Page 565: I 2 S Master Mode
RM0008 Serial peripheral interface (SPI) When the master clock is disabled (MCKOE bit cleared): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide 22.4.4 S master mode The I S can be configured in master mode.
Page 566: I 2 S Slave Mode
Serial peripheral interface (SPI) RM0008 To ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with the next data to transmit before the end of the current transmission. To switch off the I S, by clearing I2SE, it is mandatory to wait for TXE = 0 and BSY = 0. Reception sequence The operating mode is the same as for the transmission mode except for the point 3, where the configuration should set the master reception mode through the I2SCFG[1:0] bits.
Page 567 RM0008 Serial peripheral interface (SPI) master transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the external master. This means that the slave needs to be ready to transmit the first data before the clock is generated by the master. WS assertion corresponds to channel Left transmitted first.
Page 568: Status Flags
Serial peripheral interface (SPI) RM0008 22.4.6 Status flags Three status flags are provided for the application to fully monitor the state of the I S bus. Busy flag (BSY) This flag indicates the state of the I S communication layer. It is set to indicate that the I S is busy communicating and/or that there is a valid data half-word in the Tx buffer awaiting transmission.
Page 569: I 2 S Interrupts
RM0008 Serial peripheral interface (SPI) Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in SPI_CR2.
Page 570 Serial peripheral interface (SPI) RM0008 Bit 15 BIDIMODE: Bidirectional data mode enable 0: 2-line unidirectional data mode selected 1: 1-line bidirectional data mode selected Note: Not used in I2S mode Bit 14 BIDIOE: Output enable in bidirectional mode This bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode 0: Output disabled (receive-only mode) 1: Output enabled (transmit-only mode) Notes: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
Page 571 RM0008 Serial peripheral interface (SPI) Bit 6 SPE: SPI Enable 0: Peripheral disabled 1: Peripheral enabled Note: Not used in I S mode Bits 5:3 BR[2:0]: Baud Rate Control 000: f PCLK 001: f PCLK 010: f PCLK 011: f PCLK 100: f PCLK...
Page 572: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface (SPI) RM0008 22.5.2 SPI control register 2 (SPI_CR2) Address offset: 0x04 Reset value: 0x0000 RXNE TXDMA RXDMA Reserved TXEIE ERRIE reserved SSOE Res. Res. Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 TXEIE: Tx buffer Empty Interrupt Enable 0: TXE interrupt masked 1: TXE interrupt not masked.
Page 573: Spi Status Register (Spi_Sr)
RM0008 Serial peripheral interface (SPI) 22.5.3 SPI status register (SPI_SR) Address offset: 08h Reset value: 0x0002 CHSID Reserved MODF RXNE Res. rc_w0 Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 BSY: Busy flag 0: SPI (or I2S) not busy 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and reset by hardware.
Page 574: Spi Data Register (Spi_Dr)
Serial peripheral interface (SPI) RM0008 Bit 2 CHSIDE: Channel side 0: Channel Left has to be transmitted or has been received 1: Channel Right has to be transmitted or has been received Note: Not used for the SPI mode No meaning in PCM mode Bit 1 TXE: Transmit buffer Empty 0: Tx buffer not empty 1: Tx buffer empty...
Page 575: Spi Crc Polynomial Register (Spi_Crcpr)
RM0008 Serial peripheral interface (SPI) 22.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.
Page 576: Spi Tx Crc Register (Spi_Txcrcr) (Not Used In I 2 S Mode)
Serial peripheral interface (SPI) RM0008 22.5.7 SPI Tx CRC register (SPI_TXCRCR) (not used in I S mode) Address offset: 0x18 Reset value: 0x0000 TxCRC[15:0] Bits 15:0 TxCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes.
Page 577 RM0008 Serial peripheral interface (SPI) Bit 7 PCMSYNC: PCM frame synchronization 0: Short frame synchronization 1: Long frame synchronization Notes: This bit has a meaning only if I2SSTD = 11 (PCM standard is used) Not used for the SPI mode Bit 6 Reserved: forced at 0 by hardware Bit 5:4 I2SSTD: I S standard selection...
Page 578: Spi_I S Prescaler Register (Spi_I2Spr)
Serial peripheral interface (SPI) RM0008 22.5.9 SPI_I S Prescaler register (SPI_I2SPR) Address offset: 20h Reset value: 0000 0010 (0002h) MCKO Reserved I2SDIV Res. Bits 15:10 Reserved: Forced to 0 by hardware Bit 9 MCKOE: Master Clock Output Enable 0: Master clock output is disabled 1: Master clock output is enabled Notes: This bit should be configured when the I S is disabled.
Page 579: Spi Register Map
RM0008 Serial peripheral interface (SPI) 22.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 148. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset Value SPI_CR2 0x04 Reserved Reset Value SPI_SR 0x08...
Page 580: Inter-Integrated Circuit (I 2 C) Interface
Inter-integrated circuit (I C) interface RM0008 Inter-integrated circuit (I C) interface Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 581: I 2 C Functional Description
RM0008 Inter-integrated circuit (I C) interface – Acknowledgement failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled ● 2 Interrupt vectors: – 1 Interrupt for successful address/ data communication –...
Page 582: Figure 230. I2C Bus Protocol
Inter-integrated circuit (I C) interface RM0008 In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode).
Page 583: I2C Slave Mode
RM0008 Inter-integrated circuit (I C) interface Figure 231. I C block diagram DATA REGISTER DATA DATA SHIFT REGISTER CONTROL PEC CALCULATION COMPARATOR OWN ADDRESS REGISTER DUAL ADDRESS REGISTER CLOCK PEC REGISTER CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTERS (CR1&CR2) CONTROL STATUS REGISTERS LOGIC (SR1&SR2)
Page 584: Figure 232. Transfer Sequence Diagram For Slave Transmitter
Inter-integrated circuit (I C) interface RM0008 Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: ● An acknowledge pulse if the ACK bit is set ●...
Page 585: Figure 233. Transfer Sequence Diagram For Slave Receiver
RM0008 Inter-integrated circuit (I C) interface Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ●...
Page 586: I2C Master Mode
Inter-integrated circuit (I C) interface RM0008 23.3.3 C master mode In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a Start condition and ends with a Stop condition. Master mode is selected as soon as the Start condition is generated on the bus with a START bit.
Page 587 RM0008 Inter-integrated circuit (I C) interface Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. ● In 10-bit addressing mode, sending the header sequence causes the following event: – The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Page 588: Figure 234. Transfer Sequence Diagram For Master Transmitter
Inter-integrated circuit (I C) interface RM0008 Closing the communication After writing the last byte to the DR register, the STOP bit is set by software to generate a Stop condition (see Figure 234 Transfer sequencing EV8_2). The interface goes automatically back to slave mode (M/SL bit cleared). Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
Page 589: Error Conditions
RM0008 Inter-integrated circuit (I C) interface After the Stop condition generation, the interface goes automatically back to slave mode (M/SL bit cleared). Figure 235. Transfer sequence diagram for master receiver 7-bit Master Receiver: Address Data1 Data2 DataN ..EV7_1 10-bit Master Receiver Header Address Header...
Page 590: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0008 Arbitration lost (ARLO) This error occurs when the I C interface detects an arbitration lost condition. In this case, ● The ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is set) ●...
Page 591: Table 149. Smbus Vs. I2C
RM0008 Inter-integrated circuit (I C) interface The System Management Bus Specification refers to three types of devices. A slave is a device that is receiving or responding to a command. A master is a device that issues commands, generates the clocks, and terminates the transfer. A host is a specialized master that provides the main interface to the system's CPU.
Page 592 Inter-integrated circuit (I C) interface RM0008 Address resolution protocol (ARP) SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device. The Address Resolution Protocol (ARP) has the following attributes: ● Address assignment uses the standard SMBus physical layer arbitration mechanism ●...
Page 593: Dma Requests
RM0008 Inter-integrated circuit (I C) interface How to use the interface in SMBus mode To switch from I C mode to SMBus mode, the following sequence should be performed. ● Set the SMBus bit in the I2C_CR1 register ● Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the application If you want to configure the device as a master, follow the Start condition generation procedure in...
Page 594: Packet Error Checking
Inter-integrated circuit (I C) interface RM0008 When the number of data transfers which has been programmed in the DMA Controller registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt vector.
Page 595: I 2 C Interrupts
RM0008 Inter-integrated circuit (I C) interface ● If DMA and PEC calculation are both enabled:- – In transmission: when the I C interface receives an EOT signal from the DMA controller, it automatically sends a PEC after the last byte. –...
Page 596: I 2 C Debug Mode
Inter-integrated circuit (I C) interface RM0008 Figure 236. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBAlert 23.5 C debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module.
Page 597 RM0008 Inter-integrated circuit (I C) interface Bit 15 SWRST: Software Reset When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are released and the bus is free. 0: I C Peripheral not under reset 1: I C Peripheral under reset state Note:...
Page 598 Inter-integrated circuit (I C) interface RM0008 Bit 8 START: Start Generation This bit is set and cleared by software and cleared by hardware when start is sent or PE=0. In Master Mode: 0: No Start generation 1: Repeated start generation In Slave mode: 0: No Start generation 1: Start generation when the bus is free...
Page 599: Control Register 2 (I2C_Cr2)
RM0008 Inter-integrated circuit (I C) interface 23.6.2 Control register 2 (I2C_CR2) Address offset: 0x04 Reset value: 0x0000 ITBUF ITEVT ITER Reserved LAST Reserved FREQ[5:0] Res. Res. Bits 15:13 Reserved, forced by hardware to 0. Bit 12 LAST: DMA Last Transfer 0: Next DMA EOT is not the last transfer 1: Next DMA EOT is the last transfer Note:...
Page 600: Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I C) interface RM0008 Bit 8 ITERREN: Error Interrupt Enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 –...
Page 601: Own Address Register 2 (I2C_Oar2)
RM0008 Inter-integrated circuit (I C) interface 23.6.4 Own address register 2 (I2C_OAR2) Address offset: 0x0C Reset value: 0x0000 Reserved ADD2[7:1] ENDUAL Res. Bits 15:8 Reserved, forced by hardware to 0. Bits 7:1 ADD2[7:1]: Interface address bits 7:1 of address in dual addressing mode Bit 0 ENDUAL: Dual addressing mode enable 0: Only OAR1 is recognized in 7-bit addressing mode 1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode...
Page 602: Status Register 1 (I2C_Sr1)
Inter-integrated circuit (I C) interface RM0008 23.6.6 Status register 1 (I2C_SR1) Address offset: 0x14 Reset value: 0x0000 TIME STOP ARLO BERR RxNE ADD10 ADDR ALERT Res. Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15 SMBALERT: SMBus Alert In SMBus host mode: 0: no SMBAlert 1: SMBAlert event occurred on pin In SMBus slave mode:...
Page 603 RM0008 Inter-integrated circuit (I C) interface Bit 10 AF: Acknowledge Failure. 0: No acknowledge failure 1: Acknowledge failure – Set by hardware when no acknowledge is returned. – Cleared by software writing 0, or by hardware when PE=0. Bit 9 ARLO: Arbitration Lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master...
Page 604 Inter-integrated circuit (I C) interface RM0008 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 605: Status Register 2 (I2C_Sr2)
RM0008 Inter-integrated circuit (I C) interface 23.6.7 Status register 2 (I2C_SR2) Address offset: 0x18 Reset value:0x0000 PEC[7:0] DUALF Res. BUSY HOST CALL AULT Bits 15:8 PEC[7:0] Packet Error Checking Register This register contains the internal PEC when ENPEC=1. Bit 7 DUALF: Dual Flag (Slave mode) 0: Received address matched with OAR1 1: Received address matched with OAR2 –...
Page 606: Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I C) interface RM0008 Bit 2 TRA: Transmitter/Receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on R/W bit of address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 607 RM0008 Inter-integrated circuit (I C) interface Bit 14 DUTY Fast Mode Duty Cycle 0: Fast Mode t high 1: Fast Mode t = 16/9 (see CCR) high Bits 13:12 Reserved, forced by hardware to 0. Bits 11:0 CCR[11:0] Clock Control Register in Fast/Standard mode (Master mode) Controls the SCL clock in master mode.
Page 608: Trise Register (I2C_Trise)
Inter-integrated circuit (I C) interface RM0008 23.6.9 TRISE Register (I2C_TRISE) Address offset: 0x20 Reset value: 0x0002 Reserved TRISE[5:0] Res. Bits 15:6 Reserved, forced by hardware to 0. Bits 5:0 TRISE[5:0]: Maximum Rise Time in Fast/Standard mode (Master mode) These bits must be programmed with the maximum SCL rise time given in the I C bus specification, incremented by 1.
Page 609: I2C Register Map
RM0008 Inter-integrated circuit (I C) interface 23.6.10 C register map The table below provides the I C register map and reset values. Table 151. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value...
Page 610: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Universal synchronous asynchronous receiver transmitter (USART) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 611: Usart Functional Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) ● Configurable multibuffer communication using DMA (direct memory access) – Buffering of received/transmitted bytes in reserved SRAM using centralized DMA ● Separate enable bits for Transmitter and Receiver ● Transfer detection flags: – Receive buffer full –...
Page 612 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ●...
Page 613 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 237. USART block diagram PRDATA PWDATA Write Read (DATA REGISTER) DR (CPU or DMA) (CPU or DMA) Receive Data Register (RDR) Transmit Data Register (TDR) IrDA SW_RX ENDEC Receive Shift Register Transmit Shift Register BLOCK IRDA_OUT IRDA_IN...
Page 614: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 238). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”...
Page 615: Transmitter
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 24.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 616: Figure 239. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 239. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 617: Receiver
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When no transmission is taking place, a write instruction to the USART_DR register places the data directly in the shift register, the data transmission starts, and the TXE bit is immediately set. When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set in the USART_CR1 register.
Page 618: Figure 240. Start Bit Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 240. Start bit detection RX state Idle Start bit RX line Ideal sample 10 11 12 13 14 15 16 clock sampled values Real 10 11 12 13 14 15 16 sample clock 6/16 7/16...
Page 619 RM0008 Universal synchronous asynchronous receiver transmitter (USART) When a character is received ● The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
Page 620: Table 152. Noise Detection From Sampled Data
Universal synchronous asynchronous receiver transmitter (USART) RM0008 when the new data is received during the reading sequence (between the USART_SR register read access and the USART_DR read access). Noise error Over-sampling techniques are used (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise.
Page 621: Fractional Baud Rate Generation
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When the framing error is detected: ● The FE bit is set by hardware ● The invalid data is transferred from the Shift register to the USART_DR register. ● No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt.
Page 622: Table 153. Error Calculation For Programmed Baud Rates
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Fraction (USARTDIV) = 12/16 = 0.75d Therefore USARTDIV = 27.75d Example 2: To program USARTDIV = 25.62d, This leads to: DIV_Fraction = 16*0.62d = 9.92d, nearest real number 10d = 0xA DIV_Mantissa = mantissa (25.620d) = 25d = 0x19 Then, USART_BRR = 0x19A Example 3: To program USARTDIV = 50.99d...
Page 623: Multiprocessor Communication
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 24.3.5 Multiprocessor communication There is a possibility of performing multiprocessor communication with the USART (several USARTs connected in a network). For instance one of the USARTs can be the master, its TX output is connected to the RX input of the other USART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.
Page 624: Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0008 The USART enters mute mode when an address character is received which does not match its programmed address. The RXNE flag is not set for this address byte and no interrupt nor DMA request is issued as the USART would have entered mute mode. It exits from mute mode when an address character is received which matches the programmed address.
Page 625: Lin (Local Interconnection Network) Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in USART_CR1 = 1). Transmission mode: If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s”...
Page 626 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 244. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set ‚ÄúShort‚Äù Break F RX line Capture Strobe Break State machine Idle...
Page 627: Usart Synchronous Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 245. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 628: Figure 246. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0008 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 629: Single Wire Half Duplex Communication
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 248. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 630: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0008 arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set. 24.3.10 Smartcard The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register.
Page 631: Figure 251. Parity Error Detection Using The 1.5 Stop Bits
RM0008 Universal synchronous asynchronous receiver transmitter (USART) NACK signal (pulling transmit line low for 1 baud clock) will cause a framing error on the transmitter side (configured with 1.5 stop bits). The application can handle re-sending of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted.
Page 632: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.3.11 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: ● LINEN, STOP and CLKEN bits in the USART_CR2 register, ●...
Page 633: Continuous Communication Using Dma
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Receiver: Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in USART_GTPR).
Page 634 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the DMA specification) to the USART_DR register whenever the TXE bit is set.
Page 635: Hardware Flow Control
RM0008 Universal synchronous asynchronous receiver transmitter (USART) case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which if set will issue an interrupt after the current byte with either of these errors. 24.3.13 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and...
Page 636: Figure 256. Cts Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0008 When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure below shows an example of communication with CTS flow control enabled.
Page 637: Usart Interrupts
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 24.4 USART interrupts Table 155. USART interrupt requests Enable Interrupt event Event flag Control bit Transmit Data Register Empty TXEIE CTS flag CTSIE Transmission Complete TCIE Received Data Ready to be Read RXNE RXNEIE Overrun Error Detected Idle Line Detected...
Page 638: Usart Mode Configuration
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.5 USART mode configuration Table 156. USART modes configuration USART modes USART1 USART2 USART3 UART4 UART5 Asynchronous mode Hardware Flow Control Multibuffer Communication (DMA) Multiprocessor Communication Synchronous Smartcard Half-Duplex (Single-Wire mode) IrDA 1. X = supported; NA = not applicable. 24.6 USART registers Refer to...
Page 639 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 7 TXE: Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It is cleared by a write to the USART_DR register.
Page 640 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 2 NE: Noise Error Flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit which...
Page 641: Data Register (Usart_Dr)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 24.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: Undefined Reserved Reserved DR[8:0] Res. Bits 31:9 Reserved, forced by hardware to 0. Bits 8:0 DR[8:0]: Data value. Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Page 642: Control Register 1 (Usart_Cr1)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 Reserved RXNE Reserved WAKE PEIE TXEIE TCIE IDLEIE Res. Bits 31:14 Reserved, forced by hardware to 0. Bit 13 UE: USART Enable. When this bit is cleared the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.
Page 643 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 6 TCIE: Transmission Complete Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever TC=1 in the USART_SR register Bit 5 RXNEIE: RXNE Interrupt Enable. This bit is set and cleared by software.
Page 644: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 Reserved LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, forced by hardware to 0. Bit 14 LINEN: LIN mode enable This bit is set and cleared by software.
Page 645 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 LBCL: Last Bit Clock pulse. This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin.
Page 646: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.6.6 Control register 3 (USART_CR3) Address offset: 0x14 Reset value: 0x0000 Reserved Reserved CTSIE CTSE RTSE DMAT DMAR SCEN NACK IRLP IREN Res. Bits 31:11 Reserved, forced by hardware to 0. Bit 10 CTSIE: CTS Interrupt Enable. 0: Interrupt is inhibited 1: An interrupt is generated whenever CTS=1 in the USART_SR register Note: This bit is not available for UART4 &...
Page 647 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 NACK: Smartcard NACK enable. 0: NACK transmission in case of parity error is disabled 1: NACK transmission during parity error is enabled. Note: This bit is not available for UART4 & UART5. Bit 3 HDSEL: Half-Duplex Selection.
Page 648: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 24.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, forced by hardware to 0. Bits 15:8 GT[7:0]: Guard time value. This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode.
Page 649: Usart Register Map
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 24.6.8 USART register map The table below gives the USART register map and reset values. Table 157. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction...
Page 650: Device Electronic Signature
Device electronic signature RM0008 Device electronic signature Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 651: Unique Device Id Register (96 Bits)
RM0008 Device electronic signature 25.2 Unique device ID register (96 bits) The unique device identifier is ideally suited: ● for use as serial numbers (for example USB string serial numbers or other end applications) ● for use as security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory ●...
Page 652 Device electronic signature RM0008 Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed U_ID(95:80) U_ID(79:64) Bits 31:0 U_ID(95:64): 95:64 Unique ID bits. 652/690...
Page 653: Debug Support (Dbg)
RM0008 Debug support (DBG) Debug support (DBG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 654: Figure 258. Block Diagram Of Stm32F10Xxx-Level And Cortex-M3-Level Debug Support
Debug support (DBG) RM0008 Figure 258. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support STM32F10x debug support Cortex-M3 debug support Bus Matrix DCode interface Data Cortex-M3 System Core interface JTMS/ SWDIO External Private TRACESWO Peripheral Bus (PPB) JTDI Trace Port TRACECK Bridge TPIU...
Page 655: Reference Arm Documentation
RM0008 Debug support (DBG) 26.2 Reference ARM documentation ● Cortex™-M3 r1p1 Technical Reference Manual (TRM) ● ARM Debug Interface V5 ● ARM CoreSight Design Kit revision r1p0 Technical Reference Manual 26.3 SWJ debug port (serial wire and JTAG) The STM32F10xxx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW- DP (2-pin) interface.
Page 656: Pinout And Debug Port Pins
Debug support (DBG) RM0008 JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins. This sequence is: Send more than 50 TCK cycles with TMS (SWDIO) =1 Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) Send more than 50 TCK cycles with TMS (SWDIO) =1 26.4...
Page 657: Internal Pull-Up And Pull-Down On Jtag Pins
RM0008 Debug support (DBG) Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are reset by the System Reset. ● REMAP_AF_REG (@ 0x4001 0004 in STM32F10xxx MCU) – READ: APB - No Wait State – WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full. Bit 26:24= SWJ_CFG[2:0] Set and cleared by software.
Page 658: Using Serial Wire And Releasing The Unused Debug Pins As Gpios
Debug support (DBG) RM0008 Once a JTAG I/O is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: ● JNTRST: Input pull-up ● JTDI: Input pull-up ●...
Page 659: Id Codes And Locking Mechanism
26.6.1 MCU device ID code The STM32F10xxx MCU integrates an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 26.15 on page...
Page 660: Boundary Scan Tap
Debug support (DBG) RM0008 Bits 31:16 REV_ID(15:0) Revision identifier This field indicates the revision of the device: In low-density devices: – 0x1000 = Revision A In medium-density devices: – 0x0000 = Revision A – 0x2000 = Revision B – 0x2001 = Revision Z –...
Page 661: Jtag Debug Port
RM0008 Debug support (DBG) 26.7 JTAG debug port A standard JTAG state machine is implemented with a 4-bit Instruction Register (IR) and five Data Registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual (TRM): Table 160. JTAG debug port data registers IR(3:0) Data register Details...
Page 662: Sw Debug Port
Debug support (DBG) RM0008 Table 161. 32-bit debug port registers addressed through the shifted value A[3:2] Address A(3:2) value Description Reserved DP CTRL/STAT register. Used to: – Request a system or debug power-up – Configure the transfer operation for AP accesses –...
Page 663: Sw-Dp State Machine (Reset, Idle States, Id Code)
RM0008 Debug support (DBG) Table 162. Packet request (8-bits) Name Description Start Must be “1” 0: DP Access APnDP 1: AP Access 0: Write Request 1: Read Request A(3:2) Address field of the DP or AP registers (refer to Table 161) Parity Single bit parity of preceding bits...
Page 664: Dp And Ap Read/Write Accesses
SW-DP registers Access to these registers are initiated when APnDP=0 Table 165. SW-DP registers CTRLSEL bit A(3:2) of SELECT Register Notes register The manufacturer code is not set to ST Read IDCODE code. 0x1BA01477 (identifies the SW-DP) Write ABORT 664/690...
Page 665: Sw-Ap Registers
RM0008 Debug support (DBG) Table 165. SW-DP registers (continued) CTRLSEL bit A(3:2) of SELECT Register Notes register Purpose is to: – request a system or debug power-up – configure the transfer operation for AP accesses Read/Write DP-CTRL/STAT – control the pushed compare and pushed verify operations.
Page 666: Core Debug
Debug support (DBG) RM0008 The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes) and consists of: Bits [8:4] = the bits[7:4] APBANKSEL of the DP SELECT register Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP. The AHB-AP of the Cortex-M3 includes 9 x 32-bits registers: Table 166.
Page 667: Capability Of The Debugger Host To Connect Under System Reset
RM0008 Debug support (DBG) Note: Important: these registers are not reset by a system reset. They are only reset by a power- on reset. Refer to the Cortex-M3 r1p1 TRM for further details. To Halt on reset, it is necessary to: ●...
Page 668: Dwt (Data Watchpoint Trigger)
Debug support (DBG) RM0008 26.13 DWT (data watchpoint trigger) The DWT unit consists of four comparators. They are configurable as: ● a hardware watchpoint or ● a trigger to an ETM or ● a PC sampler or ● a data address sampler. The DWT also provides some means to give some profiling informations.
Page 669: Table 168. Main Itm Registers
RM0008 Debug support (DBG) For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control Register must be set. Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which will send only TPIU synchronization packets and not ITM synchronization packets.
Page 670: Mcu Debug Component (Mcudbg)
Debug support (DBG) RM0008 Example of configuration To output a simple value to the TPIU: ● Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to Section 26.16.2: TRACE pin assignment Section 26.15.3: Debug MCU configuration register) ●...
Page 671: Debug Mcu Configuration Register
RM0008 Debug support (DBG) For the bxCAN, the user can choose to block the update of the receive register during a breakpoint. For the I C, the user can choose to block the SMBUS timeout during a breakpoint. 26.15.3 Debug MCU configuration register This register allows the configuration of the MCU under DEBUG.
Page 672 Debug support (DBG) RM0008 Bit 14 DBG_CAN_STOP: Debug CAN stopped when Core is halted 0: Same behavior as in normal mode. 1: The CAN receive registers are frozen. Bits 13:10 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=4..1) 0: The clock of the involved Timer Counter is fed even if the core is halted. 1: The clock of the involved Timer counter is stopped when the core is halted.
Page 673: Tpiu (Trace Port Interface Unit)
RM0008 Debug support (DBG) 26.16 TPIU (trace port interface unit) 26.16.1 Introduction The TPIU acts as a bridge between the on-chip trace data from the ITM. The output data stream encapsulates the trace source ID, that is then captured by a Trace Port Analyzer (TPA).
Page 674: Table 170. Synchronous Trace Pin Assignment
Debug support (DBG) RM0008 and in Serial Wire mode and provides better bandwidth output capabilities than asynchronous trace. Table 170. Synchronous TRACE pin assignment Trace synchronous mode STM32F10xxx pin TPUI pin name assignment Type Description TRACECK TRACE Clock TRACE Sync Data Outputs TRACED[3:0] PE[6:3] Can be 1, 2 or 4.
Page 675: Tpui Formatter
RM0008 Debug support (DBG) Table 171. Flexible TRACE pin assignment (continued) DBGMCU_CR TRACE I/O pin assigned register PB3 / Pins assigned for: PE2 / PE3 / PE4 / PE5 / PE6 / JTDO/ TRACE TRACE TRACE TRACE TRACE TRACES D[0] D[1] D[2] D[3]...
Page 676: Tpui Frame Synchronization Packets
Debug support (DBG) RM0008 For STM32F10xxx MCU, there is only one TRACE source (the ITM). But the formatter can not be disabled and must be used in bypass mode because the TRACECTL pin is not assigned. This way, the Trace Port Analyzer can decode part of the formatter protocol to determine the position of the trigger.
Page 677: Asynchronous Mode
RM0008 Debug support (DBG) The TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal to HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2. 26.16.7 Asynchronous mode This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO.
Page 678: 26.16.10 Example Of Configuration
Debug support (DBG) RM0008 Table 172. Important TPIU registers (continued) Address Register Description Bit 31-9 = always ‘0’ Bit 8 = TrigIn = always ‘1’ to indicate that triggers are indicated Bit 7-4 = always 0 Bit 3-2 = always 0 Bit 1 = EnFCont.
Page 679: Dbg Register Map
RM0008 Debug support (DBG) 26.17 DBG register map The following table summarizes the Debug registers. Table 173. DBG - register map and reset values Addr. Register DBGMCU_ REV_ID DEV_ID IDCODE Reserved Reset value DBGMCU_CR Reserved Reset value 679/690...
Page 680: Table 174. Document Revision History
Revision history RM0008 Revision history Table 174. Document revision history Date Revision Changes Document reference number changed from UM0306 to RM008. The changes below were made with reference to revision 1 of 01-Jun-2007 of UM0306. EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 42: ADC pins on page 151 and V...
Page 681: Figure 80. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 Revision history Table 174. Document revision history (continued) Date Revision Changes Figure 109: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 Figure 124: Output compare mode, toggle on OC1. modified. CKD definition modified in Section 13.4.1: Control register 1 (TIMx_CR1).
Page 682: Figure 237. Usart Block Diagram
Revision history RM0008 Table 174. Document revision history (continued) Date Revision Changes Figure 237: USART block diagram modified. Procedure modified in Character reception on page 618. Section 24.3.4: Fractional baud rate generation: – Equation legend modified – Table 153: Error calculation for programmed baud rates modified –...
Page 683: Figure 86. 6-Step Generation, Com Example (Ossr=1)
RM0008 Revision history Table 174. Document revision history (continued) Date Revision Changes Figure 4: Power supply overview on page 48 modified. Section 6.1.2: Power reset on page 70 modified. Section 6.2: Clocks on page 70 modified. Definition of Bits 26:24 modified in Section 7.4.2: AF remap and debug I/O configuration register (AFIO_MAPR) on page 117.
Page 684: Figure 95. General-Purpose Timer Block Diagram
Revision history RM0008 Table 174. Document revision history (continued) Date Revision Changes Section 6: Reset and clock control (RCC) on page – LSI calibration on page 74 added – Figure 7: Reset circuit on page 70 updated – APB2 peripheral reset register (RCC_APB2RSTR) on page 83 updated –...
Page 685 RM0008 Revision history Table 174. Document revision history (continued) Date Revision Changes Figure 204: CAN frames on page 516 modified. Bits 31:21 and bits 20:3 modified in TX mailbox identifier register (CAN_TIxR) (x=0..2) on page 529. Bits 31:21 and bits 20:3 modified in Rx FIFO mailbox identifier register (CAN_RIxR) (x=0..1) on page 531.
Page 686: Figure 257. Usart Interrupt Mapping Diagram
Revision history RM0008 Table 174. Document revision history (continued) Date Revision Changes Developed polynomial form updated in Section 3.2: CRC main features on page Figure 4: Power supply overview on page 48 modified. Section 4.1.2: Battery backup domain on page 49 modified.
Page 687 RM0008 Revision history Table 174. Document revision history (continued) Date Revision Changes This reference manual also applies to low-density STM32F101xx, STM32F102xx and STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections, definitions of low-density and medium-density devices updated. Section 1.3: Peripheral availability on page 32 added.
Page 688: Figure 229. I
RM0008 Index Index CAN_TDHxR ......531 CAN_TDLxR ......530 ADC_CR1 .
Page 689 RM0008 Index IWDG_KR ......356 TIMx_CCR2 ..... . 266 IWDG_PR .
Page 690 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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Memory and Bus Architecture

CRC Calculation Unit

Power Control (PWR)

Backup Registers (BKP)

Reset and Clock Control (RCC)

General-Purpose and Alternate-Function I/Os (Gpios and Afios)

Interrupts and Events

DMA Controller (DMA)

Analog-To-Digital Converter (ADC)

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