ST STM32F101 series Reference Manual page 1040

RM0008
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 RGUFS: Received Good Unicast Frames Status
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 RFAES: Received frames alignment error status
Bit 5 RFCES: Received frames CRC error status
Bits 4:0 Reserved, must be kept at reset value.
Ethernet MMC transmit interrupt register (ETH_MMCTIR)
Address offset: 0x0108
Reset value: 0x0000 0000
The Ethernet MMC transmit Interrupt register maintains the interrupts generated when
transmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is
a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that
caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective
counter must be read in order to clear the interrupt bit.
31 30 29 28 27 26 25 24 23 22
Reserved
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TGFS: Transmitted good frames status
Bits 20:16 Reserved, must be kept at reset value.
Bit 15 TGFMSCS: Transmitted good frames more single collision status
Bit 14 TGFSCS: Transmitted good frames single collision status
Bits 13:0 Reserved, must be kept at reset value.
Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
Address offset: 0x010C
Ethernet (ETH): media access control (MAC) with DMA controller
This bit is set when the received, good unicast frames, counter reaches half the maximum
value.
This bit is set when the received frames, with alignment error, counter reaches half the
maximum value.
This bit is set when the received frames, with CRC error, counter reaches half the maximum
value.
21 20 19 18 17 16 15
Reserved
rc_r
This bit is set when the transmitted, good frames, counter reaches half the maximum value.
This bit is set when the transmitted, good frames after more than a single collision, counter
reaches half the maximum value.
This bit is set when the transmitted, good frames after a single collision, counter reaches half
the maximum value.
14 13 12 11 10
rc_r rc_r
DocID13902 Rev 15
9 8 7 6 5 4 3
Reserved
2 1 0
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