Hardware Interrupts - Fujitsu F2MC-16LX Hardware Manual
Mb90550a/b series, 16-bit
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 3 INTERRUPTS
3.4
Hardware Interrupts
A hardware interrupt suspends the program the CPU is executing in response to an
interrupt request signal from an internal resource and transfers the control to a
program that the user has defined for interrupt processing.
■ Overview of Hardware Interrupts
A hardware interrupt occurs after comparing the interrupt level for an interrupt request with the
interrupt level mask register (ILM) in the PS of the CPU and after referencing the contents of the
I flag in the PS by hardware if the interrupt condition is satisfied.
The CPU performs one of the following operations when a hardware interrupt occurs:
•
Saving data to the system stack of the PC, PS, A, PCB, DTB, ADB, and DPR registers in the
CPU.
•
Setting the ILM in the PS register. The ILM is automatically set to the same level as the
currently requesting interrupt level.
•
Incorporating the contents of the corresponding interrupt vector and branching to the
interrupt vector.
■ Structure of Hardware Interrupts
The processing related to a hardware interrupt can be classified into the following three
structure elements:
❍ Internal Resources
Interrupt permission bit, interrupt request bit: Control interrupt requests from a resource.
❍ Interrupt Controller
ICR: Assigns an interrupt level, and evaluates the priority among simultaneous interrupt
requests.
❍ CPU
I and ILM: Compare the request interrupt level with the current level and distinguish between
Microcode: Contains the steps for interrupt processing.
Each interrupt is defined by the control register for an internal resource, the ICR for the interrupt
controller, and the contents of CCR in the CPU. For using a hardware interrupt, it is necessary
to define these three structure parts in advance on the software level. See section "3.6.1
Interrupt Control Register (ICR)" for the ICR.
The table of interrupt vectors referenced during interrupt processing is allocated to FFFC00
FFFFFF
H
58
interrupt permission statuses.
, and is shared by hardware and software interrupts.
to
H
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