Page 1 The following document contains information on Cypress products.
Page 2 FUJITSU MICROELECTRONICS CM44-10120-4E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90460/465 Series HARDWARE MANUAL...
Page 4 Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED...
Page 6 The manual describes the functions and operation of the MB90460/465 series. Note: F MC is a registered of Fujitsu Microelectronics Limited and stands for FUJITSU Flexible Microcontroller. ■ Trademarks The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Page 7 Chapter 12 16-bit Reload Timer This chapter describes the functions and operation of the MB90460/465 series 16-bit reload timer. Chapter 13 16-bit PPG Timer This chapter describes the functions and operation of the MB90460/465 series 16-bit PPG timer. Chapter 14 Multi-functional Timer This chapter describes the functions and operation of the MB90460/465 series multi-functional timer.
Page 8 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third- party's intellectual property right or other right by using such information.
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 MB90460/465 Series Features ......................2 MB90460/465 Series Product line-up ....................5 Block Diagram of MB90460/465 Series ....................7 Pin Assignment ........................... 8 Package Dimensions ........................11 I/O Pins and Pin Functions ....................... 14 I/O Circuit Types ..........................19 CHAPTER 2 NOTES ON HANDLING DEVICES ............
Page 11 Reset Cause Bits ..........................73 Status of Pins in a Reset ........................75 CHAPTER 5 CLOCK ....................... 77 Clock ..............................78 Block Diagram of the Clock Generation Block .................. 80 Clock Selection Register (CKSCR) ....................82 Clock Mode ............................84 Oscillation Stabilization Wait Interval ....................
Page 12 CHAPTER 8 MODE SETTING ..................157 Mode Setting ........................... 158 Mode Pins (MD2 to MD0) ....................... 159 Mode Data ............................160 CHAPTER 9 I/O PORT ....................163 Overview of I/O Port ........................164 Registers of I/O Port ........................166 Port 0 .............................. 167 9.3.1 Port 0 Registers (PDR0, DDR0 and RDR0) ................
Page 13 CHAPTER 12 16-BIT RELOAD TIMER ................229 12.1 Overview of the 16-bit Reload Timer ....................230 12.2 Block Diagram of the 16-bit Reload Timer ..................233 12.3 16-bit Reload Timer Pins ........................ 235 12.4 16-bit Reload Timer Registers ......................236 12.4.1 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1) ........
Page 14 14.5 Multi-functional Timer Interrupts ..................... 320 14.6 Operation of Multi-functional Timer ....................324 14.6.1 Operation of 16-bit free-run timer ....................325 14.6.2 Operation of 16-bit Output Compare ..................332 14.6.3 Operation of 16-bit Input Capture ....................337 14.6.4 Operation of Waveform Generator .................... 339 14.7 Usage Notes on the Multi-functional Timer ..................
Page 15 16.6.4 Pulse Width Measurement Mode Operation ................456 16.7 Usage Notes on the PWC Timer ....................461 16.8 Sample Programs for the PWC Timer .................... 464 CHAPTER 17 UART ......................467 17.1 Overview of UART .......................... 468 17.2 Block Diagram of UART ........................470 17.3 UART Pins ............................
Page 16 19.4 Usage Notes on the Delayed Interrupt Generator Module ............. 539 CHAPTER 20 8/10-BIT A/D CONVERTER ..............541 20.1 Overview of the 8/10-bit A/D Converter ..................542 20.2 Block Diagram of the 8/10-bit A/D Converter .................. 544 20.3 8/10-bit A/D Converter Pins ......................546 20.4 8/10-bit A/D Converter Registers ....................
Page 17 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING ................615 24.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard) ......... 616 24.2 Example of Connection for Serial Writing (When Power Supplied by User) ........618 24.3 Example of Connection for Serial Writing (When Power Supplied from Writer) ......620 24.4...
Page 18 Main changes in this edition Page Section Change Results The product name is changed to "MB90460/465 series". The function column of bit 14 in Table 5.3-1 is changed. CHAPTER 5 CLOCK · 5.3 Clock Selection Register (CKSCR) (" Writing has no effect on the operation." is added.) CHAPTER 6 LOW POWER CONSUMPTION MODE Figure 6.6-1 is changed.
Page 19 CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/ F462A/F463A CONNECTION FOR SERIAL Table 24.1-1 is changed. WRITING 24.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard) The vertical lines marked in the left side of the page show the changes.
Page 20: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB90460/465 series. 1.1 MB90460/465 Series Features 1.2 MB90460/465 Series Product line-up 1.3 Block Diagram of MB90460/465 Series 1.4 Pin Assignment 1.5 Package Dimensions 1.6 I/O Pins and Pin Functions 1.7 I/O Circuit Types...
Page 21: Mb90460/465 Series Features
CHAPTER 1 OVERVIEW MB90460/465 Series Features The MB90460/465 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing, proving to be suitable for various industrial machines and motor control (AC induction motor and brushless DC motor).
Page 22 Maximum of 51 ports ● 18-bit time-base counter/watchdog timer: 1 channel ● Watchdog timer: 1 channel ● PWC: 2 channels (MB90460 series), 1 channel (MB90465 series) ● 16-bit reload timer: 1 channel ● 16-bit PPG timer: 1 channel ● Multi-functional timer (for AC/DC motor control): 1 channel •...
Page 23 CHAPTER 1 OVERVIEW • Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time) ● Multi-pulse generator (for DC motor control): 1 channel (not present in MB90465 series) • 16-bit reload timer: 1 channel (can be used individually in MB90465 series) •...
Page 24: Mb90460/465 Series Product Line-Up
PPG timer: 3 channels 2 channels PWM mode or single-shot mode selectable 16-bit PPG timer Can be worked with multi-functional timer / multi-pulse generator (MB90460 series only) or individually 16-bit free-run timer with up or up/down mode selection and buffer: 1 channel Multi-functional...
Page 25 CHAPTER 1 OVERVIEW Table 1.2-1 MB90460/465 Series Product Line-up (2/2) Part number MB90V460 MB90F462 MB90F462A MB90F463A MB90462 MB90467 Parameter LQFP-64 (FPT-64P-M09: 0.65 mm pitch) Package PGA256 QFP-64 (FPT-64P-M06: 1.00 mm pitch) SDIP-64 (DIP-64P-M01: 1.78 mm pitch) Operating 5V ± 10% @16 MHz voltage...
Page 26: Block Diagram Of Mb90460/465 Series
CHAPTER 1 OVERVIEW Block Diagram of MB90460/465 Series Figure 1.3-1 shows a overall block diagram of the MB90460/465 series. ■ MB90460/465 Series Block Diagram Figure 1.3-1 MB90460/465 Series Overall Block Diagram Other pins Clock control Vss x 2, Vcc x 1, MD0-2, C circuit MC-16LX family core Time-base timer...
Page 27: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment Figure 1.4-1 to Figure 1.4-3 show the pin assignment diagrams for the MB90460/465 series. ■ FPT-64P-M06 Pin Assignment Figure 1.4-1 FPT-64P-M06 Pin Assignment P44/SNI1* P30* /RTO0 (U) P45/SNI2* P46/PPG2 P27/IN3 P50/AN0 P26/IN2 P51/AN1 P25/IN1 P52/AN2 P24/IN0 P53/AN3 P23/PWO1...
Page 28 CHAPTER 1 OVERVIEW ■ FPT-64P-M09 Pin Assignment Figure 1.4-2 FPT-64P-M09 Pin Assignment P45/SNI2* P27/IN3 P46/PPG2 P26/IN2 P50/AN0 P25/IN1 P51/AN1 P24/IN0 P52/AN2 P23/PWO1 P53/AN3 P22/PWI1 P54/AN4 P21/TO1 LQFP-64 P55/AN5 P20/TIN1 P56/AN6 P17/FRCK (TOP VIEW) P57/AN7 P16/INT6/TO0 (FPT-64P-M09) P15/INT5/TIN0 P14/INT4 P13/INT3 P60/SIN1 P12/INT2/DTTI1* P61/SOT1 P11/INT1...
Page 29 CHAPTER 1 OVERVIEW ■ DIP-64P-M01 Pin Assignment Figure 1.4-3 DIP-64P-M01 Pin Assignment P36/PPG1* P35* /RTO5 (Z) P37/PPG0 P34* /RTO4 (W) P40/SIN0 P33* /RTO3 (Y) P41/SOT0 P32* /RTO2 (V) P42/SCK0 P31* /RTO1 (X) P43/SNI0* P30* /RTO0 (U) P44/SNI1* P45/SNI2* P27/IN3 P46/PPG2 P26/IN2 SDIP-64 P50/AN0...
Page 30: Package Dimensions
1.00 –.012 –0.20 –0 0~15 0.25(.010) +.016 (.019±.004) +.020 .0543 .039 –.0 –.008 Dimensions in mm (inches). 2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6 Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/...
Page 31 0.25 (.017±.003) –0.20 1.20±0.20 +.006 .010 –.008 (.047±.008) (Stand off) "A" 0.10(.004) 0.10(.004) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/...
Page 32 0.50±0.20 0.10±0.10 (.020±.008) (.004±.004) "A" (Stand off) 0.60±0.15 (.024±.006) 0.65(.026) 0.32±0.05 0.13(.005) (.013±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003-2008 FUJITSU MICROELECTRONICS LIMITED F64018S-c-3-6 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/...
Page 33: I/O Pins And Pin Functions
CHAPTER 1 OVERVIEW I/O Pins and Pin Functions Table 1.6-1 lists the MB90460/465 series I/O pins and their functions. Table 1.7-1 lists the I/O circuit types. The letter in the "I/O circuit type" column in Table 1.6-1 refers to the letter in the "Type" column Table 1.7-1.
Page 34 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (2/5) Pin no. Pin status Pin name Function QFP- QFP- circuit during reset SDIP*3 M09*1 M06*2 General-purpose I/O ports. Can be used as interrupt request input channel 2. INT2 Input is enabled when "1" is set in EN2 in standby mode.
Page 35 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (3/5) Pin no. Pin status Pin name Function QFP- QFP- circuit during reset SDIP*3 M09*1 M06*2 P24 to P27 General-purpose I/O ports. Trigger input pins for input capture channels 0 to 3. 45 to 48 46 to 49 53 to 56 When input capture channels 0 to 3 are used for...
Page 36 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (4/5) Pin no. Pin status Pin name Function QFP- QFP- circuit during reset SDIP*3 M09*1 M06*2 General-purpose I/O ports. Trigger input pin for position detection of the Multi-pulse generator. When used for input SNI2*4 operation, this pin is enabled as required and must not be used for any...
Page 37 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (5/5) Pin no. Pin status Pin name Function QFP- QFP- circuit during reset SDIP*3 M09*1 M06*2 Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Mode input Input pins for operation mode specification. 20,21 21,22 28,29...
Page 38: I/O Circuit Types
CHAPTER 1 OVERVIEW I/O Circuit Types Table 1.7-1 summarize the I/O circuit types of MB90460/465 series ■ I/O Circuit Types Table 1.7-1 I/O Circuit Type (1/3) Classification Type Remarks Main clock(main clock crystal oscillator) • At an ocillation feedback resistor of Xout N-ch P-ch approximately 1MΩ...
Page 39 CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Type (2/3) Classification Type Remarks • CMOS output • CMOS input P-ch Pull-up control • Selectable pull-up resistor P-ch approximately 50 kΩ Pout • I = 4 mA Nout N-ch CMOS input Standby mode control •...
Page 40 CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Type (3/3) Classification Type Remarks • Power supply input protection circuit Analog input enable P-ch N-ch Analog input enable • A/D converter reference voltage (AVR) input pin with protection circuit • Hysteresis input P-ch Pout Nout...
Page 41 CHAPTER 1 OVERVIEW...
Page 42: Chapter 2 Notes On Handling Devices
CHAPTER 2 NOTES ON HANDLING DEVICES This chapter describes notes on Handling Devices. 2.1 Notes on Handling Devices...
Page 43: Notes On Handling Devices
CHAPTER 2 NOTES ON HANDLING DEVICES Notes on Handling Devices When handling devices, pay special attention to the following eight items or procedures: • Strict observation of maximum rated voltage (latch-up prevention) • Stabilization of supply voltage • Power-on • Treatment of unused input pins •...
Page 44 On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs.
Page 45 CHAPTER 2 NOTES ON HANDLING DEVICES...
Page 46: Chapter 3 Cpu
CHAPTER 3 This chapter describes memory space for the MB90460/ 465 series. 3.1 CPU 3.2 Memory Space 3.3 Memory Maps 3.4 Addressing 3.5 Memory Location of Multi-byte Data 3.6 Registers 3.7 Dedicated Registers 3.8 General-purpose Registers 3.9 Prefix Codes...
Page 47: Cpu
CHAPTER 3 CPU The F MC-16LX CPU is a 16-bit CPU designed for use in applications, such as welfare and mobile equipment, which require high-speed real-time processing. The instruction set of the F MC-16LX was designed for controllers so that it can perform various types of control at high speed and efficiency.
Page 48: Memory Space
CHAPTER 3 CPU Memory Space All I/O, programs and data are located in the 16-megabyte memory space of the F 16LX. A part of the memory space is used for special purposes, such as extended intelligent I/O service (EI OS) descriptors, general-purpose registers and vector tables. ■...
Page 49 CHAPTER 3 CPU ■ ROM Area ● Vector table area (address: FFFC00 to FFFFFF • This area is used as a vector table for vector call instructions, interrupt vectors and reset vectors. • This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address.
Page 50: Memory Maps
CHAPTER 3 CPU Memory Maps This section shows the memory map for each MB90460/465 series model. ■ Memory Maps Figure 3.3-1 shows the memory maps for the MB90460/465 series. Figure 3.3-1 Memory Maps Single-chip mode (with ROM mirroring function) FFFFFF ROM area Address #1 FC0000...
Page 51 CHAPTER 3 CPU Notes: • If single-chip mode (without ROM mirroring function) is selected, see "CHAPTER 22 MIRRORING FUNCTION SELECTION MODULE". • ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C compiler.
Page 52: Addressing
CHAPTER 3 CPU Addressing The methods for generating addresses are linear addressing and bank addressing. In linear addressing, the complete 24-bit address is specified directly by an instruction. In bank addressing, the upper 8 bits of the address are specified by a bank register for the required purpose, and the lower 16 bits of the address are specified by the instruction.
Page 53: Address Specification By Linear Addressing
CHAPTER 3 CPU 3.4.1 Address Specification by Linear Addressing The two types of address specification by linear addressing are specification of a 24-bit address directly in the operand and specification of the lower 24 bits of a 32-bit general- purpose register. ■...
Page 54: Address Specification By Bank Addressing
CHAPTER 3 CPU 3.4.2 Address Specification by Bank Addressing In address specification by bank addressing, the 16-Mbyte memory space is divided into 256 64-Kbyte banks. A bank address that corresponds to each space is specified in the bank register to determine the upper 8 bits of the address. The lower 16 bits of the address are specified by the instruction.
Page 55 CHAPTER 3 CPU Figure 3.4-4 shows the relationship between the memory space divisions and each register. See "3.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB)", for details. Figure 3.4-4 Sample Bank Addressing FFFFFF Program space : PCB (Program Bank Register) FF0000 0FFFFF Additional space...
Page 56: Memory Location Of Multi-Byte Data
CHAPTER 3 CPU Memory Location of Multi-byte Data Multi-byte data is written to memory sequentially from the lower address. If multi-byte data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits. If a reset signal is input immediately after the low-order data is written, the high-order data may not be written.
Page 57 CHAPTER 3 CPU ■ Storage of Multi-byte Data in a Stack Figure 3.5-3 shows the configuration of multi-byte data in a stack. Figure 3.5-3 Storage of Multi-byte Data in a Stack PUSH RW1,RW3 PUSHW RW1 (35A4 ) (6DF0 Address ‘n’ RW1: 35A4 RW3: 6DF0 *: Stack status after execution of the PUSHW instruction...
Page 58: Registers
CHAPTER 3 CPU Registers MC-16LX registers are classified into internal dedicated CPU registers and built-in RAM general-purpose registers. ■ Dedicated Registers and General-purpose Registers Dedicated registers are dedicated hardware inside the CPU with limited use in the CPU architecture. General-purpose registers exist together with RAM in the CPU address space. Just like dedicated registers, general-purpose registers can be accessed without addressing.
Page 59: Dedicated Registers
CHAPTER 3 CPU Dedicated Registers The following 11 registers are dedicated registers in the CPU. • Accumulator (A) • System stack pointer (SSP) • Program counter (PC) • Program bank register (PCB) • User stack pointer (USP) • User stack bank register (USB) •...
Page 60 CHAPTER 3 CPU Table 3.7-1 Initial Values of the Dedicated Registers Dedicated register Initial value Accumulator (A) Undefined User stack pointer (USP) Undefined System stack pointer (SSP) Undefined Processor status (PS) 13 12 Default value ⇒ 00000 -01xxxxx Program counter (PC) Value in reset vector (contents of FFFFDC , FFFFDD Direct page register (DPR)
Page 61: Accumulator (A)
CHAPTER 3 CPU 3.7.1 Accumulator (A) The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The accumulator is used to temporarily store the results of an arithmetic operation and data. The A register can be used as a 32-bit, 16-bit or 8-bit register. Various arithmetic operations can be performed between memory and other registers or between the AH register and the AL register.
Page 62 CHAPTER 3 CPU Figure 3.7-3 Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Zero Extension) MOV A,3000H (An instruction that zero-extends the contents at address 3000 stores the result in the AL register) Memory space A before execution XXXX 2456 B53000...
Page 63 CHAPTER 3 CPU Figure 3.7-6 Example of AL-AH Transfer in the Accumulator (A) (16 Bits, Register Indirect) (Instruction that performs a word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the MOVW A,@RW1+6 read value in the A register) Memory space...
Page 64: Stack Pointers (Usp, Ssp)
CHAPTER 3 CPU 3.7.2 Stack Pointers (USP, SSP) There are two types of stack pointers: a user stack pointer (USP) and a system stack pointer (SSP). Each stack pointer is a register that indicates the memory address of the location of the destination for saved data or a return address when PUSH instructions, POP instructions and subroutines are executed.
Page 65 CHAPTER 3 CPU Figure 3.7-7 Stack Operation Instruction and Dtack Pointer PUSHW A with the S flag set to "0" ⇒ Before execution A624 USB C6 F328 C6F326 S flag SSB 56 1234 ⇐ User stack is used ⇒ After execution A624 USB C6 F326...
Page 66: Processor Status (Ps)
CHAPTER 3 CPU 3.7.3 Processor Status (PS) The processor status (PS) consists of CPU control bits and bits that indicate the CPU status. The PS register consists of the following three registers: • Interrupt level mask register (ILM) • Register bank pointer (RP) •...
Page 67: Condition Code Register (Ps: Ccr)
CHAPTER 3 CPU 3.7.4 Condition Code Register (PS: CCR) The condition code register (CCR) is an 8-bit register that consists of the bits that indicate the results of an arithmetic operation and the contents of transfer data and bits that control interrupt request acceptance. ■...
Page 68 CHAPTER 3 CPU ● Overflow flag (V) Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Cleared to "0" if no overflow occurs. ● Carry flag (C) Set to "1" when there is an overflow from the MSB or an underflow from the LSB because of an arithmetic calculation.
Page 69: Register Bank Pointer (Ps: Rp)
CHAPTER 3 CPU 3.7.5 Register Bank Pointer (PS: RP) The register bank pointer (RP) is a register that indicates the first address of the general-purpose register bank currently being used. The RP is used for real address conversion when general-purpose register addressing is used. ■...
Page 70: Interrupt Level Mask Register (Ps: Ilm)
CHAPTER 3 CPU 3.7.6 Interrupt Level Mask Register (PS: ILM) The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the interrupt currently accepted by the CPU.CHAPTER 7 INTERRUPT ■ Interrupt Level Mask Register (ILM) Figure 3.7-12 shows the configuration of the interrupt level mask register (ILM).
Page 71: Program Counter (Pc)
CHAPTER 3 CPU 3.7.7 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the memory address of the next instruction code to be executed by the CPU. ■ Program Counter (PC) The program bank register (PCB) specifies the upper 8 bits of the address where the next instruction code to be executed by the CPU is stored.
Page 72: Direct Page Register (Dpr)
CHAPTER 3 CPU 3.7.8 Direct Page Register (DPR) The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. ■ Direct Page Register (DPR) As shown in Figure 3.7-14, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed.
Page 73: Bank Registers (Pcb, Dtb, Usb, Ssb, Adb)
CHAPTER 3 CPU 3.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) Bank registers specify the highest 8-bit address by bank addressing. The five bank registers are as follows: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) •...
Page 74: General-Purpose Registers
CHAPTER 3 CPU General-purpose Registers The general-purpose registers are a memory block allocated in RAM at 000180 00037F as banks, each of which consists of eight 16-bit segments. The general-purpose registers can be used as general-purpose 8-bit registers (byte registers R0 to R7), 16-bit registers (word registers RW0 to RW7) or 32-bit registers (long-word registers RL0 to RL7).
Page 75 CHAPTER 3 CPU ■ Register Bank A register bank can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7, long-word registers RL0 to RL3) for various arithmetic operations and pointers. A long-word register can be used as a linear pointer that directly accesses the entire memory space. The contents of the register bank, like ordinary RAM, are not initialized by a reset.
Page 76: Prefix Codes
CHAPTER 3 CPU Prefix Codes Prefix codes are placed before an instruction to partially change the operation of the instruction. The three types of prefix codes are as follows: • Bank select prefix (PCB, DTB, ADB, SPB) • Common register bank prefix (CMR) •...
Page 77: Bank Select Prefix (Pcb, Dtb, Adb, Spb)
CHAPTER 3 CPU 3.9.1 Bank Select Prefix (PCB, DTB, ADB, SPB) A bank select prefix is placed before an instruction to select the memory space accessed by the instruction regardless of the addressing method. ■ Bank Select Prefixes (PCB, DTB, ADB, SPB) The memory space used for data access is defined for each addressing method.
Page 78 CHAPTER 3 CPU Table 3.9-3 Instructions whose use requires Caution when Bank Select Prefix Codes are used Instruction type Instruction Explanation CCR, #imm8 The effect of the prefix extends to the next Flag change instruction CCR, #imm8 instruction. The effect of the prefix extends to the next ILM setting instruction ILM, #imm8 instruction.
Page 79: Common Register Bank Prefix (Cmr)
CHAPTER 3 CPU 3.9.2 Common Register Bank Prefix (CMR) The common register bank (CMR) prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when RP = 0) at 000180 to 00018F regardless of the current register bank pointer (RP) value.
Page 80: Flag Change Suppression Prefix (Ncc)
CHAPTER 3 CPU 3.9.3 Flag Change Suppression Prefix (NCC) The flag change suppression prefix (NCC) code is placed before an instruction to suppress a flag change accompanying the execution of the instruction. ■ Flag Change Suppression Prefix (NCC) The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes. If a flag change suppression prefix code is placed before an instruction, a flag change accompanying the execution of the instruction is suppressed.
Page 81: Restrictions On Prefix Codes
CHAPTER 3 CPU 3.9.4 Restrictions on Prefix Codes The following three restrictions are imposed on the use of prefix codes: • Interrupt/hold requests are not accepted during the execution of prefix codes and interrupt/hold suppression instructions. • If a prefix code is placed before an interrupt/hold instruction, the effect of the prefix code is delayed.
Page 82 CHAPTER 3 CPU ● Delay of the effect of prefix codes As shown in Figure 3.9-2, if a prefix code is placed before an interrupt/hold suppression instruction, the prefix code takes effect with the first instruction executed after the interrupt/hold suppression instruction. Figure 3.9-2 Interrupt/hold Suppression Instructions and Prefix Codes Interrupt suppression instructions …...
Page 83 CHAPTER 3 CPU...
Page 84: Chapter 4 Reset
CHAPTER 4 RESET This chapter describes the reset for the MB90460/465 series microcontrollers. 4.1 Reset 4.2 Reset Causes and Oscillation Stabilization Wait Intervals 4.3 External Reset Pin 4.4 Reset Operation 4.5 Reset Cause Bits 4.6 Status of Pins in a Reset...
Page 85: Reset
CHAPTER 4 RESET Reset If a reset cause is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. When the reset is cleared, the CPU begins processing at the address indicated by the reset vector. There are four causes of a reset: Power-on reset Watchdog timer overflow...
Page 86 CHAPTER 4 RESET ● Software reset A software reset is an internal reset of three machine cycles (3/φ) generated by writing "0" to the RST bit of the low power consumption mode control register (LPMCR). The oscillation stabilization wait interval is not required for software resets.
Page 87: Reset Causes And Oscillation Stabilization Wait Intervals
CHAPTER 4 RESET Reset Causes and Oscillation Stabilization Wait Intervals The F MC-16LX has four reset causes. The oscillation stabilization wait interval for a reset depends on the reset cause. ■ Reset Causes and Oscillation Stabilization Wait Intervals Table 4.2-1 and Figure 4.2-1 summarize reset causes and oscillation stabilization wait intervals. Table 4.2-1 Reset Causes and Oscillation Stabilization Wait Intervals Oscillation stabilization wait interval Reset cause...
Page 88: External Reset Pin
CHAPTER 4 RESET External Reset Pin The external reset pin (RSTX pin) is a dedicated pin for inputting, with an L level signal, a reset and generating an internal reset by the L level input. For MB90460/465 series microcontrollers, resets are generated in synchronization with the CPU operating clock.
Page 89 CHAPTER 4 RESET ● Block diagram of internal reset for external pin Figure 4.3-2 Block Diagram of Internal Reset for External Pin RSTX P-ch N-ch Internal reset signal Input buffer HCLK: Oscillation clock...
Page 90: Reset Operation
CHAPTER 4 RESET Reset Operation When a reset is cleared, the memory locations from which the mode data and the reset vector are read are selected according to the setting of the mode pins, and the mode setting data is fetched. Mode setting data determines the CPU operating mode and the execution start address after a reset operation ends.
Page 91 CHAPTER 4 RESET ■ Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data stored in the hardware memory to the appropriate registers in the CPU core. The reset vector and mode data are allocated to the four bytes from FFFFDC to FFFFDF .
Page 92: Reset Cause Bits
CHAPTER 4 RESET Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). ■ Reset Cause Bits As shown in Figure 4.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC).
Page 93 CHAPTER 4 RESET ■ Correspondence between Reset Cause Bits and Reset Causes Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 4.5-1 maps the correspondence between the reset cause bits and reset causes. Figure 4.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register) Watchdog timer control register Address : 0000A8...
Page 94: Status Of Pins In A Reset
CHAPTER 4 RESET Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins during a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = 011 ●...
Page 95 CHAPTER 4 RESET...
Page 96: Chapter 5 Clock
CHAPTER 5 CLOCK This chapter describes the clock used by MB90460/465 series microcontrollers. 5.1 Clock 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Interval 5.6 Connection of an Oscillator or an External Clock to the Microcontroller...
Page 97: Clock
CHAPTER 5 CLOCK Clock The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. This internal clock is called the machine clock. One internal clock cycle is regarded as one machine cycle. Other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal PLL oscillation, called a PLL clock.
Page 98 CHAPTER 5 CLOCK ■ Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls operation of the CPU and peripheral functions, the operation of the CPU and peripheral functions is affected by switching of the main clock and the PLL clock (clock mode) and a change in the PLL clock multiplier.
Page 99: Block Diagram Of The Clock Generation Block
CHAPTER 5 CLOCK Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Oscillation stabilization wait interval selector ■...
Page 100 CHAPTER 5 CLOCK ● System clock generation circuit The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator attached to it. Alternatively, an external clock can be input to this circuit. ● PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock through PLL oscillation and supplies a clock that is a multiple of the frequency to the CPU clock selector.
Page 101: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCK Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to set switching between the main clock and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a PLL clock multiplier. ■ Configuration of the Clock Selection Register (CKSCR) Figure 5.3-1 shows the configuration of the clock selection register (CKSCR).
Page 102 CHAPTER 5 CLOCK Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) Bit name Function bit15, RESV: (Note) bit11 Reserved bit "1" must always be written to these bits. • This bit indicates whether the main clock or a PLL clock has been selected as the machine clock.
Page 103: Clock Mode
CHAPTER 5 CLOCK Clock Mode Two clock modes are provided: main clock mode and PLL clock mode. ■ Main Clock Mode and PLL Clock Mode ● Main clock mode In main clock mode, the main clock, whose frequency is the oscillation clock divided by 2, is used as the operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
Page 104 CHAPTER 5 CLOCK Figure 5.4-1 shows the status change caused by the machine clock switching. Figure 5.4-1 Status Dhange Diagram for Machine Dlock Selection Power-on Main PLLx Main MCS = 1 MCS = 0 MCM = 1 MCM = 1 CS1, CS0 = xx CS1, CS0 = xx PLL1: Multiplied...
Page 105: Oscillation Stabilization Wait Interval
CHAPTER 5 CLOCK Oscillation Stabilization Wait Interval When the power is turned on, when stop mode is released, or when a watchdog timer reset occurs, the oscillation clock starts, oscillation is unstable initially. Therefore, an oscillation stabilization wait interval is required. When the switch from the main clock to a PLL clock occurs, an oscillation stabilization wait interval is also required when PLL oscillation starts.
Page 106: Connection Of An Oscillator Or An External Clock To The Microcontroller
CHAPTER 5 CLOCK Connection of an Oscillator or an External Clock to the Microcontroller The F MC-16LX microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. ■...
Page 107 CHAPTER 5 CLOCK...
Page 108: Chapter 6 Low Power Consumption Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE This chapter describes the low power consumption mode of MB90460/465 series microcontrollers. 6.1 Low Power Consumption Mode 6.2 Block Diagram of the Low Power Consumption Control Circuit 6.3 Low Power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Change Diagram...
Page 109: Low Power Consumption Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE Low Power Consumption Mode MC-16LX microcontrollers have the following CPU operating modes, any of which can be used depending on the operating clock selection and clock operation control: • Clock mode (PLL clock mode and main clock mode) •...
Page 110 CHAPTER 6 LOW POWER CONSUMPTION MODE ■ Clock Mode ● PLL clock mode A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. ● Main clock mode The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU and peripheral functions.
Page 111: Block Diagram Of The Low Power Consumption Control Circuit
CHAPTER 6 LOW POWER CONSUMPTION MODE Block Diagram of the Low Power Consumption Control Circuit The low power consumption control circuit consists of the following seven blocks: • CPU intermittent operation selector • Standby clock control circuit • CPU clock control circuit •...
Page 112 CHAPTER 6 LOW POWER CONSUMPTION MODE ● CPU intermittent operation selector This selector selects the number of clock pulses the CPU is to be halted during CPU intermittent operation mode. ● Standby control circuit The standby control circuit controls the CPU clock control circuit and the peripheral clock control circuit, and turns the low power consumption mode on and off.
Page 113: Low Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW POWER CONSUMPTION MODE Low Power Consumption Mode Control Register (LPMCR) The low power consumption mode control register (LPMCR) switches to or releases low power consumption mode. It is also used to set the number of CPU clock pulses the CPU is to be halted during CPU intermittent mode.
Page 114 CHAPTER 6 LOW POWER CONSUMPTION MODE Table 6.3-1 Function Description of Each Bit of the Low Power Consumption Mode Control Register (LPMCR) Bit name Function • This bit indicates switching to stop mode. • When "1" is written to this bit, a switch to stop mode. STP: •...
Page 115 CHAPTER 6 LOW POWER CONSUMPTION MODE ■ Access to the Low Power Consumption Mode Control Register Switching to low power consumption mode (including stop mode and sleep mode) is performed by writing to the low power consumption mode control register. Only the instructions listed in Table 6.3-2 should be used for this purpose.
Page 116: Cpu Intermittent Operation Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE CPU Intermittent Operation Mode CPU intermittent operation mode is used for intermittent operation of the CPU while external buses and peripheral functions continue to operate at high speed. Its purpose is to reduce power consumption. ■...
Page 117: Standby Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE Standby Mode Standby mode includes the sleep (PLL sleep and main sleep), time-base timer and stop modes. ■ Operating Status during Standby Mode Table 6.5-1 summarizes the operating statuses during standby mode. Table 6.5-1 Operation Statuses during Standby Mode Condition Release Standby mode...
Page 118: Sleep Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE 6.5.1 Sleep Mode Sleep mode causes the CPU operating clock to stop while other components continue to operate. When the low power consumption mode control register (LPMCR) indicates a switch to sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set. Alternatively, a switch to main sleep mode occurs if main clock mode has been set.
Page 119 CHAPTER 6 LOW POWER CONSUMPTION MODE ● Return to normal mode by an interrupt If an interrupt request higher than level 7 is issued from a peripheral circuit during sleep mode, sleep mode is released. After release, the CPU handles the interrupt as it would any other interrupt. The CPU executes processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR).
Page 120 CHAPTER 6 LOW POWER CONSUMPTION MODE Figure 6.5-2 Release of PLL Sleep Mode (by External Reset) RSTX pin Sleep mode Main clock Oscillating PLL clock Oscillating PLL clock CPU clock Inactive Reset sequence Execution CPU operation Sleep mode released. Reset cleared.
Page 121: Time-Base Timer Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE 6.5.2 Time-base Timer Mode Time-base timer mode causes the microcontroller operation to stop with the exception of the source oscillation and the time-base timer. All functions other than time-base timer are deactivated. ■ Switching to Time-base Timer Mode Writing "0"...
Page 122 CHAPTER 6 LOW POWER CONSUMPTION MODE Figure 6.5-3 shows the operation for return to normal mode from time-base timer mode triggered by an external reset. Figure 6.5-3 Release of Time-base Timer Mode (by an External Reset) RSTX pin Time-base timer mode Main clock Oscillating PLL clock...
Page 123: Stop Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE 6.5.3 Stop Mode Stop mode causes the source oscillation to stop and deactivates all functions. It therefore saves the most power saving while data is being retained. ■ Switching to Stop Mode Writing "1" to the STP bit of LPMCR triggers a switch to stop mode. At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL stop mode.
Page 124 CHAPTER 6 LOW POWER CONSUMPTION MODE Note: When interrupt processing is executed normally, the CPU first executes the instruction that follows the instruction in which switching to stop mode was specified. The CPU then proceeds to interrupt processing. Figure 6.5-4 shows the operation of return to normal mode from stop mode. Figure 6.5-4 Release of Main Stop Mode (by External Reset) RSTX pin Stop mode...
Page 125: State Change Diagram
CHAPTER 6 LOW POWER CONSUMPTION MODE State Change Diagram Figure 6.6-1 shows the state change diagram of F MC-16LX operation and gives change conditions. ■ State Change Diagram Figure 6.6-1 State Change Diagram Power-on Main clock mode Main clock Source Osc. [12] Main time-base stabilization wait and...
Page 126 CHAPTER 6 LOW POWER CONSUMPTION MODE ■ Low Power Consumption Mode Operating States Table 6.6-1 lists the operating states of low power consumption mode. Table 6.6-1 Low Power Consumption Mode Operating States Low power Condition Release consumption Oscillation Clock Peripheral for transition event mode...
Page 127 CHAPTER 6 LOW POWER CONSUMPTION MODE ● Switching to and release of standby mode Table 6.6-3 lists switching to and release of standby mode. Table 6.6-3 Switching to and Release of Standby Mode Transition Conditions Transition to main sleep [21] SLP = 1, MCS = 1 (Transition from main run state) mode [2] SLP =1, MCS = 1 (Transition from PLL run state) [22] Interrupt input...
Page 128: State Of Pins In Standby Mode And During Reset
CHAPTER 6 LOW POWER CONSUMPTION MODE State of Pins in Standby Mode and during Reset The state of pins in standby mode and during reset are summarized below for each memory access mode. ■ Software Pull-up Resistor For pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during L level output.
Page 129: Usage Notes On Low Power Consumption Mode
CHAPTER 6 LOW POWER CONSUMPTION MODE Usage Notes on Low Power Consumption Mode Note the following six items to use low power consumption mode: • Switching to standby mode and interrupts • Release of standby mode by an interrupt • Setting of standby mode •...
Page 130 CHAPTER 6 LOW POWER CONSUMPTION MODE ■ Release of Stop Mode To use an external interrupt for releasing stop mode, use an input that has been set as an interrupt input cause before the system enters stop mode. As an input cause, H level, L level, rising edge or falling edge can be selected.
Page 131 CHAPTER 6 LOW POWER CONSUMPTION MODE...
Page 132: Chapter 7 Interrupt
CHAPTER 7 INTERRUPT This chapter explains the interrupt and extended intelligent I/O service (EI OS) in the MB90460/465 series. 7.1 Interrupt 7.2 Interrupt Causes and Interrupt Vectors 7.3 Interrupt Control Registers and Peripheral Functions 7.4 Hardware Interrupt 7.5 Software Interrupt 7.6 Interrupt of Extended Intelligent I/O Service (EI 7.7 Exception Processing Interrupt 7.8 Stack Operations for Interrupt Processing...
Page 133: Interrupt
CHAPTER 7 INTERRUPT Interrupt This chapter explains the interrupt and extended intelligent I/O service (EI OS) in the MB90460/465 series. • Hardware interrupt • Software interrupt • Interrupt from extended intelligent I/O service (EI • Exception processing ■ Interrupt Types and Functions ●...
Page 134 CHAPTER 7 INTERRUPT ■ Interrupt Operation Figure 7.1-1 shows the activation and return processing for the four types of interrupt functions. Figure 7.1-1 Overall Flow of Interrupt Operation Main program Is there a valid hardware interrupt Interrupt activation/return request? String type * processing instruction being executed...
Page 135: Interrupt Causes And Interrupt Vectors
CHAPTER 7 INTERRUPT Interrupt Causes and Interrupt Vectors The F MC-16LX has functions for handling 256 types of interrupt causes. The 256 interrupt vector tables are allocated to the memory at the highest addresses. These interrupt vectors are shared by all interrupts. Software interrupt can use all these interrupt vectors (INT0 to INT256).
Page 136 CHAPTER 7 INTERRUPT ■ Interrupt Causes and Interrupt Vectors/interrupt Control Registers Table 7.2-2 shows the relationship among interrupt causes (excluding software interrupt), interrupt vectors, and interrupt control registers. Table 7.2-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Interrupt vector Interrupt control register Interrupt cause Priority...
Page 137 CHAPTER 7 INTERRUPT O:Can be used and interrupt request flag is cleared by EI OS interrupt clear signal. X:Cannot be used. :Can be used and support the EI OS stop request. ∆:Usable when an interrupt cause that shares the ICR is not used. *1:- For peripheral functions that share the ICR register, the interrupt level will be the same.
Page 138: Interrupt Control Registers And Peripheral Functions
CHAPTER 7 INTERRUPT Interrupt Control Registers and Peripheral Functions Interrupt control registers (ICR00 to ICR15) are located inside the interrupt controller. The interrupt control registers correspond to all peripheral functions that have the interrupt function. These registers control interrupts and the extended intelligent I/O service (EI OS).
Page 139 CHAPTER 7 INTERRUPT ■ Interrupt Control Register Functions All interrupt control registers (ICR) do the following • Set the interrupt level of the corresponding peripheral function • Select ordinary interrupt or the extended intelligent I/O service as interrupt of the corresponding peripheral function OS) channel •...
Page 140: Interrupt Control Registers (Icr00 To Icr15)
CHAPTER 7 INTERRUPT 7.3.1 Interrupt Control Registers (ICR00 to ICR15) Interrupt control registers correspond to all peripheral functions that have the interrupt function. The interrupt control registers control the processing when an interrupt request occurs. The functions of these registers partially differ at writing and reading. ■...
Page 141 CHAPTER 7 INTERRUPT Figure 7.3-2 Interrupt Control Registers (ICR00 to ICR15) during reading Reading Address Initial value 0000B0 XX000111 0000BF Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) OS enable bit Activates the interrupt sequence when an interrupt occurs Activates EI OS when an interrupt occurs OS status...
Page 142: Interrupt Control Register Functions
CHAPTER 7 INTERRUPT 7.3.2 Interrupt Control Register Functions The interrupt control registers (ICR00 to ICR15) consist of the following four functional bits: • Interrupt level setting bits (IL2 to IL0) • Extended intelligent I/O service (EI OS) enable bit (ISE) •...
Page 143 CHAPTER 7 INTERRUPT Table 7.3-2 Correspondence between the Interrupt Level Setting Bits and Interrupt Levels Interrupt level 0 (highest priority) 6 (lowest priority) 7 (no interrupt) ● Extended intelligent I/O service (EI OS) enable bit (ISE) If this bit is "1" when an interrupt request is generated, EI OS is activated.
Page 144 CHAPTER 7 INTERRUPT Table 7.3-3 Correspondence between the EI OS Channel Selection Bits and Eescriptor Addresses (2 / 2) ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 000140 000148 000150 000158 000160 000168 000170 000178 ● Extended intelligent I/O service (EI OS) status bits (S1, S0) These are read-only bits.
Page 145: Hardware Interrupt
CHAPTER 7 INTERRUPT Hardware Interrupt The hardware interrupt function temporarily interrupts the program being executed by the CPU and transfers control to a user-defined interrupt processing program in response to an interrupt signal from a peripheral function. The extended intelligent I/O service (EI OS) and external interrupt are executed as a type of hardware interrupt.
Page 146 CHAPTER 7 INTERRUPT ■ Hardware Interrupt Structure Table 7.4-1 lists four mechanisms used for hardware interrupt. These four mechanisms must be included in the program before hardware interrupt can be used. Table 7.4-1 Mechanisms used for Hardware Interrupt Mechanism Function Interrupt enable bit, interrupt Controls interrupt requests from a peripheral Peripheral function...
Page 147 CHAPTER 7 INTERRUPT ● Hardware interrupt suppression by interrupt suppression instruction The ten types of hardware interrupt suppression instructions listed in Table 7.4-2 ignore interrupt requests without detecting whether a hardware interrupt request exists. Table 7.4-2 Hardware Interrupt Suppression Instruction Interrupt/hold suppression instructions Prefix code (instructions that delay the effect of the prefix code)
Page 148: Operation Of Hardware Interrupt
CHAPTER 7 INTERRUPT 7.4.1 Operation of Hardware Interrupt This section explains hardware interrupt operation from generation of a hardware interrupt request to the completion of interrupt processing. ■ Hardware Interrupt Activation ● Peripheral function operation (generation of an interrupt request) A peripheral function that has a hardware interrupt request function also has an interrupt request flag that indicates the presence of interrupt requests and an interrupt enable flag that determines whether CPU interrupt requests are enabled or disabled.
Page 149 CHAPTER 7 INTERRUPT ■ Hardware Interrupt Operation Figure 7.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion of interrupt processing. Figure 7.4-2 Hardware Interrupt Operation Internal bus Microcode Check Comparator Other peripheral functions Peripheral function that generated the interrupt request Level Interrupt...
Page 150: Processing For Interrupt Operation
CHAPTER 7 INTERRUPT 7.4.2 Processing for Interrupt Operation When an interrupt request is generated by the peripheral function, the interrupt controller transmits the interrupt level to the CPU. If the CPU is able to accept interrupt, the interrupt controller temporarily interrupts the instruction currently being executed. The interrupt controller then executes the interrupt processing routine or activates the extended intelligent I/O service (EI OS).
Page 151: Procedure For Using Hardware Interrupt
CHAPTER 7 INTERRUPT 7.4.3 Procedure for using Hardware Interrupt Before hardware interrupt can be used, the system stack area, peripheral function, and interrupt control register (ICR) must be set. ■ Procedure for using Hardware Interrupt Figure 7.4-4 shows an example of the procedure for using hardware interrupt. Figure 7.4-4 Procedure for using Hardware Interrupt Start Set the system stack area...
Page 152: Multiple Interrupts
CHAPTER 7 INTERRUPT 7.4.4 Multiple Interrupts Multiple hardware interrupts can be implemented by setting different interrupt levels in the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in response to multiple interrupt requests from peripheral functions. Use of multiple interrupts, however, is not possible with the extended intelligent I/O service.
Page 153 CHAPTER 7 INTERRUPT Figure 7.4-5 Example of Multiple Interrupts Main program A/D interrupt processing Timer interrupt processing Interrupt level 2 (ILM = 010) Interrupt level 1 Peripheral initialization (ILM = 001) Timer interrupt A/D interrupt generated generated Timer interrupt processing Interrupted Restart Main processing restarts...
Page 154: Hardware Interrupt Processing Time
CHAPTER 7 INTERRUPT 7.4.5 Hardware Interrupt Processing Time From the generation of a hardware interrupt request to the execution of an interrupt processing routine, the time for the instruction currently being executed to terminate and the time required to handle an interrupt are necessary. ■...
Page 155 CHAPTER 7 INTERRUPT ● Interrupt handling time (φ machine cycle) The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it receives an interrupt request. The required handling time for this processing is f machine cycles. The interrupt handling time is calculated with the following formula: When an interrupt is activated: θ...
Page 156: Software Interrupt
CHAPTER 7 INTERRUPT Software Interrupt When the software interrupt instruction (INT instruction) is executed, the software interrupt function transfers control from the program being executed by the CPU to the user-defined interrupt processing program. Hardware interrupt is disabled during execution of a software interrupt. ■...
Page 157 CHAPTER 7 INTERRUPT ■ Software Interrupt Operation Figure 7.5-1 shows software interrupt operation from the generation of a software interrupt to the completion of interrupt processing. Figure 7.5-1 Software Interrupt Operation Register file B unit Microcode Fetch Queue MC-16LX CPU Save Instruction bus Processor status...
Page 158: Interrupt Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 7 INTERRUPT Interrupt of Extended Intelligent I/O Service (EI The extended intelligent I/O service (EI OS) automatically transfers data between a peripheral function (I/O) and memory. When the data transfer terminates, a hardware interrupt is generated. ■ Extended Intelligent I/O Service (EI The extended intelligent I/O service is a type of hardware interrupt.
Page 159 CHAPTER 7 INTERRUPT Note: When the extended intelligent I/O service (EI OS) is operating, execution of the CPU program stops. ■ Operation of the Extended Intelligent I/O Service (EI Figure 7.6-1 shows EI OS operation. Figure 7.6-1 Extended Intelligent I/O Service (EI OS) Operation Memory space by IOA...
Page 160: Extended Intelligent I/O Service (Ei 2 Os) Descriptor (Isd)
CHAPTER 7 INTERRUPT 7.6.1 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) The extended intelligent I/O service (EI OS) descriptor (ISD) resides in internal RAM at 000100 to 00017F . The ISD consists of 8 bytes x 16 channels. ■ Configuration of the Extended Intelligent I/O Service (EI OS) Descriptor (ISD) The ISD consists of 8 bytes x 16 channels.
Page 161: Registers Of Ei 2 Os Descriptor (Isd)
CHAPTER 7 INTERRUPT 7.6.2 Registers of EI OS Descriptor (ISD) • Data counter (DCT) • I/O register address pointer (IOA) • EI OS status register (ISCS) • Buffer address pointer (BAP) Note: that the initial value of each register is undefined after a reset. ■...
Page 162 CHAPTER 7 INTERRUPT ■ Extended Intelligent I/O Service (EI OS) Status Register (ISCS) The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O register address pointer, transfer data format (byte or word), and transfer direction. Figure 7.6-5 shows the configuration of the ISCS.
Page 163 CHAPTER 7 INTERRUPT Figure 7.6-6 Configuration of Buffer Address Pointer (BAP) 16 15 Initial value xxxxxx BAPH BAPM BAPL (R/W) (R/W) (R/W) R/W: Read-write x: Undefined References: • The area that can be specified by the I/O address pointer (IOA) extends from 000000 00FFFF •...
Page 164: Operation Of The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 7 INTERRUPT 7.6.3 Operation of the Extended Intelligent I/O Service (EI If an interrupt request is generated by a peripheral function, EI OS activation is set in the corresponding interrupt control register (ICR) that the CPU uses EI OS to transfer data.
Page 165: Procedure For Using The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 7 INTERRUPT 7.6.4 Procedure for using the Extended Intelligent I/O Service Before the extended intelligent I/O service (EI OS) an be used, the system stack area, extended intelligent I/O service (EI OS) descriptor, interrupt function, and interrupt control register (ICR) must be set. ■...
Page 166: Processing Time Of The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 7 INTERRUPT 7.6.5 Processing Time of the Extended Intelligent I/O Service The time required for processing the extended intelligent I/O service (EI OS) changes according to the following factors: • EI OS status register (ISCS) setting • Address (area) pointed to by the I/O register address pointer (IOA) •...
Page 167 CHAPTER 7 INTERRUPT ● When the data counter (DCT) count terminates (final data transfer) Because the hardware interrupt is activated when data transfer by EI OS terminates, the interrupt handling time is added. The EI OS processing time when counting terminates is calculated with the following formula: OS processing time when counting terminates = EI OS processing time when data is transferred +...
Page 168: Exception Processing Interrupt
CHAPTER 7 INTERRUPT Exception Processing Interrupt In the F MC-16LX, the execution of an undefined instruction results in exception processing. Exception processing is basically the same as an interrupt. When the generation of an exception processing is detected on the instruction boundary, ordinary processing is interrupted and exception processing is executed.
Page 169: Stack Operations For Interrupt Processing
CHAPTER 7 INTERRUPT Stack Operations for Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are automatically saved to the system stack before a branch to interrupt processing. When the interrupt processing terminates, the previous processing is automatically restored from the stack.
Page 170 CHAPTER 7 INTERRUPT ■ Stack Area ● Stack area allocation The stack area is used for saving and restoring the program counter (PC) when the subroutine call instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt processing. The stack area is used for temporary saving and restoring of registers by the PUSHW and POPW instructions.
Page 171: Sample Programs For Interrupt Processing
CHAPTER 7 INTERRUPT Sample Programs for Interrupt Processing This section contains sample programs for interrupt processing. ■ Sample Programs for Interrupt Processing ● Processing specifications The following is a sample program for an interrupt that uses external interrupt 0 (INT0). ●...
Page 172 CHAPTER 7 INTERRUPT ;Unconditional jump ;---------Interrupt program ---------------------------------------------------------------------------------------------- ED_INT1: I:EIRR, #00H ;Acceptance of new INT0 not allowed RETI ;Return from interrupt CODE ENDS ;--------Vector setting----------------------------------------------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFACH ;Sets vector for interrupt #20 (14H) DSLED_INT1 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT...
Page 173 CHAPTER 7 INTERRUPT BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status IOAL 000104H ;Lower I/O address pointer IOAH 000105H ;Upper I/O address pointer DCTL 000106H ;Low-order data counter DCTH 000107H ;High-order data counter EIRR:0 ;Definition of external interrupt request flag bit STACK SSEG;Stack RW100...
Page 174 CHAPTER 7 INTERRUPT I:ENIR, #01H ;Enables INT0 interrupts ILM, #07H ;Sets the ILM in the PS to level 7 CCR, #40H ;Sets the I flag of the CCR in the PS and enables interrupts LOOP LOOP ;Infinite loop ;---------------Interrupt program----------------------------------------------------------------------------------------- WARI CLRB ;Clears interrupt/DTP request flag...
Page 175 CHAPTER 7 INTERRUPT...
Page 176: Chapter 8 Mode Setting
CHAPTER 8 MODE SETTING This chapter describes the operating modes and memory access modes supported by the MB90460/465 series. 8.1 Mode Setting 8.2 Mode Pins (MD2 to MD0) 8.3 Mode Data...
Page 177: Mode Setting
CHAPTER 8 MODE SETTING Mode Setting The F MC-16LX supports the modes for access method, and access areas. A mode is determined based on the settings by the mode pin at a reset as well as the mode data fetched. ■...
Page 178: Mode Pins (Md2 To Md0)
CHAPTER 8 MODE SETTING Mode Pins (MD2 to MD0) Three external pins, MD2 to MD0, are supported as the mode pins. These are used to specify how the reset vector and mode data are fetched. ■ Mode Pins (MD2 to MD0) The mode pins are used to select the data bus (external or internal) used for reading the reset vector and to specify the bus width when the external data bus is selected.
Page 179: Mode Data
CHAPTER 8 MODE SETTING Mode Data The mode data is at memory location FFFFDF , and is used to specify the operation after a reset sequence. The mode data is automatically fetched to the CPU. ■ Mode Data During a reset sequence, the mode data at address FFFFDF is fetched to the mode register in the CPU.
Page 180 CHAPTER 8 MODE SETTING Figure 8.3-2 shows the correspondence between access areas and physical addresses in single-chip mode. Figure 8.3-2 Correspondence between Access Areas and Physical Addresses in Single-chip Mode FFFFFF Model #1 FF0000 00FFFF When ROM mirroring function is selected Model #2 Model #3 : No access...
Page 181 CHAPTER 8 MODE SETTING...
Page 182: Chapter 9 I/O Port
CHAPTER 9 I/O PORT This chapter describes the functions and operation of the I/O port. 9.1 Overview of I/O Port 9.2 Registers of I/O Port 9.3 Port 0 9.4 Port 1 9.5 Port 2 9.6 Port 3 9.7 Port 4 9.8 Port 5 9.9 Port 6 9.10 Sample I/O Port Program...
Page 183: Overview Of I/O Port
CHAPTER 9 I/O PORT Overview of I/O Port An I/O port can be used as a general-purpose I/O port (parallel I/O port). The MB90460/ 465 series has 7 ports (51 lines). The ports are also used for resource I/O pins (peripheral function I/O pins).
Page 184 CHAPTER 9 I/O PORT Note: Port 5 is also used as analog input pins. To use the port as a general-purpose port, be sure to reset the corresponding bit of the analog data input enable register (ADER) to "0". Resetting the CPU sets the ADER register bits to "1".
Page 185: Registers Of I/O Port
CHAPTER 9 I/O PORT Registers of I/O Port This section provides a list of the registers related to the I/O port settings. ■ Registers for I/O Ports Table 9.2-1 is a list of the registers corresponding to individual port. Table 9.2-1 Registers and Corresponding port Register Read/Write Address...
Page 186: Port 0
CHAPTER 9 I/O PORT Port 0 Port 0 is a general-purpose I/O port. It can also be used for resource I/O. The port pins can be switched in units of bits between the I/O port and resource. This section focuses on the general I/O port function. This section also provides the configuration of port 0, lists of pins, shows a block diagram of the pins, and describes the corresponding registers.
Page 187 CHAPTER 9 I/O PORT ■ Block Diagram of Port 0 Pins Figure 9.3-1 is a block diagram of the port 0pins. Figure 9.3-1 Block Diagram of port 0 Pins Resource output Direct resource input Port data register (PDR) Resource output enable Pull-up resistor About 50k PDR read...
Page 188: Port 0 Registers (Pdr0, Ddr0 And Rdr0)
CHAPTER 9 I/O PORT 9.3.1 Port 0 Registers (PDR0, DDR0 and RDR0) This section describes the port 0 registers. ■ Functions of Port 0 Registers ● Port 0 data register (PDR0) The PDR0 register indicates the state of each pin of port 0. ●...
Page 189 CHAPTER 9 I/O PORT Table 9.3-3 lists the functions of the port 0 registers. Table 9.3-3 Port 0 Register Functions Read/ Register Data During reading During writing Address Initial value Write The output latch is loaded with 0. When The pin is at the the pin functions as an output port, the low level.
Page 190: Operation Of Port 0
CHAPTER 9 I/O PORT 9.3.2 Operation of Port 0 This section describes the operation of port 0. ■ Operation of Port 0 ● Port operation in output mode • Setting a bit of the DDR0 register to "1" places the corresponding port pin in output mode. •...
Page 191 CHAPTER 9 I/O PORT ● Port operation after a reset • When the CPU is reset, the DDR0 and RDR registers are initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state.
Page 192: Port 1
CHAPTER 9 I/O PORT Port 1 Port 1 is a general-purpose I/O port. It can also be used for resource I/O. The port pins can be switched in units of bits between the I/O port and resource. This section focuses on the general I/O port function. The section provides the configuration of port 1, lists its pins, shows a block diagram of the pins, and describes the corresponding registers.
Page 193 CHAPTER 9 I/O PORT ■ Block Diagram of Port 1 Pins Figure 9.4-1 is a block diagram of port 1 pins. Figure 9.4-1 Block Diagram of Port 1 Pins Resource input Resource output Port data register (PDR) Resource output enable Pull-up resistor About 50k PDR read...
Page 194: Port 1 Registers (Pdr1, Ddr1 And Rdr1)
CHAPTER 9 I/O PORT 9.4.1 Port 1 Registers (PDR1, DDR1 and RDR1) This section describes the port 1 registers. ■ Functions of Port 1 Registers ● Port 1 data register (PDR1) The PDR1 register indicates the state of each pin of port 1. ●...
Page 195: Operation Of Port 1
CHAPTER 9 I/O PORT 9.4.2 Operation of Port 1 This section describes the operation of port 1. ■ Operation of Port 1 ● Port operation in output mode • Setting a bit of the DDR1 register to "1" places the corresponding port pin in output mode. •...
Page 196 CHAPTER 9 I/O PORT ● Port operation after a reset • When the CPU is reset, the DDR1 and RDR registers are initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state.
Page 197: Port 2
CHAPTER 9 I/O PORT Port 2 Port 2 is a general-purpose I/O port. It can also be used for resource I/O. The port pins can be switched in units of bits between the I/O port and the resource. This section focuses on the general I/O port function.
Page 198 CHAPTER 9 I/O PORT ■ Block Diagram of Port 2 Pins Figure 9.5-1 is a block diagram of port 2 pins. Figure 9.5-1 Block Diagram of Port 2 Pins Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write...
Page 199: Port 2 Registers (Pdr2 And Ddr2)
CHAPTER 9 I/O PORT 9.5.1 Port 2 Registers (PDR2 and DDR2) This section describes the port 2 registers. ■ Functions of Port 2 Registers ● Port 2 data register (PDR2) The PDR2 register indicates the state of each pin of port 2. ●...
Page 200: Operation Of Port 2
CHAPTER 9 I/O PORT 9.5.2 Operation of Port 2 This section describes the operation of port 2. ■ Operation of Port 2 ● Port operation in output mode • Setting a bit of the DDR2 register to "1" places the corresponding port pin in output mode. •...
Page 201 CHAPTER 9 I/O PORT ● Port operation after a reset • When the CPU is reset, the DDR2 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), and the pins are placed in a high impedance state. •...
Page 202: Port 3
CHAPTER 9 I/O PORT Port 3 Port 3 is a general-purpose I/O port. It can also be used for resource output. The port pins can be switched in units of bits between the I/O port and resource. This section focuses on the general I/O port function. It provides the configuration of port 3, lists its pins, shows a block diagram of the pins, and describes the corresponding registers.
Page 203 CHAPTER 9 I/O PORT ■ Block Diagram of Port 3 Pins Figure 9.6-1 is a block diagram of port 3 pins. Figure 9.6-1 Block Diagram of Port 3 Pins Resource output Resource output enable Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR)
Page 204: Port 3 Registers (Pdr3 And Ddr3)
CHAPTER 9 I/O PORT 9.6.1 Port 3 Registers (PDR3 and DDR3) This section describes the port 3 registers. ■ Functions of Port 3 Registers ● Port 3 data register (PDR3) The PDR3 register indicates the state of each pin of port 3. ●...
Page 205: Operation Of Port 3
CHAPTER 9 I/O PORT 9.6.2 Operation of Port 3 This section describes the operation of port 3. ■ Operation of Port 3 ● Port operation in output mode • Setting a bit of the DDR3 register to "1" places the corresponding port pin in output mode. •...
Page 206 CHAPTER 9 I/O PORT ● Port operation in stop or time-base timer mode If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state.
Page 207: Port 4
CHAPTER 9 I/O PORT Port 4 Port 4 is a general-purpose I/O port. It can also be used for resource I/O. The port pins can be switched in units of bits between the I/O port and resource. This section focuses on the general I/O port function. It provides the configuration of port 4, lists its pins, shows a block diagram of the pins, and describes the corresponding registers.
Page 208 CHAPTER 9 I/O PORT ■ Block Diagram of Port 4 Pins Figure 9.7-1 is a block diagram of port 4 pins. Figure 9.7-1 Block Diagram of Port 4 Pins Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write...
Page 209: Port 4 Registers (Pdr4 And Ddr4)
CHAPTER 9 I/O PORT 9.7.1 Port 4 Registers (PDR4 and DDR4) This section describes the port 4 registers. ■ Functions of Port 4 Registers ● Port 4 data register (PDR4) The PDR4 register indicates the state of each pin of port 4. ●...
Page 210: Operation Of Port 4
CHAPTER 9 I/O PORT 9.7.2 Operation of Port 4 This section describes the operation of port 4. ■ Operation of Port 4 ● Port operation in output mode • Setting a bit of the DDR4 register to "1" places the corresponding port pin in output mode. •...
Page 211 CHAPTER 9 I/O PORT ● Port operation after a reset • When the CPU is reset, the DDR4 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), and the pins are placed in a high impedance state. •...
Page 212: Port 5
CHAPTER 9 I/O PORT Port 5 Port 5 is a general-purpose I/O port. It can also be used for A/D converter analog input. The port pins can be switched in units of bits between the I/O port and analog input. This section focuses on the general I/O port function.
Page 213 CHAPTER 9 I/O PORT ■ Block Diagram of Port 5 Pins Figure 9.8-1 is a block diagram of port 5 pins. Figure 9.8-1 Block Diagram of Port 5 Pins ADER Analog input Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch...
Page 214: Port 5 Registers (Pdr5, Ddr5 And Ader)
CHAPTER 9 I/O PORT 9.8.1 Port 5 Registers (PDR5, DDR5 and ADER) This section describes the port 5 registers. ■ Functions of Port 5 Registers ● Port 5 data register (PDR5) The PDR5 register indicates the state of each pin of port 5. ●...
Page 215: Operation Of Port 5
CHAPTER 9 I/O PORT 9.8.2 Operation of Port 5 This section describes the operation of port 5. ■ Operation of Port 5 ● Port operation in output mode • Setting a bit of the DDR5 register to "1" places the corresponding port pin in output mode. •...
Page 216 CHAPTER 9 I/O PORT ● Port operation in stop or time-base timer mode If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state.
Page 217: Port 6
CHAPTER 9 I/O PORT Port 6 Port 6 is a general-purpose I/O port. It can also be used for resource input and output. The port pins can be switched in units of bits between the I/O port and resource. This section focuses on the general I/O port function.
Page 218 CHAPTER 9 I/O PORT ■ Block Diagram of Port 6 Pins Figure 9.9-1 is a block diagram of port 6 pins. Figure 9.9-1 Block Diagram of Port 6 Pins Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write...
Page 219: Port 6 Registers (Pdr6 And Ddr6)
CHAPTER 9 I/O PORT 9.9.1 Port 6 Registers (PDR6 and DDR6) This section describes the port 6 registers. ■ Functions of Port 6 Registers ● Port 6 data register (PDR6) The PDR6 register indicates the state of each pin of port 6. ●...
Page 220: Operation Of Port 6
CHAPTER 9 I/O PORT 9.9.2 Operation of Port 6 This section describes the operation of port 6. ■ Operation of Port 6 ● Port operation in output mode • Setting a bit of the DDR6 register to "1" places the corresponding port pin in output mode. •...
Page 221 CHAPTER 9 I/O PORT ● Port operation after a reset • When the CPU is reset, the DDR6 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), and the pins are placed in a high impedance state. •...
Page 222: Sample I/O Port Program
CHAPTER 9 I/O PORT 9.10 Sample I/O Port Program This section provides a sample program using I/O port pins. ■ Sample I/O Port Program ● Processing specifications • Ports 0 and 1 are used to turn on all segments of a seven-segment (eight-segment if the decimal point is included) LED.
Page 223 CHAPTER 9 I/O PORT...
Page 224: Chapter 10 Time-Base Timer
CHAPTER 10 TIME-BASE TIMER This chapter describes the functions and operation of the time-base timer. 10.1 Overview of the Time-base Timer 10.2 Configuration of the Time-base Timer 10.3 Time-base Timer Control Register (TBTC) 10.4 Time-base Timer Interrupts 10.5 Operation of the Time-base Timer 10.6 Usage Notes on the Time-base Timer 10.7 Sample Program for the Time-base Timer Program...
Page 225: Overview Of The Time-Base Timer
CHAPTER 10 TIME-BASE TIMER 10.1 Overview of the Time-base Timer The time-base timer is an 18-bit free-run counter (time-base counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation). The timer has an interval timer function that can select four intervals. The time-base timer also has functions for timer output of the oscillation stabilization time and for supplying the clocks for the watchdog timer.
Page 226 CHAPTER 10 TIME-BASE TIMER ■ Clock Supply Function The clock supply function supplies clocks to the oscillation stabilization time timer and to some peripheral functions. Table 10.1-2 lists the cycle times of clocks supplied from the time-base timer to each peripheral. Table 10.1-2 Clock Cycle Time supplied from the Time-base Timer Clock destination Clock cycle time...
Page 227: Configuration Of The Time-Base Timer
CHAPTER 10 TIME-BASE TIMER 10.2 Configuration of the Time-base Timer The time-base timer consists of the following four blocks: • Time-base timer counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of the Time-base Timer Figure 10.2-1 shows the block diagram of the time-base timer.
Page 228: Time-Base Timer Control Register (Tbtc)
CHAPTER 10 TIME-BASE TIMER 10.3 Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) selects the interval, clears the counter, controls interrupts, and checks the status. ■ Time-base Timer Control Register (TBTC) Figure 10.3-1 Time-base Timer Control Register (TBTC) Address Initial value RESV...
Page 229 CHAPTER 10 TIME-BASE TIMER Table 10.3-1 Function Description of Each Bit in the Time-base Timer Control Register (TBTC) Bit name Function RESV: (Note) bit15 Reserved bit Always write "1" to this bit. • When read, the value is undefined. bit14, Not used •...
Page 230: Time-Base Timer Interrupts
CHAPTER 10 TIME-BASE TIMER 10.4 Time-base Timer Interrupts The time-base timer can generate an interrupt request when the bit specifying the time- base timer counter overflows. ■ Time-base Timer Interrupts The interrupt request flag bit (TBTC: TBOF) is set to "1" when the time-base timer counter counts up with the internal count clock and when the bit for the selected interval timer bit overflows.
Page 231: Operation Of The Time-Base Timer
CHAPTER 10 TIME-BASE TIMER 10.5 Operation of the Time-base Timer The time-base timer provides the interval timer function and the clock supply function that supplies clocks to some peripheral functions. ■ Operation of the Interval Timer Function (Time-base Timer) The interval timer function generates an interrupt request for each interval The setting in Figure 10.5-1 is required to all the timer to operate as an interval timer.
Page 232 CHAPTER 10 TIME-BASE TIMER ■ Oscillation Stabilization Time Timer Function The time-base timer is also used as the oscillation stabilization time timer for oscillation and the PLL clocks. The oscillation stabilization time is set for the interval from the time the counter counts up from "0" (count clear) until the oscillation stabilization time bit overflows.
Page 233: Usage Notes On The Time-Base Timer
CHAPTER 10 TIME-BASE TIMER 10.6 Usage Notes on the Time-base Timer Notes about the effects on peripheral functions of clearing interrupt requests and the time-base timer are given below. ■ Time-base Timer Usage Notes ● Clearing interrupt requests The TBOF bit of the time-base timer control register must be cleared while a time-base timer interrupt is masked by the TBIE bit or the interrupt level mask register (ILM) of the processor status (PS).
Page 234 CHAPTER 10 TIME-BASE TIMER ■ Operation of the Time-base Timer The following operations are shown in Figure 10.6-1: • A power-on reset occurs. • Sleep mode is entered during operation of the interval timer function. • A counter clear request is issued. When stop mode is entered, the time-base timer is cleared and its operation stops.
Page 235: Sample Program For The Time-Base Timer Program
CHAPTER 10 TIME-BASE TIMER 10.7 Sample Program for the Time-base Timer Program This section contains a sample program for the time-base timer. ■ Sample Program for the Time-base Timer ● Processing An interval interrupt of 2 / HCLK (HCLK: oscillation clock) is repeatedly generated. The interval becomes approx.
Page 236 CHAPTER 10 TIME-BASE TIMER ;-------Vector setting-------------------------------------------------------------------------------------------------- VECT CSEG ABS=0FFH 0FF6CH ;Sets vector for interrupt #36 (24H) WARI 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT ENDS START...
Page 237 CHAPTER 10 TIME-BASE TIMER...
Page 238: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 11.1 Overview of the Watchdog Timer 11.2 Configuration of the Watchdog Timer 11.3 Watchdog Timer Control Register (WDTC) 11.4 Operation of the Watchdog Timer 11.5 Usage Notes on the Watchdog Timer 11.6 Sample Program for the Watchdog Timer...
Page 239: Overview Of The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Overview of the Watchdog Timer The watchdog timer is a 2-bit counter that uses the time-base timer supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given time, the CPU is reset.
Page 240: Configuration Of The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of the Watchdog Timer The watchdog timer consists of the following five blocks: • Count clock selector • Watchdog counter (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) ■...
Page 241: Watchdog Timer Control Register (Wdtc)
CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates and clears the watchdog timer, and displays the reset cause. ■ Watchdog Timer Control Register (WDTC) Figure 11.3-1 shows the watchdog timer control register (WDTC). Table 11.3-1 describes the function of each bit of the watchdog timer control register (WDTC).
Page 242 CHAPTER 11 WATCHDOG TIMER Table 11.3-1 Function Description of Each bit of the Watchdog Timer Control Register (WDTC) Bit name Function • Read-only bits for indicating the reset cause. If more than one reset cause occurs, the bit bit7, for each reset cause occurring is set to "1". PONR, WRST, •...
Page 243: Operation Of The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4 Operation of the Watchdog Timer The watchdog timer generates a watchdog reset by an overflow of the watchdog counter. ■ Watchdog Timer Operation Operation of the watchdog timer requires the setting in Figure 11.4-1. Figure 11.4-1 Setting of the Watchdog Timer WDTC TBTC PONR...
Page 244 CHAPTER 11 WATCHDOG TIMER Figure 11.4-2 Clear Timing and Watchdog Timer Intervals [WDG timer block diagram] 2-bit counter Clock Divide-by- Divide-by- Reset Reset signal selector two circuit two circuit circuit Count enabling and clearing Count enable WTE bit output circuit [Minimum interval] When the WTE bit is cleared immediately before the count clock rises: Count start Counter clearing...
Page 245: Usage Notes On The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.5 Usage Notes on the Watchdog Timer Notes on using the watchdog timer are given below. ■ Usage Notes on the Watchdog Timer ● Stopping the watchdog timer Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. The watchdog timer counter is cleared by an external reset or software reset;...
Page 246: Sample Program For The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.6 Sample Program for the Watchdog Timer This section contains a sample program for the watchdog timer. ■ Sample Program for the Watchdog Timer ● Processing • The watchdog timer is cleared every time in the main program loop. •...
Page 247 CHAPTER 11 WATCHDOG TIMER...
Page 248: Chapter 12 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER The chapter describes the functions and operation of the 16-bit reload timer. 12.1 Overview of the 16-bit Reload Timer 12.2 Block Diagram of the 16-bit Reload Timer 12.3 16-bit Reload Timer Pins 12.4 16-bit Reload Timer Registers 12.5 16-Bit Reload Timer Interrupts 12.6 Operation of the 16-bit Reload Timer 12.7 Usage Notes on the 16-bit Reload Timer...
Page 249: Overview Of The 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.1 Overview of the 16-bit Reload Timer The 16-bit reload timer functions in the two modes shown below, either of which can be selected. It is synchronized with three types of internal clocks for counting down in internal clock mode, and it counts down by detecting an optional edge input to the external pin in event counter mode.
Page 250 CHAPTER 12 16-BIT RELOAD TIMER ■ Event Count Mode (External Clock Mode) When selected valid edges (rising, falling and both edges) are input to TIN0 and TIN1 pins, the timer counts down at these edges in channel 0 and 1 respectively. When an external clock with a constant period is used, this timer can also be used as an interval timer.
Page 251 CHAPTER 12 16-BIT RELOAD TIMER ■ 16-bit Reload Timer Interrupts and EI Table 12.1-3 lists 16-bit reload timer interrupts and EI Table 12.1-3 16-bit Reload Timer Interrupts and EI Interrupt control register Vector table address Interrupt Channel number Register name Address Lower Middle...
Page 252: Block Diagram Of The 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.2 Block Diagram of the 16-bit Reload Timer There are two 16-bit reload timers in MB90460/465 series. Each of them consists of the seven blocks as shown in the block diagram below. ■ Block Diagram of the 16-bit Reload Timer Figure 12.2-1 shows the block diagram of the 16-bit reload timer Figure 12.2-1 Block Diagram of the 16-bit Reload Timer MC-16LX bus...
Page 253 CHAPTER 12 16-BIT RELOAD TIMER ● Output control circuit This circuit controls the inversion of the TO pin output by an underflow of the 16-bit timer register and enabling and disabling of TO pin output. ● Operation control circuit This circuit controls starting and stopping of the 16-bit reload timer. ●...
Page 254: 16-Bit Reload Timer Pins
CHAPTER 12 16-BIT RELOAD TIMER 12.3 16-bit Reload Timer Pins This section describes the pins of the 16-bit reload timer and provides a pin block diagram. ■ 16-bit Reload Timer Pins The pins of the 16-bit reload timer are shared with the general-purpose ports. Table 12.3-1 lists the functions of the pins, I/O format, and settings required to use the 16-bit reload timer.
Page 255: 16-Bit Reload Timer Registers
CHAPTER 12 16-BIT RELOAD TIMER 12.4 16-bit Reload Timer Registers The 16-bit reload timer registers are as follows. ■ 16-bit Reload Timer Registers Figure 12.4-1 shows 16-bit reload timer registers. Figure 12.4-1 16-bit Reload Timer Registers Timer Control Status Register (Upper) Address: ch.0 000083 TMCSRH0/ CSL1...
Page 256: Timer Control Status Register, Upper Byte (Tmcsrh0/Tmcsrh1)
CHAPTER 12 16-BIT RELOAD TIMER 12.4.1 Timer Control Status Register, Upper Byte (TMCSRH0/ TMCSRH1) High-order bit11 to bit8 and low-order bit7 of the timer control status registers (TMCSR0/TMCSR1) are used to select the operating mode of the 16-bit reload timer and set the operating conditions.
Page 257 CHAPTER 12 16-BIT RELOAD TIMER Table 12.4-1 Timer Control Status Register (TMCSRH0/TMCSRH1) Bit name Function bit15 • When these bits are read, their values are undefined. Not used • Writing to these bits has no effect on operation. bit12 • Selects the count clock. •...
Page 258: Timer Control Status Register, Lower Byte (Tmcsrl0/Tmcsrl1)
CHAPTER 12 16-BIT RELOAD TIMER 12.4.2 Timer Control Status Register, Lower Byte (TMCSRL0/ TMCSRL1) The lower seven bits of the timer control status registers (TMCSR0/TMCSR1) are used to set operating conditions for the 16-bit reload timer, enable and disable operation, control interrupts, and check the status.
Page 259 CHAPTER 12 16-BIT RELOAD TIMER Table 12.4-2 Timer Control Status Register (TMCSRL0/TMCSRL1) Bit name Function • This bit enables or disables output from the timer output pin. • When this bit is "0", the pin functions as a general-purpose port. When this bit is OUTE: "1", the pin functions as a timer output pin.
Page 260: 16-Bit Timer Register (Tmr0/Tmr1)
CHAPTER 12 16-BIT RELOAD TIMER 12.4.3 16-bit Timer Register (TMR0/TMR1) The 16-bit timer register (TMR0/TMR1) is always able to read the count value from the 16-bit down counter. ■ 16-bit Timer Register (TMR0/TMR1) Figure 12.4-4 shows the 16-bit timer registers (TMR0/TMR1). Figure 12.4-4 16-bit Timer Register (TMR0/TMR1) 16-bit Timer Register (Upper) Address: ch.0 000085...
Page 261: 16-Bit Reload Register (Tmrd0/Tmrd1)
CHAPTER 12 16-BIT RELOAD TIMER 12.4.4 16-bit Reload Register (TMRD0/TMRD1) The 16-bit reload register (TMRD0/TMRD1) sets a reload value in the 16-bit down counter. The value written to this register is loaded into the down counter, and the value is counted down. ■...
Page 262: 16-Bit Reload Timer Interrupts
CHAPTER 12 16-BIT RELOAD TIMER 12.5 16-Bit Reload Timer Interrupts The 16-bit reload timer is enabled to generate an interrupt request in an underflow of the counter. It is also coordinated with the extended intelligent I/O service (EI OS). ■ 16-bit Reload Timer Interrupts Table 12.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer.
Page 263: Operation Of The 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.6 Operation of the 16-bit Reload Timer This section describes the 16-bit reload timer settings and counter operating status. ■ 16-bit Reload Timer Settings ● Internal clock mode setting The setting shown in Figure 12.6-1 is required to operate this timer as an interval timer. Figure 12.6-1 Internal Clock Mode Setting TMCSR0/ UF CNTE TRG...
Page 264 CHAPTER 12 16-BIT RELOAD TIMER ■ Counter Operating State The counter status is determined by the CNTE bit of the timer control status register (TMCSRL0/ TMCSRL1) and the internal WAIT signal. Possible settings include the stop status (STOP state), trigger wait state (WAIT state), and running state (RUN state).
Page 265: Internal Clock Mode (Reload Mode)
CHAPTER 12 16-BIT RELOAD TIMER 12.6.1 Internal Clock Mode (reload mode) Synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter, generating an interrupt request to the CPU for a counter underflow.
Page 266 CHAPTER 12 16-BIT RELOAD TIMER ● External trigger operation When a valid edge (rising, falling and both edges can be selected) is input to the TIN pin, the counter is started. Figure 12.6-5 shows external trigger operation in reload mode. Figure 12.6-5 Counting in Reload Mode (External Trigger Operation) Count clock Reload data...
Page 267: Internal Clock Mode (Single-Shot Mode)
CHAPTER 12 16-BIT RELOAD TIMER 12.6.2 Internal Clock Mode (single-shot mode) Synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter, generating an interrupt request to the CPU for a counter underflow.
Page 268 CHAPTER 12 16-BIT RELOAD TIMER ● External trigger operation When a valid edge (rising, falling, and both edges can be selected) is input to the TIN0/TIN1 pin, the counter is started. Figure 12.6-8 shows external trigger operation in single-shot mode Figure 12.6-8 Specify 2/f or more for the Width of the Trigger Pulse Input to the TIN0/TIN1 Pin.
Page 269: Event Count Mode
CHAPTER 12 16-BIT RELOAD TIMER 12.6.3 Event Count Mode The 16-bit reload timer counts an input edge from the TIN0/TIN1 pin, counts down the 16-bit counter, and generates an interrupt request to the CPU for a counter underflow. It can also output a toggle waveform or rectangular waveform from the TO0/TO1 pin. ■...
Page 270 CHAPTER 12 16-BIT RELOAD TIMER ● Operation in single-shot mode When an underflow of the counter value (from 0000 to FFFF ) occurs, the counter stops in the FFFF state. If the underflow interrupt flag (TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow interrupt enable (TMCSRL0/TMCSRL1:INTE) bit is "1", an interrupt request is generated.
Page 271: Usage Notes On The 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.7 Usage Notes on the 16-bit Reload Timer Notes on using the 16-bit reload timer are given below. ■ Usage Notes on the 16-bit Reload Timer ● Notes on using a program for setting • Write a value to the 16-bit reload register (TMRD0/TMRD1) when counting stops (TMCSRL0/ TMCSRL1:CNTE = 0).
Page 272: Sample Programs For The 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.8 Sample Programs for the 16-bit Reload Timer This section contains sample programs for the 16-bit reload timer in internal clock mode and event count mode. ■ Sample Program in Internal Clock Mode ● Processing •...
Page 273 CHAPTER 12 16-BIT RELOAD TIMER LOOP: A,#00H ;Endless loop A,#01H LOOP ;-------Interrupt program-------------------------------------------------------------------------------------------- WARI: CLRB I:UF ;Clears interrupt request flag User processing RETI ;Returns from interrupt CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------------ VECT CSEG ABS=0FFH 0FF84H ;Sets vector for interrupt #30 (1EH) WARI 0FFDCH ;Sets reset vector...
Page 274 CHAPTER 12 16-BIT RELOAD TIMER ;-------Main program------------------------------------------------------------------------------------------------ CODE CSEG START: ;Assumes that stack pointer (SP) has already been initialized CCR,#0BFH ;Interrupt disable I:ICR09,#00H ;Interrupt level 0 (strongest) I:DDR1,#00H ;Sets P15/INT5/TIN0 pin to input CLRB I:CNTE ;Temporary stopping of counter MOVW I:TMRD,#2710H ;Sets reload value to 10,000 MOVW...
Page 275 CHAPTER 12 16-BIT RELOAD TIMER...
Page 276: Chapter 13 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER This chapter describes the functions and operation of the 16-bit PPG Timer. 13.1 Overview of 16-bit PPG Timer 13.2 Block Diagram of 16-bit PPG Timer 13.3 16-bit PPG Timer Pins 13.4 16-bit PPG Timer Registers 13.5 16-bit PPG Timer Interrupts 13.6 Operation of 16-bit PPG Timer 13.7 Usage Notes on the 16-bit PPG Timer...
Page 277: Overview Of 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER 13.1 Overview of 16-bit PPG Timer The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin. ■ 16-bit PPG Timer (× 3, PPG1 is not present in MB90465 Series) The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin.
Page 278: Block Diagram Of 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER 13.2 Block Diagram of 16-bit PPG Timer This section shows the block diagram of 16-bit PPG timer. ■ Block Diagram of 16-bit PPG Timer Figure 13.2-1 Block Diagram of 16-bit PPG Timer Period Setting Buffer Register 0/1/2 Duty Setting Buffer Register 0/1/2 Prescaler CKS2...
Page 279: 16-Bit Ppg Timer Pins
CHAPTER 13 16-BIT PPG TIMER 13.3 16-bit PPG Timer Pins This section describes the pins of the 16-bit PPG timer and provides a pin block diagram. ■ 16-bit PPG Timer Pins The pins of the 16-bit PPG timer are shared with the general-purpose ports. Table 13.3-1 lists the functions of the pins, I/O format, and settings required to use the 16-bit PPG timer.
Page 280 CHAPTER 13 16-BIT PPG TIMER Figure 13.3-2 Block Diagram of the 16-bit PPG Timer 2 Pin Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1)
Page 281: 16-Bit Ppg Timer Registers
CHAPTER 13 16-BIT PPG TIMER 13.4 16-bit PPG Timer Registers ■ 16-bit PPG Timer Registers Figure 13.4-1 Registers of 16-bit PPG Timer PPG Down Counter Register (Upper) Address: ch.0 000039 PDCR0 to ch.1 000041 DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08 PDCR2 ch.2 000049 Read/write...
Page 282 CHAPTER 13 16-BIT PPG TIMER (Continued) PPG Control Status Register (Upper) Address: ch.0 00003F PCNTH0 to ch.1 000047 CNTE STGR MDSE RTRG CKS1 CKS0 PGMS CKS2 PCNTH2 ch.2 00004F Read/write Initial value PPG Control Status Register (Lower) Address: ch.0 00003E ch.1 000046 PCNTL0 to IREN...
Page 283: Ppg Down Counter Register (Pdcr0 To Pdcr2)
CHAPTER 13 16-BIT PPG TIMER 13.4.1 PPG Down Counter Register (PDCR0 to PDCR2) PPG down counter registers (PDCR0 to PDCR2) are 16-bit registers, which are used to read the count value of the 16-bit PPG down counter. ■ PPG Down Counter Register (PDCR0 to PDCR2) Figure 13.4-2 PPG Down Counter Register (PDCR0 to PDCR2) PPG Down Counter Register (Upper) Address: ch.0 000039...
Page 284: Ppg Period Setting Buffer Register (Pcsr0 To Pcsr2)
CHAPTER 13 16-BIT PPG TIMER 13.4.2 PPG Period Setting Buffer Register (PCSR0 to PCSR2) PPG period setting buffer register is used to set the period of the output pulses generated by PPG. ■ PPG Period Setting Buffer Register (PCSR0 to PCSR2) Figure 13.4-3 PPG Period Setting Buffer Register (PCSR0 to PCSR2) PPG Period Setting Buffer Register (Upper) Address: ch.0 00003B...
Page 285: Ppg Duty Setting Buffer Register (Pdut0 To Pdut2)
CHAPTER 13 16-BIT PPG TIMER 13.4.3 PPG Duty Setting Buffer Register (PDUT0 to PDUT2) PPG duty setting buffer register is used to control the duty ratio of the output pulses generated by PPG. ■ PPG Duty Setting Buffer Register (PDUT0 to PDUT2) Figure 13.4-4 PPG Duty Setting Buffer Register (PDUT0 to PDUT2) PPG Duty Setting Buffer Register (Upper) Address: ch.0 00003D...
Page 286: Ppg Control Status Register (Pcntl0 To Pcntl2, Pcnth0 To Pcnth2)
CHAPTER 13 16-BIT PPG TIMER 13.4.4 PPG Control Status Register (PCNTL0 to PCNTL2, PCNTH0 to PCNTH2) PPG control status register is used to set operating conditions for 16-bit PPG timer enable or disable operation, software trigger, retrigger control interrupt, output polarity and check the status ■...
Page 287 CHAPTER 13 16-BIT PPG TIMER Table 13.4-1 PPG Control Register (PCNTH0 to PCNTH2) Bit Bit name Function • This bit is used to enable the PPG timer operation. CNTE: • Writing “1” will enable the PPG operation and wait for trigger to start PPG bit15 Timer enable operation.
Page 288 CHAPTER 13 16-BIT PPG TIMER ■ PPG Control Status Register, Lower Byte (PCNTL0 to PCNTL2) Figure 13.4-6 PPG Control Register (PCNTL0 to PCNTL2) Address Initial value ch.0: 00003E IREN IRQF IRS1 IRS0 POEN OSEL --000000 ch.1: 000046 ch.2: 00004E OSEL Output inversion bit Normal polarity Inverted polarity...
Page 289 CHAPTER 13 16-BIT PPG TIMER Table 13.4-2 PPG Control Register (PCNTL0 to PCNTL2) Bit name Function • This read value is indeterminate. bit7, Unused bit • Writing to this bit has no effect on the operation. bit6 • This bit enable or disables PPG interrupt request to the CPU. IREN: •...
Page 290: 16-Bit Ppg Timer Interrupts
CHAPTER 13 16-BIT PPG TIMER 13.5 16-bit PPG Timer Interrupts The 16-bit PPG timer is enabled to generate an interrupt request when trigger or counter borrow or PPG rising in normal polarity or PPG falling in inverted polarity depending on PCNTL=IRS1, IRS0 setting.
Page 291 CHAPTER 13 16-BIT PPG TIMER ■ 16-bit PPG Timer Interrupts and EI Table 13.5-2 lists the 16-bit PPG timer interrupts and EI Table 13.5-2 16-bit PPG Timer Interrupts and EI Interrupt control register Vector table address Interrupt Channel number Register name Address Lower Middle...
Page 292: Operation Of 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER 13.6 Operation of 16-bit PPG Timer The 16-bit PPG Timer operate in either PWM mode or single shot mode. And Retriggering can be enabled. ■ PWM Mode (PCNTL: MDSE = 0) For PWM operation, the 16-bit down counter will be loaded with PCSR value, starts counting after a valid trigger is detected.
Page 293 CHAPTER 13 16-BIT PPG TIMER ■ Single-shot Mode (PCNTL: MDSE = 1) For single-shot operation, a single pulse of specified width can be output by a valid trigger. When retriggering is enabled, the counter is reloaded if an edge is detected during operation. a) Retriggering is disabled (PCNTH: RTRG = 0) Figure 13.6-3 Retriggering is disabled in Single-shot Mode Counter value...
Page 294 CHAPTER 13 16-BIT PPG TIMER ■ Gate Trigger (PPG channel 0 only) When gate trigger is used, PPG starts operation when rising edge of gate trigger is detected and stops when falling is detected. In next rising edge, PPG restarts operation again. Figure 13.6-5 Gate Trigger in PWM Mode when retriggering is enable Counter value Time...
Page 295: Usage Notes On The 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER 13.7 Usage Notes on the 16-bit PPG Timer Notes on using the 16-bit PPG timer are given below. ■ Usage Notes on the 16-bit PPG Timer ● Notes on using a program for setting • Write a value to the period setting buffer register (PCSR), duty setting buffer register (PDUT) must be written after writing to PCSR.
Page 296: Sample Programs For The 16-Bit Ppg Timer
CHAPTER 13 16-BIT PPG TIMER 13.8 Sample Programs for the 16-bit PPG Timer This section contains sample programs for the 16-bit PPG timer. ■ Sample Program for the 16-bit PPG Timer ● Processing • An output in 160 kHz with 60% duty is generated with 16-bit PPG timer 0. •...
Page 297 CHAPTER 13 16-BIT PPG TIMER ;-------Interrupt program----------------------------------------------------------------------------- WARI: CLRB I:IRQF ;Clears interrupt request flag User processing RETI ;Returns from interrupt CODE ENDS ;-------Vector setting---------------------------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFC4H ;Sets vector for interrupt #14 (0EH) WARI 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT ENDS...
Page 298: Chapter 14 Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER This chapter describes the functions and operation of the multi-functional timer. 14.1 Overview of Multi-functional Timer 14.2 Block Diagram of Multi-functional Timer 14.3 Multi-functional Timer Pins 14.4 Registers of Multi-functional Timer 14.5 Multi-functional Timer Interrupts 14.6 Operation of Multi-functional Timer 14.7 Usage Notes on the Multi-functional Timer 14.8 Sample Programs for the Multi-functional Timer...
Page 299: Overview Of Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.1 Overview of Multi-functional Timer The multi-functional timer consists of a 16-bit free-run timer, six 16-bit output compare, four 16-bit input capture, 1 channel of 16-bit PPG timer and a waveform generator. By using this waveform generator, 12 independent waveform can be outputted through 16- bit free-run timer.
Page 300 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Input Capture (× 4) Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit free- run timer can be stored in the capture register and an interrupt is generated simultaneously.
Page 301: Block Diagram Of Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.2 Block Diagram of Multi-functional Timer The block diagram of the multi-functional timer will be described in the following sections. ■ Block Diagram of Multi-functional Timer Figure 14.2-1 Block Diagram of Multi-functional Timer Real time I/O P30/RTO0 (U) RTO0 Interrupt #12...
Page 302 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Block Diagram of 16-bit Free-run TImer Figure 14.2-2 Block Diagram of 16-bit Free-run Timer φ CLK1 STOP MODE SCLR CLK2 CLK0 Prescaler STOP UP/UP-DOWN Zero detect 16-bit free-run Zero detect (to output compare) circuit timer To input capture &...
Page 303 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Block Diagram of 16-bit Output Compare Figure 14.2-3 Block Diagram of 16-bit Output Compare Count value from free-run timer BTS0 BUF0 Compare buffer register 0/2/4 Zero detect from free-run timer transfer Compare register 0/2/4 Compare clear match from Selector free-run timer BUF1...
Page 304 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Block Diagram of Waveform Generator Figure 14.2-5 Waveform Generator Block Diagram DCK2 DCK1 DCK0 NRSL DTIF DTIE SIGCR NWS1 NWS0 φ DTTI0 control circuit Divider DTTI0 Noise cancellation PICSH01 PGEN1 PGEN0 DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0 GATE 0/1 GATE (to PPG0)
Page 305: Multi-Functional Timer Pins
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.3 Multi-functional Timer Pins This section describes the pins of the multi-functional timer and provides a pin block diagram. ■ Multi-functional Timer Pins Table 14.3-1 Multi-functional Timer Pins Standby Pin Name Pin function I/O format Pull-up option Setting required for pins control Port 1 input-output/...
Page 306 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Block Diagram of Multi-functional Timer Pins Figure 14.3-1 Block Diagram of P10/INT0/DTTI0, P17/FRCK Resource output Resource input Port data register (PDR) Resource output enable Pull-up resistor About 50k PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write DDR read...
Page 307 CHAPTER 14 MULTI-FUNCTIONAL TIMER Figure 14.3-3 Block Diagram of P30/RTO0 to P35/RTO5 Resource output Resource output enable Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1)
Page 308: Registers Of Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4 Registers of Multi-functional Timer This section describes registers of multi-functional timer. ■ 16-bit Free-run Timer Registers Figure 14.4-1 Registers of 16-bit Free-run Timer Compare Clear Buffer Register / Compare Clear Register (Upper) Address: 00005B CL15 CL14 CL13 CL12...
Page 309 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Output Compare Registers Figure 14.4-2 Registers of Output Compare Output Compare Buffer Register / Output Compare Register (Upper) Address: ch.0 000071 ch.1 000073 ch.2 000075 OCCPB0 to ch.3 000077 OCCPB5/ ch.4 000079 OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 OCCP0 to...
Page 310 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Input Capture Registers Figure 14.4-3 Registers of 16-bit Input Capture Input Capture Data Register (Upper) Address: ch.0 000061 ch.1 000063 ch.2 000065 IPCP0 to CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 ch.3 000067 IPCP3 Read/write Initial value Input Capture Data Register (Lower)
Page 311 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Waveform Generator Registers Figure 14.4-4 Registers of Waveform Generator 16-bit Timer Register (Upper) Address: ch.0 000051 ch.1 000053 TMRR0/TMRR1/ TR15 TR14 TR13 TR12 TR11 TR10 TR09 TR08 TMRR2 ch.2 000055 Read/write Initial value 16-bit Timer Register (Lower) Address: ch.0 000050 TMRR0/TMRR1/ ch.1 000052...
Page 312: Compare Clear Buffer Register (Cpclrb) And Compare Clear Register (Cpclr)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.1 Compare Clear Buffer Register (CPCLRB) and Compare Clear Register (CPCLR) Compare clear buffer register (CPCLRB) is a 16-bit buffer register of compare clear register (CPCLR). Both CPCLRB and CPCLR registers are located in the same address. ■...
Page 313: Timer Data Register (Tcdt)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.2 Timer Data Register (TCDT) The timer data register (TCDT) is used to read the count value of 16-bit free-run timer. ■ Timer Data Register (TCDT) Figure 14.4-7 Timer Data Register Timer Data Register (Upper) Address: 00005D TCDT Read/write Initial value...
Page 314: Timer Control Status Register (Tccsh, Tccsl)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.3 Timer Control Status Register (TCCSH, TCCSL) The timer control status register (TCCS) is a 16-bit register and used to control the operation of 16-bit free-run timer. ■ Timer Control Status Register, Upper Byte (TCCSH) Figure 14.4-8 Timer Control Status Register (TCCSH) Address bit15 Initial value 00005F...
Page 315 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-1 Timer Control Status Register (TCCSH) Bit name Function • This bit is used to select internal or external clock as count clock for 16-bit free-run timer. • Writing “0” selects internal clock. The clock frequency selection bits (CK2 to CK0) should also be set to select the count clock frequency.
Page 316 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ TImer Control Ctatus Register, Lower Byte (TCCSL) Figure 14.4-9 Timer Control Status Register (TCCSL) Address bit7 Initial value 00005E BFE STOP MODE SCLR CLK2 CLK1 CLK0 -0100000 Clock frequency selection bit CLK2 CLK1 CLK0 Count φ...
Page 317 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-2 Timer control status register (TCCSL) Bit name Function • The read value is indeterminate. bit7 Unused bit • Writing to this bit has no effect on the operation. • This bit is used to enable compare clear buffer. •...
Page 318: Output Compare Buffer Registers (Occpb0 To Occpb5) / Output Compare Registers (Occp0 To Occp5)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.4 Output Compare Buffer Registers (OCCPB0 to OCCPB5) / Output Compare Registers (OCCP0 to OCCP5) Output compare buffer register (OCCPB) is a 16-bit buffer register of output compare register (OCCP). Both OCCPB and OCCP registers are located in the same address. ■...
Page 319 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Output Compare Registers (OCCP0 to OCCP5) Figure 14.4-11 Output Compare Registers (OCCP0 to OCCP5) Output Compare Register (Upper) Address: ch.0 000071 ch.1 000073 ch.2 000075 ch.3 000077 OCCP0 to ch.4 000079 OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 OCCP5...
Page 320: Compare Control Registers (Ocs0 To Ocs5)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.5 Compare Control Registers (OCS0 to OCS5) Compare control register is used to control the output level, output enable, output reverse mode, compare operation enable, compare match interrupt enable and compare match interrupt flag for RTO0 to RTO5. ■...
Page 321 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-3 Compare Control Register (OCS1/OCS3/OCS5) bit Bit name Function • The read value is indeterminate. bit15 Unused bit • Writing to this bit has no effect on the operation. • This bit is used to select when data transfer from output compare buffer register (OCCPB1/ OCCPB3/OCCPB5) to output compare register (OCCP1/OCCP3/OCCP5).
Page 322 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Compare Vontrol Tegister, Lower Byte (OCS0/OCS2/OCS4) Figure 14.4-13 Compare Vontrol Register (OCS0/OCS2/OCS4) Address bit7 Initial value ch.0: 00007C IOP1 IOP0 IOE1 IOE0 BUF1 BUF0 CST1 CST0 00001100 ch.2: 00007E ch.4: 000080 CST0 Compare operation enable bit Disable compare operation for compare register 0/2/4 Enable compare operation for compare register 0/2/4 CST1...
Page 323 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-4 Compare Control Register (OCS0/OCS2/OCS4) Bit name Function • This bit is an interrupt flag for when compare register 1/3/5 is matched with the value of 16-bit free-run timer. • “1” is set to this bit when the compare register value matches the 16-bit free-run timer IOP1: value.
Page 324: Input Capture Register (Ipcp0 To Ipcp3)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.6 Input Capture Register (IPCP0 to IPCP3) Input capture registers are used to hold the count value of 16-bit timer when a valid edge of the input waveform is detected. ■ Input Capture Register (IPCP0 to IPCP3) Figure 14.4-14 Input Capture Data Registers (IPCP0 to IPCP3) Input Capture Data Register (Upper) Address: ch.0 000061...
Page 325: Input Capture Control Status Registers (Ics23, Pics01)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.7 Input Capture Control Status Registers (ICS23, PICS01) Input capture control status registers (ICS23, PICS01) are used to control edge selection, interrupt request enable, interrupt request flag and to indicate valid edge detected for input capture 0 to 3. ■...
Page 326 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Input Capture Control Status Register, Lower Byte (ICSL23) Figure 14.4-16 Input Capture Control Status Register (ICSL23) Address bit7 Initial value 00006A ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 00000000 EG21 EG20 Edge selection bit (input capture 2) No edge detection (stop) Rising edge detection Falling edge detection...
Page 327 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-6 Input Capture Control Status Register (ICSL23) Bit name Function • This bit is used as interrupt request flag for input capture 3. • “1” is set to this bit upon detection of a valid edge in an external input pin. ICP3: •...
Page 328 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ PPG Output Control / Input Capture Control Status Register, Upper Byte (PICSH01) Figure 14.4-17 PPG Output Control/Input Capture Control Status Register (PICSH01) Address bit15 Initial value 000069 PGEN5 PGEN4PGEN3 PGEN2 PGEN1 PGEN0 IEI1 IEI0 00000000 IEI0 Valid edge indication bit (input capture 0) Falling edge detected...
Page 329 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-7 PPG output control/input capture control status register (PICSH01) Bit name Function PGEN5 to bit15 PGEN0: • This bit is used to select PPG0 output to RTO0 to RTO5. PPG output bit10 enable bits • This bit is an valid edge indication bit for capture register 1, to indicate a rising or falling edge is detected.
Page 330 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Input Capture Control Status Register, Lower Byte (PICSL01) Figure 14.4-18 Input Capture Control Status Register (PICSL01) Address bit7 Initial value 000068 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000 EG01 EG00 Edge selection bit (input capture 0) No edge detection (stop) Rising edge detection Falling edge detection...
Page 331 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-8 Input Capture Control Status Register (PICSL01) Bit name Function • This bit is used as interrupt request flag for input capture 1. • “1” is set to this bit upon detection of a valid edge of an external input pin. ICP1: •...
Page 332: 16-Bit Timer Register (Tmrr0/Tmrr1/Tmrr2)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.8 16-bit Timer Register (TMRR0/TMRR1/TMRR2) 16-bit timer registers hold the compare value of 16-bit timers. ■ 16-bit Timer Registers (TMRR0/TMRR1/TMRR2) Figure 14.4-19 16-bit Timer Registers (TMRR0/TMRR1/TMRR2) 16-bit Timer Register (Upper) Address: ch.0 000051 TMRR0/TMRR1/ ch.1 000053 TMRR2 TR15 TR14...
Page 333: 16-Bit Timer Control Register (Dtcr0/Dtcr1/Dtcr2)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.9 16-bit Timer Control Register (DTCR0/DTCR1/DTCR2) 16-bit timer control registers (DTCR0/DTCR1/DTCR2) are used to control the operation mode, interrupt request enable, interrupt request flag, GATE signal enable and output level polarity for the waveform generator. ■ 16-bit Timer Control Register (DTCR0/DTCR2) Figure 14.4-20 16-bit Timer Control Register (DTCR1) Address bit 7...
Page 334 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-9 16-bit Timer Control Registers (DTCR0/DTCR2) bit Bit name Function • This bit is used to set the output polarity of U/V/W in dead-time timer mode. DMOD: • By setting this bit, the output polarity of U/V/W is inverted. bit7 Output polarity (Note)
Page 335 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Timer Control Register (DTCR1) Figure 14.4-21 16-bit Timer Control Register (DTCR1) Address bit 15 Initial value DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000 ch.1: 000057 TMD2 TMD1 TMD0 Operation mode bit Waveform generator is stopped. PPG timer 0 output pulse while RT signal is “H”.
Page 336 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-10 16-bit Timer Control Registers (DTCR1) bit Bit name Function • This bit is used to set the output polarity of U/V/W in dead-time timer mode. DMOD: • By setting this bit, the output polarity of U/V/W is inverted. bit15 Output polarity (Note)
Page 337: Waveform Control Register (Sigcr)
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.4.10 Waveform Control Register (SIGCR) Waveform control register is used to control how the operating clock frequencies, noise cancellation function enable, DTTI0 input enable and DTTI0 interrupt. ■ Waveform Control Register (SIGCR) Figure 14.4-22 Waveform Control Register (SIGCR) Address bit15 Initial value 000059...
Page 338 CHAPTER 14 MULTI-FUNCTIONAL TIMER Table 14.4-11 Waveform Control Register (SIGCR) Bit name Function DTIE: • This bit is used to enable the DTTI0 pin to control the output level of RTO0 to RTO5 bit15 DTTI0 input pin. enable bit • This bit is an interrupt flag for DTTI0. •...
Page 339: Multi-Functional Timer Interrupts
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.5 Multi-functional Timer Interrupts The multi-functional timer is enabled to generate interrupts in 16-bit free-run timer, 16- bit output compare, 16-bit input capture and waveform generator. ■ 16-bit Free-run Timer Interrupts Table 14.5-1 lists the interrupt control bits and interrupt causes of the 16-bit free-run timer. Table 14.5-1 Interrupt Control Bits and Interrupt Causes of the 16-bit Free-run Timer 16-bit free-run timer Compare Clear...
Page 340 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Output Compare Interrupts Table 14.5-3 lists the interrupt control bits and interrupt causes of the 16-bit output compare. Table 14.5-3 Interrupt Control Bits and Interrupt Causes of the 16-bit Output Compare 0 to 5 16-bit output compare 0/1 16-bit output compare 2/3 16-bit output compare 4/5...
Page 341 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Input Capture Interrupts Table 14.5-5 lists the interrupt control bits and interrupt causes of the 16-bit input capture. Table 14.5-5 Interrupt Control Bits and Interrupt Causes of the 16-bit Input Capture 0 to 3 16-bit input capture 0/1 16-bit input capture 2/3 Interrupt request flag bit...
Page 342 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Waveform Generator Interrupts and EI Table 14.5-8 lists the waveform generator interrupts and EI Table 14.5-8 Waveform Generator Interrupts and EI Interrupt control register Vector table address Channel Interrupt number Register Address Lower Middle Upper name 16-bit timer 0/1/2 #29 (1D...
Page 343: Operation Of Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6 Operation of Multi-functional Timer This section describes the operation of the multi-functional timer. ■ Operation of Multi-functional Timer ● 16-bit free-run timer The 16-bit free-run timer starts counting up from value set in timer data register (TCDT) after a reset has been completed.
Page 344: Operation Of 16-Bit Free-Run Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.1 Operation of 16-bit free-run timer The 16-bit free-run timer starts counting up from counter value specified in timer data register (TCDT) after a reset has been completed. The counter value is used as the reference time for 16-bit output compare and 16-bit input capture. ■...
Page 345 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Timer Mode Two count modes can be selected in 16-bit free-run timer • up-count mode (TCCSL:MODE=0) • up-down count mode (TCCSL:MODE=1) In up-count mode, counter starts counting from pre-set timer data register (TCDT), counts up until counter value matches value of compare clear register (CPCLR), then counter is cleared to "0000 "...
Page 346 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Compare Clear Buffer There is a selected buffer function on compare clear register (CPCLR). In buffer enable (TCCSL:BFE=1), data written in compare clear buffer register (CPCLRB) will transfer to CPCLR at zero detection of the 16- bit free-run timer.
Page 347 CHAPTER 14 MULTI-FUNCTIONAL TIMER Figure 14.6-5 Operation in Up-down Count Mode with Compare Clear Buffer enabled (TCCSL:BFE=1) Counter value Compare clear match FFFF BFFF 7FFF 3FFF Time 0000 Timer starts Zero detect Reset Compare clear buffer register BFFF 7FFF FFFF value Compare clear BFFF...
Page 348 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Timer Interrupts Two interrupts can be generated from 16-bit free-run timer: • Compare clear interrupt • Zero detect interrupt Compare clear interrupt is generated when the timer value matches compare clear register (CPCLR). Zero detect interrupt is generated when the timer value reaches "0000 ".
Page 349 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Interrupt Mask Function The number of times of Interrupt source can be masked by setting TCCSH:MSI2 to MSI0. MSI2 to MSI0 configure a 3-bit reload down counter, which reloads when its count value reaches "000 ".
Page 350 CHAPTER 14 MULTI-FUNCTIONAL TIMER Figure 14.6-9 Zero Detect Interrupt masked in Up-down Count Mode Counter value Compare clear match FFFF BFFF 7FFF 3FFF Time 0000 Timer starts Zero detect Reset Compare clear interrupt Software clear TCCSH:MSI2:0=000 Zero detect TCCSH:MSI2:0=001 interrupt TCCSH:MSI2:0=010 * Both zero detect interrupt and compare clear interrupt are software cleared ■...
Page 351: Operation Of 16-Bit Output Compare
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.2 Operation of 16-bit Output Compare The output compare unit is used to compare the value set in the specified compare register with the value of the 16-bit free-run timer. If a match is detected, the interrupt flag is set and the output level is inverted.
Page 352 CHAPTER 14 MULTI-FUNCTIONAL TIMER Figure 14.6-12 Sample Output Waveform when Compare Registers 0 and 1 are used individually when the Initial Output Value is "0" (Free-run Timer in Up-down Count Mode) Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare register 0 BFFF value...
Page 353 CHAPTER 14 MULTI-FUNCTIONAL TIMER Figure 14.6-14 Sample Output Waveform when Compare Register 0 and 1 are used in a Pair when the Initial Output Value is "0" (Free-run Timer in Up-down Count Mode) Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare register 0...
Page 354 CHAPTER 14 MULTI-FUNCTIONAL TIMER ● Output level when compare buffer is selected at compare clear match Figure 14.6-16 Sample Output Waveform when Compare Buffer is enable (Free-run Timer in Up-down Count Mode) Counter value FFFF BFFF 7FFF 3FFF 0000 Time Zero detection Timer starts Compare clear match...
Page 355 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Output Compare Timing When the free-run timer matches the value set in the compare register, the output compare unit generates a compare match signal to invert the output and generate an interrupt. When a compare match occurs, the output is inverted in synchronization with the count timing of the counter.
Page 356: Operation Of 16-Bit Input Capture
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.3 Operation of 16-bit Input Capture The input capture unit is used to detect a specified valid edge. If a valid edge is detected, the interrupt flag is set and the value of 16-bit free-run timer is loaded into the capture register.
Page 357 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ 16-bit Input Capture Input Timing Figure 14.6-21 16-bit Input Capture Timing for Input Signals φ Machine clock Counter value Input capture Valid edge input Capture signal Capture register Interrupt...
Page 358: Operation Of Waveform Generator
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.4 Operation of Waveform Generator Waveform generator can produce various waveform such as dead-time, by using the real-time outputs (RT0 to RT5), 16-bit PPG timer 0 and 16-bit timers 0/1/2. ■ Output Condition of RTO0 to RTO5 and GATE Table 14.6-1 Output Condition of RTO0 to RTO5, GATE and Register Bit Setting TMD2 TMD1 TMD0 GTENx PGENx RTOx...
Page 359 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ PPG0 Output Control PPG0 output to RTO0 to RTO5 can be enabled by PGEN0 to PGEN5 in PPG output control/input capture control status register (PICSH01). ■ Gate Triggered PPG0 Output In waveform generator, a GATE signal can be generated by using real-time outputs RT0 to RT5 or cope with 16-bit timers 0/1/2 to trigger PPG0 counting.
Page 360 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Generating GATE Signal from Rising Edge of Each RTx until 16-bit Timer 0/1/2 Underflow when GTENx is active (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=010 Figure 14.6-23 Generating GATE Signal from Rising Edge of RTx until 16-bit Timer Underflow 16-bit free-run timer FFFF BFFF...
Page 361 CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.4.1 Operation in Timer Mode With RT0 to RT5 rising edge, the 16-bit timer is reloaded, starts down-counting and the PPG timer 0 keeps outputting to RTO0 to RTO5 until the 16-bit timer is underflow. ■ PPG0 Output Pulse from Tising Rdge of RT to 16-bit Timer Underflow (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=010 Figure 14.6-24 Waveform generated when TMD2 to TMD0=010 Setting up registers:...
Page 362 CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.4.2 Operation in Dead-time Timer Mode The dead-time generator will input the real-time output (RT1/RT3/RT5), select PPG timer 0 pulse output, and output non-overlap signals (inverted signals) to external pins (RTO0 to RTO5). ■ Making Non-overlap Signals by using RT1/RT3/RT5 in Normal Polarity (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100 When selecting non-overlap signal for an active level "0"...
Page 363 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Making Non-overlap Signals by using RT1/RT3/RT5 in Inverted Polarity (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100 When selecting non-overlap signal for a active level "1" (inverted polarity) in DTCR0/DTCR1/ DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2 register (16-bit timer register) is applied.
Page 364 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Making Non-overlap Signals by using PPG in Normal Polarity (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=111 When selecting non-overlap signal for a active level "0" (normal polarity) in DTCR0/DTCR1/ DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2 register (16-bit timer register) is applied.
Page 365 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Making Non-overlap Signals by using PPG in Inverted Polarity (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=111 When selecting non-overlap signal for an active level "1" (inverted polarity) in DTCR0/DTCR1/ DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2 register (16-bit timer register) is applied.
Page 366 CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.6.4.3 Operation of DTTI0 Pin Control By setting "1" to waveform control register, SIGCR: bit7 (DTIE), the output of RTO0 to RTO5 can be controlled by the DTTI0 pin. When "L" level in DTTI0 is detected, the output of RTO0 to RTO5 will be fixed to an inactive level until the interrupt flag, SIGCR: bit6 (DTIF) is cleared.
Page 367 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ DTTI0 Pin Noise Cancellation Function By setting bit5 (NRSL) of the waveform control register (SIGCR) to "1", the noise cancellation function for DTTI0 pin input is enabled. When noise cancellation function is enabled, the time for fixing an output pin RTO0 to RTO5 to inactive level is delayed for about 4, 8, 16 or 32 machine cycles (selected by SIGCR:NWS1,NWS0).
Page 368: Usage Notes On The Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.7 Usage Notes on the Multi-functional Timer Notes on using the multi-functional timer are given below. ■ Usage Notes on the 16-bit Free-run Timer ● Notes about using a program for setting • After reset, the timer value is "0000 ", zero detect interrupt flag will be set to "1"...
Page 369 CHAPTER 14 MULTI-FUNCTIONAL TIMER ■ Usage Notes on the 16-bit Input Capture ● Notes about interrupts • When the ICP bit of the input capture control status register (PICSL01/ICSL23) is set to "1" and an interrupt request is enabled (PICSL01/ICSL23:ICE=1), control cannot be returned from interrupt processing.
Page 370: Sample Programs For The Multi-Functional Timer
CHAPTER 14 MULTI-FUNCTIONAL TIMER 14.8 Sample Programs for the Multi-functional Timer This section contains sample programs for the multi-functional timer. ■ Sample Program for 16-bit Free-run Timer ● Processing • A 4 ms compare clear interrupt is generated with 16-bit free-run timer 0. •...
Page 371 CHAPTER 14 MULTI-FUNCTIONAL TIMER WARI: CLRB I:ICLR ;Clears interrupt request flag User processing RETI ;Returns from interrupt CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------------ VECT CSEG ABS=0FFH 0FF74H ;Sets vector for interrupt #34 (22H) WARI 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT ENDS START...
Page 372 CHAPTER 14 MULTI-FUNCTIONAL TIMER CCR,#0BFH ;Interrupt disable I:ICR00,#00H ;Interrupt level 0 (strongest) MOVW I:TCCS,#0000H ;Enables 16-bit free-run timer ;Sets up-count mode MOVW I:OCCP0,#0BFFFH ;Set output compare register 0 MOVW I:OCCP1,#07FFFH ;Set output compare register 1 MOVW I:OCS01,#0C1FH ;Enables output compare output ;Enables compare match interrupt 0 ;Clears interrupt flag and enable output compare ILM,#07H...
Page 373 CHAPTER 14 MULTI-FUNCTIONAL TIMER...
Page 374: Chapter 15 Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR This chapter describes the specification and operation of the Multi-pulse Generator. 15.1 Overview of Multi-pulse Generator 15.2 Block Diagram of Multi-pulse Generator 15.3 Multi-pulse Generator Pins 15.4 Registers of Multi-pulse Generator 15.5 Multi-pulse Generator Interrupts 15.6 Operation of Multi-pulse Generator 15.7 Usage Notes on the Multi-pulse Generator 15.8 Sample Programs for the Multi-pulse Generator...
Page 375: Overview Of Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.1 Overview of Multi-pulse Generator The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse Generator output (OPT5 to OPT0) according to the input signal of Multi-pulse Generator (SNI2 to SNI0).
Page 376 CHAPTER 15 MULTI-PULSE GENERATOR • In the waveform sequencer, there is a 16-bit timer that can be used to measure the speed of the motor and disable the OPT output in case of position detect missing. • Forced stop control using DTTI1 pin input External pin control can be performed through clockless DTTI1 pin input even when oscillation is stopped.
Page 377 CHAPTER 15 MULTI-PULSE GENERATOR Figure 15.1-2 PPG Falling Edge Synchronization Asynchronous State Change WTS1,WTS0 = 00 Glitch Synchronous State Change WTS1,WTS0 = 10 OP5’ OP4’ Sequencer changes state due to, e.g. the reload timer 0 underflow. Note: Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from rising- edge synchronization to falling-edge synchronization or vice versa) is inhibited, no synchronization mode must be the transit for such switch.
Page 378: Block Diagram Of Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.2 Block Diagram of Multi-pulse Generator Figure 15.2-1 shows the block diagram of the Multi-pulse Generator and Figure 15.2-2 shows the block diagram of the Waveform Sequencer. ■ Block Diagram of Multi-pulse Generator Figure 15.2-1 Block Diagram of Multi-pulse Generator OPT5 P05/OPT5 P12/INT2/DTTI1...
Page 379 CHAPTER 15 MULTI-PULSE GENERATOR ■ Block Diagram of Waveform Sequencer Figure 15.2-2 Block Diagram of Waveform Sequencer Interrupt WRITE TIMING INTERRUPT # 26 Interrupt #22 POSITION DETECTION INTERRUPT OPCR Register PDIRT DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 From PPG1 SYN Circuit WTS1...
Page 380 CHAPTER 15 MULTI-PULSE GENERATOR ● 16-bit Timer The 16-bit timer is used to act as an interval timer for motor speed checking and abnormal detection timer when control DC sensorless motor. The detail is shown in Figure 15.2-3. ● Comparison Circuit The Comparison Circuit is used to compare the RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0) with the CPD2 to CPD0 bits of the Input Control Register (IPCR: CPD2 to CPD0) for motor direction change.
Page 381 CHAPTER 15 MULTI-PULSE GENERATOR ● Output Control Register (OPCR) The Output Control Register (OPCR) is a register which enables the write timing interrupt and flag, position detect interrupt and flag, sets the data transfer method, and sets the control of the OPT5 to OPT0 and DTTI1 pins.
Page 382 CHAPTER 15 MULTI-PULSE GENERATOR ■ Block Diagram of 16-bit Timer Figure 15.2-3 Block Diagram of 16-bit Timer Compare Clear Interrupt (CCIRT) φ TCSR TCLR ICLR ICRE MODE TMEN CLK2 CLK1 CLK0 Prescaler Clock 16-bit up counter Latch 16-bit compare clear Compare circuit register WTIN1...
Page 383 CHAPTER 15 MULTI-PULSE GENERATOR ● Timer Buffer Register (TMBR) The Timer Buffer Register (TMBR) is used store the value of the 16-bit Up Counter when a write timing interrupt or position detect interrupt occurs. ● Timer Control Register (TCSR) The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit timer such as the clock frequency, enable/disable the interrupt.
Page 384 CHAPTER 15 MULTI-PULSE GENERATOR ● Selector 0 The Selector 0 is used to select from either WTIN1 of the Position Detect Circuit or external pin (P15/ INT5/TIN0) to enable the count of the 16-bit Reload Timer 0. ● Selector 1 The Selector 1 is used to select from among Write OPDBR or TOUT of 16-bit Reload timer 0 or WTIN1 of Position Detect Circuit to generate the Write Timing signal (WTO).
Page 385 CHAPTER 15 MULTI-PULSE GENERATOR ■ Block Diagram of Position Detection Circuit Figure 15.2-5 Block Diagram of Position Detection Circuit RDA2 RDA1 RDA0 COMPARISON CIRCUIT NOISE EDGE FILTER DETECTION SNI0 CIRCUIT CIRCUIT 0 SEE0 CPE1 CPE0 EDGE NOISE WTIN1 SELECTOR DETECTION SNI1 FILTER CIRCUIT 1...
Page 386: Multi-Pulse Generator Pins
CHAPTER 15 MULTI-PULSE GENERATOR 15.3 Multi-pulse Generator Pins This section describes the pins of the Multi-pulse Generator and provides a pin block diagram. ■ Pins of Multi-pulse Generator Multi-pulse Generator uses P00/OPT0 to P05/OPT5, P43/SNI0 to P45/SNI2, P12/INT2/DTTI1 and P15/ INT5/TIN0.
Page 387 CHAPTER 15 MULTI-PULSE GENERATOR ■ Block Diagram of Multi-pulse Generator Pins Figure 15.3-1 Block Diagram of P00/OPT0 to P05/OPT5 Pins Resource output Direct resource input Port data register (PDR) Resource output enable Pull-up resistor About 50kΩ PDR read Output latch PDR write Port data direction register (DDR) Direction latch...
Page 388: Registers Of Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.4 Registers of Multi-pulse Generator This section describes the registers of the Multi-pulse Generator. ■ Registers of Multi-pulse Generator Figure 15.4-1 Registers of Multi-pulse Generator Output Control Register (Upper) OPCUR DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE Address: 00008B Read/Write...
Page 389 CHAPTER 15 MULTI-PULSE GENERATOR (Continued) Output Data Buffer Registers (Upper) Addresses: OPDBRB to 003FF7 to E1 OPDBR0 BNKF RDA2 RDA1 RDA0 OP51 OP50 OP41 OP40 (Odd Addresses) Read/Write Initial Value Output Data Buffer Registers (Lower) Addresses: OPDBRB to 003FF6 to E0 OPDBR0 OP31 OP30 OP21 OP20...
Page 390 CHAPTER 15 MULTI-PULSE GENERATOR (Continued) Compare Clear Register (Upper) CPCR Address: 003FFB CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08 Read/Write Initial Value Compare Clear Register (Lower) CPCR Address: 003FFA CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 Read/Write Initial Value Timer Buffer Register (Upper) TMBR Address: 003FFD...
Page 391: Output Control Register (Opcr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.1 Output Control Register (OPCR) The Output Control Register (OPCR) is a register which enables the write timing interrupt and flag, position detect interrupt and flag, sets the data transfer method, and sets the control of the OPT5 to OPT0 and DTTI1 pins. ■...
Page 392 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-1 Output Control Upper Register (OPCUR) Bits Bit name Function • DTTI1 pin input enable bit. DTIE: • This bit is used to enable the DTTI1 pin to control the output levels of the OPT5 to bit15 DTTI1 control OPT0 pins.
Page 393 CHAPTER 15 MULTI-PULSE GENERATOR ■ Output Control Lower Register (OPCLR) Figure 15.4-3 Output Control Lower Register (OPCLR) Address Initial value PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 00000000 00008A OPE0 OPT0 output enable bit Disable OPT0 pin output. (Initial value) Enable OPT0 pin output.
Page 394 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-2 Output Control Lower Register (OPCLR) Bits Bit name Function • Position detection interrupt request flag. • It is an interrupt request flag for the position detection. When CMPE is set to "0" and the PDIF: SNI2 to SNI0 bits are compared and matched with the RDA2 to RDA0 bit, or when CMPE Position detect...
Page 395: Output Data Register (Opdr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.2 Output Data Register (OPDR) This is a register which stores the output data to the OPT5 to OPT0 pins. ■ Output Data Upper Register (OPDR) Figure 15.4-4 Output Data Upper Register (OPDR) Address bit 15 Initial value 003FF9 BNKF...
Page 396 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-3 Output Data Upper Register (OPDR) Bits Bit name Function BNKF, RDA2 to bit15 • These bits indicate the addresses of the OPDBR registers and decide which RDA0: OPDBR register Output Data Buffer Register value is loaded into the OPDR register. bit12 selection bits OP51, OP50:...
Page 397 CHAPTER 15 MULTI-PULSE GENERATOR ■ Output Data Lower Register (OPDR) Figure 15.4-5 Output Data Lower Register (OPDR) Address bit 7 Initial value 003FF8 OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 XXXXXXXX OP01 OP00 OPT0 output waveform selection bits Pin OPT0 outputs “L” level. Pin OPT0 outputs the output of the PPG timer.
Page 398 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-4 Output Data Lower Register (OPDR) Bits Bit name Function OP31, OP30: bit7, OPT3 output • These bits are used to select the kind of the output waveform to the OPT3 pin. bit6 waveform selection bits OP21, OP20: bit5, OPT2 output...
Page 399: Output Data Buffer Register (Opdbr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.3 Output Data Buffer Register (OPDBR) The Output Data Buffer Register is composed of twelve registers (OPDBRB to OPDBR0). The value of the OPDBRx register specified by the BNKF, RDA2 to RDA0 bits is loaded into the OPDR register at the rising edge of the write signal generated by the Data Write Control Unit.
Page 400 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-5 Output Data Buffer Upper Register (OPDBR) Bits Bit name Function BNKF, RDA2 to • These bits indicate the addresses of the OPDBR registers and decide which bit15 RDA0: Output Data Buffer Register value is loaded into the OPDR register after it is OPDBR register bit12 loaded into the OPDR register.
Page 401 CHAPTER 15 MULTI-PULSE GENERATOR ■ Output Data Buffer Lower Register (OPDBR) Figure 15.4-7 Output Data Buffer Lower Register (OPDBR) Address bit 7 Initial value 003FF6 OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 00000000 to 003FE0 OP01 OP00 OPT0 output waveform selection bits Setting for OPT0 pin to output “L”...
Page 402 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-6 Output Data Buffer Lower Register (OPDBR) Bits Bit name Function OP31, OP30: • These bits are used to select the kind of the output waveform to the OPT3 pin after it bit7, OPT3 output bit6 waveform is loaded into the OPDR register.
Page 403: Input Control Register (Ipcr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.4 Input Control Register (IPCR) The Input Control Register (IPCR) is a register which sets the control of the position detection inputs. ■ Input Control Upper Register (IPCUR) Figure 15.4-8 Input Control Upper Register (IPCUR) Address bit 15 Initial value 00008D WTS1...
Page 404 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-7 Input Control Upper Register (IPCUR) Bits Bit name Function WTS1, WTS0: • These bits are used to select the synchronization edge of the next coming of PPG bit15, PPG edge bit14 synchronization signal with the write timing. selection bits •...
Page 405 CHAPTER 15 MULTI-PULSE GENERATOR ■ Input Control Lower Register (IPCLR) Figure 15.4-9 Input Control Lower Register (IPCLR) Address bit 7 Initial value 00008C CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0 00000000 SEE0 SNI0 enable bit Disable SNI0 edge detection. (Initial value) Enable SNI0 edge detection.
Page 406 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-8 Input Control Lower Register (IPCLR) Bits Bit name Function • Input polarity selection bits. CPE1, CPE0: bit7, • These bits are used to select the polarity of the input edge for the position detection, Input polarity bit6 selection bits...
Page 407: Compare Clear Register (Cpcr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.5 Compare Clear Register (CPCR) The Compare Clear Register (CPCR) is 16-bit register. When this register is matched with the count value of 16-bit timer, the 16-bit timer is reset to "0000 ". ■ Compare Clear Register (CPCR) Compare Clear Register is a 16-bit register and is used to compare the count value of the 16-bit timer.
Page 408: Timer Buffer Register (Tmbr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.6 Timer Buffer Register (TMBR) The Timer Buffer Register (TMBR) is used to read the count value of 16-bit timer. ■ Timer Buffer Register (TMBR) The timer buffer register is used to store the count value of the 16-bit timer at the moment when a write timing or position detection trigger is generated, and the counter is then cleared to "0000 ".
Page 409: Timer Control Status Register (Tcsr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.7 Timer Control Status Register (TCSR) The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit timer. ■ Timer Control Status Register (TCSR) Figure 15.4-12 Timer Control Status Register (TCSR) Address bit Initial value TCLR 00008E...
Page 410 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-9 Timer Control Status Register (TCSR) Bit name Function • The read value is always “0”. TCLR: • Writing “1” to this bit initialize the counter to “0000 ”. bit7 Timer clear bit • Writing “0” has no effect. •...
Page 411: Noise Cancellation Control Register (Nccr)
CHAPTER 15 MULTI-PULSE GENERATOR 15.4.8 Noise Cancellation Control Register (NCCR) The Noise Cancellation Control Register (NCCR) is used to control the noise pulse width to be cancelled for DTTI1 and SNIx pins. ■ Noise Cancellation Control Register (NCCR) Figure 15.4-13 Noise Cancellation Control Register (NCCR) Address bit 7 Initial value 00008F...
Page 412 CHAPTER 15 MULTI-PULSE GENERATOR Table 15.4-10 Noise Cancellation Control Register (NCCR) Bits Bit name Function S21,S20: bit7, • These bits are used to specify the noise pulse width to be removed for SNI2 pin. Noise width bit6 selection bits S11,S10: bit5, •...
Page 413: Multi-Pulse Generator Interrupts
CHAPTER 15 MULTI-PULSE GENERATOR 15.5 Multi-pulse Generator Interrupts The Multi-pulse Generator can generate an interrupt request when in the following causes: • Write timing output is generated by the Data Write Control Unit • Any valid position detection input is detected •...
Page 414 CHAPTER 15 MULTI-PULSE GENERATOR ● Position Detect Timing Interrupt If the PDIE bit of the Output Control Register (OPCR: PDIE) is set to "1", this Position Detect Interrupt is generated when the write timing is output by Position Detect Circuit to make data transfer from one of 12 Output Data Buffer Registers (OPDBRB to OPDBR0) to the Output Data Register (OPDR).
Page 415 CHAPTER 15 MULTI-PULSE GENERATOR ■ Multi-pulse Generator Interrupts and EI Table 15.5-1 Multi-pulse Generator Interrupts and EI Interrupt control register Vector table address Interrupt Interrupt cause number Register Address Lower Upper Bank name × #22 (16 0000B5 FFFFAC FFFFAD FFFFAE DTTI1 ICR05 Write Timing or...
Page 416: Operation Of Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.6 Operation of Multi-pulse Generator The operation of the Multi-pulse Generator will be described in the following sections. According to the setting of (OPx1/OPx0) bits in the Output Data Register (OPDR), the OPTx pin outputs the corresponding kind of waveforms ("H" or "L" or PPG output). See Table 15.6-1.
Page 417 CHAPTER 15 MULTI-PULSE GENERATOR ■ Output Data Register (OPDR) The content of the Output Data Register (OPDR) is received from the Output Data Buffer Register (OPDBRB to OPDBR0) according to the write timing signal (WTO) generated by the Data Write Control Unit, and the OPTx output waveform is updated.
Page 418: Operation Of Position Detection
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.1 Operation of Position Detection This section describes the operation of the Position Detection Circuit. When the effective position is detected, a Data Write Timing Output (WTIN1) will be generated to the Data Write Control Unit and a Position Detect Interrupt is generated if the OPCR: PDIE is set to "1".
Page 419 CHAPTER 15 MULTI-PULSE GENERATOR ■ Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = 1) Figure 15.6-4 Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = 1) CMPE CPE1, CPE0 RDA2 to RDA0 (OPDR) SNI2 SNI1 SNI0 WTIN1 COMPARISON COMPARISON COMPARISON...
Page 420: Operation Of Data Write Control Unit
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.2 Operation of Data Write Control Unit The Data Write Control Unit is used to generate the write timing output (WTO) for transferring data from the Output Data Buffer Register (OPDBR) to Output Data Register (OPDR). ■...
Page 421 CHAPTER 15 MULTI-PULSE GENERATOR ■ OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000 Figure 15.6-6 OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000 OPS2 to OPS0 RDA2 to RDA0 (OPDR) OPDBR0W OPDBR1W OPDBR0[0] OPDBR1[0] OP00 ■ Signal Flow Diagram for Reload Timer 0 Underflow by Setting OPS2 to OPS0 = 001 Figure 15.6-7 Signal Flow Diagram for Reload Timer 0 Underflow (OPS2 to OPS0 = 001 TIN0O TIN0...
Page 422 CHAPTER 15 MULTI-PULSE GENERATOR ■ Signal Flow Diagram for Position Detection by Setting OPS2 to OPS0 = 010 or 110 Figure 15.6-8 Signal Flow Diagram for Position Detection (OPS2 to OPS0 = 010 or 110 TIN0 TIN0O TIN0 16-BIT RELOAD TIMER 0 TOUT WTIN0 WRITE...
Page 423 CHAPTER 15 MULTI-PULSE GENERATOR ■ Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to OPS0 = 100 or 101 Figure 15.6-10 Signal Flow Diagram for Reload Timer 0 or Position Detect (OPS2 to OPS0 = 100 or 101 TIN0 TIN0O...
Page 424: Operation Of Output Data Buffer Register
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.3 Operation of Output Data Buffer Register The Output Data Buffer Register (OPDBR) is composed of twelve registers. By loading different OPDBR register into the Output Data Register (OPDR), various kind of waveform is output at the Multi-pulse Generator Output (OPT5 to OPT0). ■...
Page 425 CHAPTER 15 MULTI-PULSE GENERATOR Setting the Output Data Buffer Register 0 (OPDBR0) (No. 0) as shown in Table 15.6-3 initializes the value of the Output Data Register (OPDR). The following sequence begins to operate according to the write timing generated: No.
Page 426: Operation Of Data Transfer Of Output Data Register
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4 Operation of Data Transfer of Output Data Register Eight methods can be used to transfer data from the Output Data Buffer Register (OPDBR) to the Output Data Register (OPDR) automatically, which are described in the following paragraphs.
Page 427 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.1 When OPDBR0 Write The timing change of the output pin OPTx, which is triggered by the OPDBR0 write, is shown in Figure 15.6-13. Note: Word access to Output Data Buffer Register 0 must be used in this operation, byte access to either lower register or upper register does not start any transfer operation.
Page 428 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.2 When 16-bit Reload Timer Underflow The timing change of the output pin OPTx, which is triggered by the 16-bit reload timer 0 underflow, is shown in Figure 15.6-14 and Figure 15.6-15. ■ Timing Generated by Reload Timer Underflow Figure 15.6-14 Timing Generated by Reload Timer Underflow No.
Page 429 CHAPTER 15 MULTI-PULSE GENERATOR The data transfer from the Output Data Buffer Register (OPDBR) specified by the BNKF, RDA2 to RDA0 bits to the Output Data Register (OPDR) is updated automatically whenever a 16-bit reload timer 0 underflow is generated as shown in Figure 15.6-15. In order to use this method, the reload timer should be used in "Reload Mode".
Page 430 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.3 When Position Detection The output timing change, which is triggered by the input pin SNIx for the position detection, is shown in Figure 15.6-16 and Figure 15.6-17. ■ Timing Generated by Position Detection Figure 15.6-16 Timing Generated by Position Detection No.
Page 431 CHAPTER 15 MULTI-PULSE GENERATOR The comparisons between pin SNI2 and RDA2 bit, pin SNI1 and RDA1 bit, pin SNI0 and RDA0 bit are done for each position detection. The OPTx output waveform is updated according to the effective edge input to pin SNIx as shown in Figure 15.6-17.
Page 432 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.4 When Position Detection and Timer Underflow The output timing change of the operation of the Position Detection and Reload Timer underflow is shown in Figure 15.6-18 and Figure 15.6-19. ■ Timing Generated by Position Detection and Timer Underflow Figure 15.6-18 Timing Generated by Position Detection and Timer Underflow No.
Page 433 CHAPTER 15 MULTI-PULSE GENERATOR The comparison for the position detection is done in pair for each SNIx pin and RDAx bit (SNI2 and RDA2, SNI1 and RDA1, SNI0 and RDA0), a comparison match starts the 16-bit reload timer 0. The write signal is generated by the16-bit reload timer 0 underflow.
Page 434 CHAPTER 15 MULTI-PULSE GENERATOR ■ Timing Generated by Position Detection and Timer Underflow (OPS2 to OPS0 = 011 Figure 15.6-19 Timing Generated by Position Detection and Timer Underflow (OPS2 to OPS0 = 011 SNI2 SNI1 SNI0 TIN0O (TIN) Reload timer 0 counter action RDA2 to...
Page 435 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.5 When Position Detection or Timer Underflow The output timing changes of the operation of the Position Detection or Reload Timer underflow are shown in Figure 15.6-20 and Figure 15.6-21. This operation mode is selected by setting the OPS2 to OPS0 = 100 ■...
Page 436 CHAPTER 15 MULTI-PULSE GENERATOR ■ Timing Generated by Position Detection or Timer Underflow (OPS2 to OPS0 = 100 Figure 15.6-21 Timing Generated by Position Detection or Timer Underflow (OPS2 to OPS0 = 100 SNI2 SNI1 SNI0 WTIN1 Reload Timer 0 Counter Action RDA2 to...
Page 437 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.6 When One-shot Position Detection The output timing change, which is triggered by the input pin SNIx for the one-shot position detection, is shown in Figure 15.6-22. ■ When One-shot Position Detection Same as operation of position detection except that no further position detection will be recognized after the first valid detection until it is changed to ANY OTHER operation mode.
Page 438 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.7 When One-shot Position Detection and Timer Underflow The output timing change of the operation of the One-shot Position Detection and Reload Timer underflow is shown in Figure 15.6-23. ■ When One-shot Position Detection and Timer Underflow Same as operation of position detection and timer underflow except that no further position detection will be recognized after first valid position detection until it is changed to ANY OTHER operation mode.
Page 439 CHAPTER 15 MULTI-PULSE GENERATOR 15.6.4.8 When One-shot Position Detection or Timer Underflow The output timing change of the operation of the One-shot Position Detection or Reload Timer underflow is shown in Figure 15.6-24. This operation mode is selected by setting the OPS2 to OPS0 = 101 ■...
Page 440: Operation Of Dtti1 Input Control
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.5 Operation of DTTI1 Input Control This section describes the operation of the DTTI1 Input Control Circuit. ■ Operation of DTTI1 Input Control The DTTI1 circuit controls the output of the value of PDRx (PORTx Data Register) to the pin OPTx which is multiplexed with the PORTx where OPTx is enable by setting OPEx = 1.
Page 441 CHAPTER 15 MULTI-PULSE GENERATOR ■ DTTI1 Circuit Timing Diagram (D1,D0 = 00 Figure 15.6-26 DTTI1 Circuit Timing Diagram (D1,D0 = 00 φ DTTI1 DTIE* NRSL DTIF DTISP DTTI1 DTIE NRSL DTIF* DTISP 4 Cycles * DTIF goes to low only by writing a “0” to it. Note: In worst case the time from DTTI1 being recognized (after noise cancellation) to DTISP in effect takes 2 cycles, in best case it takes 1 cycle.
Page 442 CHAPTER 15 MULTI-PULSE GENERATOR ■ Relationship between DTTI1 and OPTx Output Table 15.6-4 Relationship between DTTI1 and OPTx Output NRSL DTIE DTTI1 Function DTTI1 has no effect on OPTx. (Initial value) DTTI1 takes effect. Noise filter is not enable. An “L” input at DTTI1 pin triggers the output of the inactive level set in PDRx.
Page 443: Operation Of Noise Cancellation Function
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.6 Operation of Noise Cancellation Function This section describes the noise cancellation function for the SNIx and DTTI1 pins. ■ Operation of Noise Cancellation Function ● DTTI1 Pin Noise Cancellation Function When NRSL bit (bit12) of the Output Control Register (OPCR) is set to "1", the noise cancellation function for DTTI1 pin input can be used.
Page 444: Operation Of 16-Bit Timer
CHAPTER 15 MULTI-PULSE GENERATOR 15.6.7 Operation of 16-bit Timer The 16-bit timer has buffer and compare clear function, which is used for motor speed checking and abnormal detection timeout. The 16-bit timer starts counting up from counter value "0000 " after a reset has been completed and counting enable bit is set. ■...
Page 445 CHAPTER 15 MULTI-PULSE GENERATOR ■ 16-bit Timer Timing The 16-bit timer is incremented based on the prescaler clock and counts up at a rising edge. Note: Before the prescaler clock is changed, the Timer Counter should be disable first by setting the TMEN bit to "0".
Page 446 CHAPTER 15 MULTI-PULSE GENERATOR ■ 16-bit Timer Buffer Operation Timing Diagram Figure 15.6-31 16-bit Timer Buffer Operation Timing Diagram CPU clock Counter value 0000 0001 0002 0000 0001 0002 Timer buffer XXXX 0002 MODE 0 or 1 Load buffer TMEN WTIN1 Timer reset...
Page 447 CHAPTER 15 MULTI-PULSE GENERATOR ■ The Use of the 16-bit Timer in Multi-pulse Generator The timer is reset when write timing or position detection interrupt flag is set, which is selectable by the MODE bit in the Timer Control Status Register (TCSR). The timer can be started or stopped by setting the TMEN bit in the Timer Control Status Register (TCSR).
Page 448: Usage Notes On The Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.7 Usage Notes on the Multi-pulse Generator Notes on using the Multi-pulse Generator are given below. ■ Usage Notes on the Waveform Sequencer ● Notes on using a program for setting • Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from rising- edge synchronization (IPCUR: WTS1,WTS0 = 01 ) to falling-edge synchronization (IPCUR: WTS1,WTS0 = 10...
Page 449 CHAPTER 15 MULTI-PULSE GENERATOR ● Notes about interrupts • When the DTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be returned from interrupt processing. Always clear the DTIF bit. • When the WTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be returned from interrupt processing.
Page 450: Sample Programs For The Multi-Pulse Generator
CHAPTER 15 MULTI-PULSE GENERATOR 15.8 Sample Programs for the Multi-pulse Generator This section contains sample programs for the Multi-pulse Generator. ■ Sample Program for the Multi-pulse Generator ● Processing • An output in PPG is directed to OPT0 and an inverted output in PPG is directed to OPT1 when write timing interrupt is generated.
Page 451 CHAPTER 15 MULTI-PULSE GENERATOR ; Enable write timing interrupt ;Clears interrupt flag MOVW I:OPDBR0,#0009H ;Sets OPT0 pin as PPG output ;Sets OPT1 pin as inverted PPG output ;Starts data transfer ILM,#07H ;Sets ILM in PS to level 7 CCR,#40H ;Interrupt enable LOOP: A,#00H ;Endless loop...
Page 452: Chapter 16 Pwc Timer
CHAPTER 16 PWC Timer This chapter explains the functions and operations of the PWC timer. 16.1 Overview of the PWC Timer 16.2 Block Diagram of the PWC Timer 16.3 PWC Timer Pins 16.4 PWC Timer Registers 16.5 PWC Timer Interrupts 16.6 Operation of the PWC Timer 16.7 Usage Notes on the PWC Timer 16.8 Sample Programs for the PWC Timer...
Page 453: Overview Of The Pwc Timer
16-bit control register. ■ PWC Timer (× 2, PWC Timer 0 is not present in MB90465 Series) The MB90460 series contain two PWC timer channels, while MB90465 series contains only PWC timer 1. The PWC timer has the following characteristics: ●...
Page 454: Block Diagram Of The Pwc Timer
CHAPTER 16 PWC Timer 16.2 Block Diagram of the PWC Timer Figure 16.2-1 PWC timer block diagram. ■ PWC Timer Block Diagram Figure 16.2-1 PWC Timer Block Diagram PWC read Error detection Overflow P07/PWO0 Reload F.F. P23/PWO1 Data transfer Clock Overflow Clock Clock...
Page 455: Pwc Timer Pins
CHAPTER 16 PWC Timer 16.3 PWC Timer Pins This section describes the pins of the PWC timer and provides a pin block diagram. ■ PWC Timer Pins The pins of the PWC timer are shared with the general-purpose ports. Table 16.3-1 lists the functions of the pins, I/O format, and settings required to use the 16-bit reload timer.
Page 456 CHAPTER 16 PWC Timer Figure 16.3-2 shows the block diagram of the PWC timer 1 pins. Figure 16.3-2 Block Diagram of the PWC Timer 1 Pins Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch...
Page 457: Pwc Timer Registers
CHAPTER 16 PWC Timer 16.4 PWC Timer Registers Following are the PWC timer registers. ■ PWC Timer Registers Figure 16.4-1 PWC Timer Registers PWC control status register (Upper) Address: ch.0 000009 ch.1 000029 STRT STOP EDIR EDIE OVIR OVIE POUT PWCSH0, PWCSH1 Read/write...
Page 458: Pwc Control Status Register (Pwcsh0/Pwcsh1, Pwcsl0/Pwcsl1)
CHAPTER 16 PWC Timer 16.4.1 PWC Control Status Register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) The PWC control status register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) controls the PWC timer operation and reads the PWC timer state. ■ PWC Control Status Register, Upper Byte (PWCSH0/PWCSH1) Figure 16.4-2 PWC Control Status Register (PWCSH0/PWCSH1) Address Initial value 00000000...
Page 459 CHAPTER 16 PWC Timer Table 16.4-1 PWC Control Status Register (PWCSH0/PWCSH1) Bit name Function • These bits are used to start, restart, and stop the 16-bit up-count timer. • When these bits are read, the timer operation status is returned. •...
Page 460 CHAPTER 16 PWC Timer ■ PWC control Status Register, Lower Byte (PWCSL0/PWCSL1) Figure 16.4-3 PWC Control Status Register (PWCSL0/PWCSL1) Address Initial value MOD2 MOD1 MOD0 00000000 CKS1 CKS0 Reserved Reserved ch.0: 000008 ch.1: 000028 MOD2 MOD1 MOD0 Operation mode / count edge selection Timer mode and no pulse output Timer mode and pulse output (PWO pin valid): reload mode only...
Page 461 CHAPTER 16 PWC Timer Table 16.4-2 PWC Control Status Register (PWCSL0/PWCSL1) Bit name Function • CKS1 and CKS0 bits are used to select the internal count clock. These bits are used to select the internal count clock. • After reset, the bits are initialized to “00 ”.
Page 462: Pwc Data Buffer Register (Pwc0/Pwc1)
CHAPTER 16 PWC Timer 16.4.2 PWC Data Buffer Register (PWC0/PWC1) The PWC data buffer register (PWC0/PWC1) has functions that depend on the operation mode of the PWC timer. ■ PWC Data Buffer Register (PWC0/PWC1) Figure 16.4-4 PWC Data Buffer Register (PWC0/PWC1) PWC data buffer register (Upper) Address: ch.0 00000B ch.1 00002B...
Page 463: Division Rate Control Register (Div0/Div1)
CHAPTER 16 PWC Timer 16.4.3 Division Rate Control Register (DIV0/DIV1) The division rate control register (DIV0/DIV1) is used in the division period measurement mode (PWCSL:MOD2, 1, and 0 = 011 ). This register has no meaning in other modes. ■ Division Rate Control Register (DIV0/DIV1) Figure 16.4-5 Division Rate Control Register (DIV0/DIV1) Address Initial value...
Page 464: Pwc Timer Interrupts
CHAPTER 16 PWC Timer 16.5 PWC Timer Interrupts The PWC timer is enabled to generate an interrupt request in an overflow of the counter or measurement terminated in pulse-width measurement mode. It is also coordinated with the extended intelligent I/O service (EI OS).
Page 465 CHAPTER 16 PWC Timer ■ EI OS Function of the PWC Timer Since the PWC timer has a circuit that coordinates with EI OS, the counter can start EI OS when an overflow or measurement termination occurs. However, EI OS is available only when other peripheral functions sharing the interrupt control register (ICR) do not use interrupts.
Page 466: Operation Of The Pwc Timer
CHAPTER 16 PWC Timer 16.6 Operation of the PWC Timer The PWC timer is the multi-functional timer based on the 16-bit up-count timer and contains the count input pin and 8-bit input divider. The block has two main functions: timer function and pulse-width count function. Both the timer function and the pulse- width count function enable the selection of two types of count clocks.
Page 467 CHAPTER 16 PWC Timer Figure 16.6-2 Timer Operation (Reload Mode) Overflow Overflow Timer count value Overflow Overflow Overflow FFFF (Restart is invalid) Reload PWC write value Reload Reload Reload Reload Reload Reload 0000 Write to PWC Restart Timer stop Timer starts OVIR flag setting Time POUT bit...
Page 468 CHAPTER 16 PWC Timer Figure 16.6-3 Pulse-width Measurement Operation (Single Measurement Mode, H-width Measurement Mode) PWC input (The solid line indicates the timer count value) measured pulse Timer count value FFFF Timer clears 0000 Start of Timer Timer measurement starts stops EDIR flag setting (termination of measurement) Time...
Page 469: Operation Mode Selection
CHAPTER 16 PWC Timer 16.6.1 Operation Mode Selection Operation modes and count modes are selected according to the setting of PWCS. ■ Operation Mode Selection The following registers are used to set the selection of operation modes and count modes: ●...
Page 470: Starting And Stopping The Timer And Pulse-Width Measurement And Clearing The Timer
CHAPTER 16 PWC Timer 16.6.2 Starting and Stopping the Timer and Pulse-width Measurement and Clearing the Timer To start, restart, and forcibly stop the timer and pulse-width measurement, use the PWCSH0/PWCSH1:STRT and PWCSH0/PWCSH1:STOP. The 16-bit up-count timer is cleared to "0000 "...
Page 471 CHAPTER 16 PWC Timer ● Stopping the timer In one-shot timer mode or single measurement mode, measurement is automatically discontinued when the timer overflows or at the end of a count. The user need not know if the timer has stopped. However, in other modes, the timer must be stopped.
Page 472: Timer Mode Operation
CHAPTER 16 PWC Timer 16.6.3 Timer Mode Operation The timer mode includes the one-shot operation mode and reload operation mode. ■ One-shot Operation Mode When the timer is started in this mode, a count is incremented at each count clock. The timer automatically stops when an overflow occurs from FFFF to 0000 If PWC0/PWC1 is set before the timer has started, the count is started from this set value.
Page 473 CHAPTER 16 PWC Timer ■ Timer Period If the timer is started in one-shot mode after "0000 " is set in PWC0/PWC1, a timer overflow occurs and the count is discontinued if the count exceeds 65536. The following formula is used to calculate the time from start to stop of the timer.
Page 474 CHAPTER 16 PWC Timer ■ Flowchart of Timer Mode Operation Figure 16.6-5 Flowchart of Timer Mode Operation -Select count clock -Select operation mode and timer mode Setting -Clear interrupt flag -Enable interrupt -Set pulse output initial value Set value in PWC Restart Start by STRT bit Reload operation mode...
Page 475: Pulse Width Measurement Mode Operation
CHAPTER 16 PWC Timer 16.6.4 Pulse Width Measurement Mode Operation The signal for pulse-width measurement is input from the PWI pin. The pulse-width measurement mode includes the single measurement mode in which the count is performed only once and continuous measurement mode in which the pulse width is continuously measured.
Page 476 CHAPTER 16 PWC Timer ● Continuous measurement mode At termination of measurement, the timer measurement results are transferred to PWC0/ PWC1. When PWC0/ PWC1 is read, the previous measurement results are read. While measurement is in progress, the previous measurement results are stored in PWC0/ PWC1. During measurement, the timer value cannot be read.
Page 477 CHAPTER 16 PWC Timer ■ Interrupt Request Generation In the pulse-width measurement mode, the following two interrupt requests can be generated: ● Timer overflow interrupt request If an overflow occurs during a count, the overflow flag is set. When the overflow interrupt request is enabled, an interrupt request is generated.
Page 478 CHAPTER 16 PWC Timer Table 16.6-6 Measurement Mode Operation (2/2) Measurement mode MOD2 MOD1 MOD0 Measurement operation Start of Termination of measurement measurement Start Termination Falling edge-to-falling Start Termination edge period measurement The falling edge-to-falling edge time is measured. Start of measurement: When the falling edge is detected Termination of measurement: When the falling edge is detected...
Page 479 CHAPTER 16 PWC Timer ■ Flowchart of Pulse-width Measurement Operation Figure 16.6-6 Flowchart of Pulse-width Measurement Mode Operation -Select count clock -Select operation mode and timer mode Setting -Clear interrupt flag -Enable interrupt Restart Start by STRT bit Continuous measurement mode Single operation mode Detect count start page Detect count start page...
Page 480: Usage Notes On The Pwc Timer
CHAPTER 16 PWC Timer 16.7 Usage Notes on the PWC Timer Notes on using the PWC timer are given below. ■ Usage Notes on the PWC Timer ● Notes about using a program for setting • Changing the following PWCS0/PWCS1 bit values is prohibited during timer operation. The bit values are changed only before the timer is started or after the operation is discontinued.
Page 481 CHAPTER 16 PWC Timer ● Notes about using a program for status checking • In timer mode, the value of the measurement termination interrupt request flag (EDIR) of PWCSH0/ PWCSH1 is insignificant. Therefore, always set "0" in the count end interrupt request (EDIE) enable bit of PWCSH0/PWCSH1.
Page 482 CHAPTER 16 PWC Timer ● Notes about interrupts • When the OVIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an interrupt request is enabled (PWCSH0/PWCSH1:OVIE = 1), control cannot be returned from interrupt processing. Always clear the OVIR bit. •...
Page 483: Sample Programs For The Pwc Timer
CHAPTER 16 PWC Timer 16.8 Sample Programs for the PWC Timer This section contains sample programs for the PWC timer. ■ Sample Program for the PWC Timer ● Processing • An output PWO0 of 30.6 Hz is generated with PWC timer 0. •...
Page 484 CHAPTER 16 PWC Timer User processing RETI ;Returns from interrupt CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------------ VECT CSEGABS=0FFH 0FFC8H ;Sets vector for interrupt #13 (0DH) WARI 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT ENDS START...
Page 485 CHAPTER 16 PWC Timer...
Page 486: Chapter 17 Uart
CHAPTER 17 UART This chapter explains the functions and operation of UART. 17.1 Overview of UART 17.2 Block Diagram of UART 17.3 UART Pins 17.4 UART Registers 17.5 UART Interrupts 17.6 UART Baud Rates 17.7 Operation of UART 17.8 Usage Notes on UART 17.9 Sample Program for UART...
Page 487: Overview Of Uart
CHAPTER 17 UART 17.1 Overview of UART UART is a general-purpose serial data communication interface for performing synchronous or asynchronous (start-stop synchronization) communication with external devices. The UART has a normal bidirectional communication function (normal mode), additionally the master-slave communication function (multiprocessor mode) is only available for the master system.
Page 488 CHAPTER 17 UART Table 17.1-2 UART Operation Mode Data length Operation mode Synchronization Stop bit length When parity is When parity is on mode disabled enabled Normal mode 7 or 8 bits Asynchronous 1 or 2 bits * Multiprocessor – Asynchronous 8+1* bits...
Page 489: Block Diagram Of Uart
CHAPTER 17 UART 17.2 Block Diagram of UART UART consists of the following 11 blocks, the block diagram is shown in Figure 17.2-1. ■ Block Diagram of UART Figure 17.2-1 Block Diagram of UART From Reception interrupt communication #39 (27 prescaler <#37 (25 )*>...
Page 490 CHAPTER 17 UART ● Clock selector The clock selector selects the dedicated baud rate generator, external input clock, or internal clock (clock supplied from the 16-bit reload timer) as the transmitting and receiving clocks. ● Reception control circuit The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter.
Page 491 CHAPTER 17 UART ● Control register 1 (SCR0/SCR1) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 •...
Page 492: Uart Pins
CHAPTER 17 UART 17.3 UART Pins This section describes the UART pins and provides a pin block diagram. ■ UART Pins The UART pins also serve as general ports. Table 17.3-1 lists the pin functions, I/O formats and settings required to use UART. Table 17.3-1 UART Pins Setting required to use Pin name...
Page 493 CHAPTER 17 UART ■ Block Diagram of UART Pins Figure 17.3-1 Block Diagram of UART Pins Resource output Resource input Resource output enable Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1)
Page 494: Uart Registers
CHAPTER 17 UART 17.4 UART Registers The following figure shows the UART registers. ■ UART Registers Figure 17.4-1 UART Registers Serial Control Register SCR0/SCR1 Address: ch.0 000021 ch.1 000025 Read/write Initial value Serial Mode Register SMR0/SMR1 Address: ch.0 000020 SCKE SOE ch.1 000024 Read/write Initial value...
Page 495: Serial Control Register (Scr0/Scr1)
CHAPTER 17 UART 17.4.1 Serial Control Register (SCR0/SCR1) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. ■...
Page 496 CHAPTER 17 UART Table 17.4-1 Serial Control Register (SCR0/SCR1) Bit name Function • This bit selects whether to add a parity bit during transmission in serial data input- PEN: output mode or to detect it during reception. bit15 Parity enable bit (Note) No parity can be used in operation modes 1 and 2.
Page 497: Serial Mode Register (Smr0/Smr1)
CHAPTER 17 UART 17.4.2 Serial Mode Register (SMR0/SMR1) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. ■ Serial Mode Register (SMR0/SMR1) Figure 17.4-3 Serial Mode Register (SMR0/SMR1) Address Initial value c h .
Page 498 CHAPTER 17 UART Table 17.4-2 Serial Mode Register (SMR0/SMR1) Bit name Function • These bits select an operation mode. (Note) bit7, MD1, MD0: Operation Operation mode 1 (multiprocessor mode) can be used only from the master bit6 mode selection bits system during master-slave communication.
Page 499: Serial Status Register (Ssr0/Ssr1)
CHAPTER 17 UART 17.4.3 Serial Status Register (SSR0/SSR1) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. ■ Serial Status Register (SSR0/SSR1) Figure 17.4-4 Serial Status Register (SSR0/SSR1) bit 15 Address Initial value ch.0:000023...
Page 500 CHAPTER 17 UART Table 17.4-3 Functions of Each Bit of Status Register (SSR0/SSR1) Bit name Function • This bit is set to "1" when a parity error occurs during reception and is cleared when "0" is written to the RFC bit of the mode control register (SMR0/SMR1). bit15 •...
Page 501: Input Data Register (Sidr0/Sidr1) And Output Data Register (Sor0/Sor1)
CHAPTER 17 UART 17.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SOR0/SOR1) The input data register (SIDR0/SIDR1) is a serial data reception register. The output data register (SODR0/SODR1) is a serial data transmission register. Both SIDR0/SIDR1 and SODR0/SODR1 registers are located in the same address. ■...
Page 502 CHAPTER 17 UART When data to be transmitted is written to this register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOT0/SOT1 pin). When the data length is 7 bits, the uppermost bit (D7) contains invalid data. When transmission data is written to this register, the transmission data empty flag bit (SS0/SS1: TDRE) is cleared to "0".
Page 503: Communication Prescaler Control Register (Cdcr)
CHAPTER 17 UART 17.4.5 Communication Prescaler Control Register (CDCR) This register controls the division of machine clocks. ■ Communication Prescaler Control Register (CDCR) The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain certain baud rates for various machine cycles.
Page 504 CHAPTER 17 UART Table 17.4-4 Communication Prescaler Control Register Bit name Function • This bit is the operation enable bit of the communication prescaler. • When "0" is set, the communication prescaler stops. bit15 Machine clock divide mode select bit •...
Page 505: Uart Interrupts
CHAPTER 17 UART 17.5 UART Interrupts UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the receive data is set in the input register (SIDR0/SIDR1), or a reception error occurs and transmission data is transferred from output data register 1 (SODR0/SODR1) to the transmission shift register.
Page 506 CHAPTER 17 UART ● Transmission interrupt When transmission data is transferred from the output data register (SODR0/SODR1) to the transfer shift register, the TDRE bit of the status register (SSR0/SSR1) is set to "1". When the transmission interrupts have been enabled (SSR0/SSR1: TIE = 1), a transmission interrupt request is output to the interrupt controller.
Page 507: Reception Interrupt Generation And Flag Set Timing
CHAPTER 17 UART 17.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR0/SSR1: RDRF) and occurrence of a reception error (SSR0/SSR1: PE, ORE, or FRE). ■ Reception Interrupt Generation and Flag Set Timing Receive data is stored in input data register 1 (SIDR0/SIDR1) if a stop bit is detected (in operation mode 0 or 1) or the last bit of data is detected (in operation mode 2) during reception.
Page 508: Transmission Interrupt Generation And Flag Set Timing
CHAPTER 17 UART 17.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the next piece of data is ready to be written to the output data register (SODR0/SODR1). ■ Transmission Interrupt Heneration and Flag Set Timing The transmission data empty flag bit (SSR0/SSR1: TDRE) is set to "1"...
Page 509: Uart Baud Rates
CHAPTER 17 UART 17.6 UART Baud Rates One of the following can be selected as the UART transmitting/receiving block, the block diagram show as below. ■ UART Baud Rate Selection The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can be selected: ●...
Page 510 CHAPTER 17 UART Figure 17.6-1 Baud Rate Selection Circuit SMR0/SMR1 : CS2 to CS0 (Clock selection bits) [Dedicated baud rate generator] Clock selector CDCR0/CDCR1 : MD, DIV2 to DIV0 (Prescaler enable and selection bits) When the bits are 000 to 101 Frequency divider (synchronous) Frequency divider...
Page 511: Baud Rates Determined Using The Dedicated Baud Rate Generator
CHAPTER 17 UART 17.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator This section describes the baud rates that can be set when the clock from the dedicated baud rate generator is selected as the UART transfer clock. ■ Baud Rates determined using the Dedicated Baud Rate Generator When the transfer clock is generated using the dedicated baud rate generator, the machine clock is divided with the machine clock prescaler.
Page 512 CHAPTER 17 UART ● Synchronous transfer clock division ratios A division ratio for synchronous baud rates is selected using the CS2 to CS0 bits of the mode control register (SMR0/SMR1) as listed in Table 17.6-2. Table 17.6-2 Selection of Synchronous Baud Rate Division Ratios CLK synchronization Calculation formula (φ...
Page 513 CHAPTER 17 UART ● Internal timer When CS2 to CS0 are set to "110 " and the internal timer is selected, the formulas for calculating baud rates (when using the reload timer) are as follows: Asynchronous (start-stop synchronization): ( φ÷ N) / (16 × 2 × (n + 1)) CLK synchronization: ( φ÷N) / (2 ×...
Page 514: Baud Rates Determined Using The Internal Timer (16-Bit Reload Timer 0)
CHAPTER 17 UART 17.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) This section describes the settings used when the internal clock supplied from 16-bit reload timer 0 is selected as the UART transfer clock. It also shows the baud rate calculation formulas.
Page 515 CHAPTER 17 UART ● Examples of setting reload values (machine clock: 7.3728 MHz) Table 17.6-4 Baud Rates and Reload Values Reload value Clock asynchronous Clock synchronous Baud rate (start-stop synchronization) (bps) (machine cycle (machine cycle (machine cycle (machine cycle divided by 2) divided by 8) divided by 2) divided by 8)
Page 516: Baud Rates Determined Using The External Clock
CHAPTER 17 UART 17.6.3 Baud Rates Determined Using the External Clock This section describes the settings used when the external clock is selected as the UART transfer clock. It also shows the baud rate calculation formulas. ■ Baud Rates determined using the External Clock The following three settings are required to select the baud rate determined by using the external clock: •...
Page 517: Operation Of Uart
CHAPTER 17 UART 17.7 Operation of UART UART operates in operation modes 0 and 2 for normal bidirectional serial communication and in operation mode 1 for master-slave communication. ■ Operation of UART ● Operation modes There are three UART operation modes: modes 0 to 2. As listed in Table 17.7-1, an operation mode can be selected according to the inter-CPU connection method and data transfer mode Table 17.7-1 UART Operation Mode Data length...
Page 518 CHAPTER 17 UART ● Operation enable bit UART controls both transmission and reception using the operation enable bit for TXE (transmission) and that for RXE (reception). If each of the operations is disabled, stop it as follows: • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and store the received data in the input data register (SIDRI).
Page 519: Operation In Asynchronous Mode (Operation Modes 0 And 1)
CHAPTER 17 UART 17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode ●...
Page 520 CHAPTER 17 UART ● Reception operation Reception operation is performed every time it is enabled (SCR0/SCR1: RXE = 1). When a start bit is detected, a frame of data is received according to the data format specified by the control register (SCR0/ SCR1).
Page 521: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 17 UART 17.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for UART operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ● Transfer data format In synchronous mode, 8-bit data is transferred using the LSB first method, in which start and stop bits are not added.
Page 522 CHAPTER 17 UART ● Initialization The following shows the set values of each control register using the synchronous mode: [Mode control register (SMR0/SMR1)] MD1,MD0:"10 " CS2,CS1,CS0:Specify clock input using the clock selector. SCKE:1 for dedicated baud rate generator or internal timer 0 for clock output and external clock (clock input) SOE:1 for transmission;...
Page 523: Bidirectional Communication Function (Normal Mode)
CHAPTER 17 UART 17.7.3 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication (one-to-one connection) is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 17.7-4 are required to operate UART in normal mode (operation mode 0 or 2).
Page 524 CHAPTER 17 UART ● Communication procedure Communication starts from the transmitting system at an optional timing when transmission data has been prepared. An ANS is returned periodically (byte by byte in this example) when the receiving system receives transmission data. Figure 17.7-6 shows an example of a bidirectional communication flowchart. Figure 17.7-6 Example of Bidirectional Communication Flowchart (Transmitting system) (Receiving system)
Page 525: Master-Slave Communication Function (Multiprocessor Mode)
CHAPTER 17 UART 17.7.4 Master-slave Communication Function (Multiprocessor Mode) With UART, communication with multiple CPUs connected in master-slave mode is available in operation mode 1. However, UART can be used only from the master system. ■ Master-slave Communication Function The settings shown in Figure 17.7-7 are required to operate UART in multiprocessor mode (operation mode 1).
Page 526 CHAPTER 17 UART ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table Table 17.7-2 Selection of the Master-slave Communication Function Operation mode Synchronizati Data Parity Stop bit on method Master CPU Slave CPU A/D = 1 Address transmission and reception...
Page 527 CHAPTER 17 UART Figure 17.7-9 Master-slave Communication Flowchart (Master CPU) Start Select transfer mode 1 Set the data for selecting the slave CPUs in D0 to D7 and set “1” in A/D to transfer one byte Set “0” in A/D Reception is enabled Communication with the slave CPU End communication?
Page 528: Usage Notes On Uart
CHAPTER 17 UART 17.8 Usage Notes on UART Notes on using UART are given below. ■ Notes on using UART ● Enabling operations In UART, the control register (SCR0/SCR1) has both TXE (transmission) and RXE (reception) operation enable bits. Both transmission and reception operations must be enabled before the transfer starts because they have been disabled as the default value (initial value).
Page 529: Sample Program For Uart
CHAPTER 17 UART 17.9 Sample Program for UART This section contains a sample program for UART. ■ Sample Program for UART ● Processing specifications The UART1 bidirectional communication function (normal mode) is used to perform serial transmission and reception. • Operation mode 0, asynchronous mode, eight data bits, two stop bits and no parity are set. •...
Page 530 CHAPTER 17 UART ;Enables transmission and reception operations I:SSR1,#00000010B ;Disables transmission interrupts and enables reception ; interrupts I:SODR1,#13H ;Writes transmission data ILM,#07H ;Sets ILM in PS to level 7 CCR,#40H ;Enables interrupts LOOP: A,#00H ;Endless loop A,#01H LOOP ;-------Interrupt program------------------------------------------------------------------------------------------- WARI: A,SIDR1 ;Reads receive data...
Page 531 CHAPTER 17 UART...
Page 532: Chapter 18 Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT This chapter describes the functions and operation of the DTP/external interrupt circuit. 18.1 Overview of the DTP/External Interrupt Circuit 18.2 Block Diagram of the DTP/External Interrupt Circuit 18.3 DTP/External Interrupt Circuit Pins 18.4 DTP/External Interrupt Circuit Registers 18.5 Operation of the DTP/External Interrupt Circuit 18.6 Usage Notes on the DTP/External Interrupt Circuit 18.7 Sample Programs for the DTP/External Interrupt Circuit...
Page 533: Overview Of The Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.1 Overview of the DTP/External Interrupt Circuit The data transfer peripheral (DTP)/external interrupt circuit is located between external peripherals and the F MC-16LX CPU. It receives interrupt requests and data transfer requests from peripherals and passes them to the CPU to generate external interrupt requests or activate the extended intelligent I/O service (EI OS).
Page 534 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ■ Interrupt of the DTP/external Interrupt Circuit and EI Table 18.1-2 Interrupt of the DTP/external Interrupt Circuit and EI Interrupt control register Vector table address Interrupt Channel number Register Address Lower Middle Upper name #20 (14 0000B4 FFFFAC FFFFAD...
Page 535: Block Diagram Of The Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.2 Block Diagram of the DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of four blocks, the block diagram is shown in Figure 18.2-1. ■ Block Diagram of the DTP/external Interrupt Circuit Figure 18.2-1 Block Diagram of the DTP/external Interrupt Circuit Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Selector...
Page 536 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ● DTP/external interrupt input detection circuit Upon detecting the level or edge selected for each pin by the interrupt request level setting register (ELVR), this circuit sets to "1" the IR bit of the DTP/external interrupt cause register (EIRR) that corresponds to the pin.
Page 537: Dtp/External Interrupt Circuit Pins
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.3 DTP/External Interrupt Circuit Pins This section describes the DTP/external interrupt circuit pins and provides a pin block diagram. ■ DTP/external Interrupt Circuit Pins The DTP/external interrupt circuit pins are also used as general ports. Table 18.3-1 lists the pin functions, I/O formats, and settings required to use the DTP/external interrupt circuit.
Page 538 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ■ Block Diagram of the DTP/external Interrupt Circuit Pins Figure 18.3-1 Block Diagram of the DTP/external Interrupt Circuit Pins (INT0 to INT6) Resource output Resource input Port data register (PDR) Resource output enable Pull-up resistor About 50k PDR read Output latch...
Page 539: Dtp/External Interrupt Circuit Registers
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.4 DTP/External Interrupt Circuit Registers This section describes DTP/external interrupt circuit registers. ■ DTP/External Interrupt Circuit Registers Figure 18.4-1 DTP/external Interrupt Circuit Registers DTP / Interrupt Cause Register Address: 000031 EIRR Read/write Initial value DTP / Interrupt Enable Register Address: 000030 ENIR Read/write...
Page 540: Dtp/Interrupt Cause Register (Eirr)
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.4.1 DTP/interrupt Cause Register (EIRR) The DTP/interrupt cause register (EIRR) stores and clears interrupt causes. ■ DTP/interrupt Cause Register (EIRR) Figure 18.4-2 DTP/interrupt Cause Register (EIRR) Address Initial value ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (ENIR) XXXXXXXX 000031...
Page 541: Dtp/Interrupt Enable Register (Enir)
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.4.2 DTP/interrupt Enable Register (ENIR) The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt requests to the CPU. ■ DTP/interrupt Enable Register (ENIR) Figure 18.4-3 DTP/interrupt Enable Register (ENIR) Initial value Address 00000000 000030 (EIRR)
Page 542 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT Table 18.4-3 Correspondence between the DTP/interrupt Control Registers (EIRR, ENIR) and Each Channel External interrupt request DTP/external interrupt pin Interrupt number External interrupt request flag bit enable bit P63/INT7 #27 (1B P16/INT6 P15/INT5 #25 (19 P14/INT4 P13/INT3 #22 (16...
Page 543: Request Level Setting Register (Elvr)
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.4.3 Request Level Setting Register (ELVR) The request level setting register (ELVR) selects the level or edge of the signal input to each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause. ■...
Page 544: Operation Of The Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.5 Operation of the DTP/External Interrupt Circuit The DTP/external interrupt circuit provides the external interrupt function and the DTP function. This section describes the settings required for each function and the operation of the circuit. ■...
Page 545 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ● Switching between the external interrupt function and the DTP function Switching between the external interrupt function and the DTP function is accomplished by the ISE bit of the corresponding interrupt control register (ICR). If the ISE bit is "1", the extended intelligent I/O service OS) is enabled and the circuit executes its DTP function.
Page 546 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT Figure 18.5-2 shows the operation of the DTP/external interrupt circuit. Figure 18.5-2 Operation of the DTP/external Interrupt Circuit DTP/external interrupt circuit Another request Interrupt controller ELVR ELVR Interrupt processing microprogram ELVR Cause DTP handling routine OS is started) Generation of DTP/ Transfer data between memory...
Page 547: External Interrupt Function
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.5.1 External Interrupt Function The DTP/external interrupt circuit has an external interrupt function that generates an interrupt request when a selected signal level is input to a DTP/external interrupt pin. ■ External Interrupt Function If the edge or level selected for a DTP/external interrupt pin by the request level setting register (ELVR) is detected at that pin, the corresponding ER7 to ER0 bit of the DTP/interrupt cause register (EIRR) is set to "1".
Page 548: Dtp Function
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.5.2 DTP Function The DTP/external interrupt circuit has a DTP function that detects a signal supplied to a DTP/external interrupt pin from an external peripheral and activates the extended intelligent I/O service. ■ Operation of the DTP Function The DTP function detects a data transfer request signal from an external peripheral to automatically transfer data between memory and the peripheral.
Page 549: Usage Notes On The Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.6 Usage Notes on the DTP/External Interrupt Circuit Notes on the signal to be input to the DTP/external interrupt circuit, release from standby mode, and interrupts are given below. ■ Usage Notes on the DTP/external Interrupt Circuit ●...
Page 550 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT Figure 18.6-2 DTP/external Interrupt Cause and Interrupt Request when the Output of Interrupt Requests is enabled DTP/external interrupt H level cause (when the H level is detected) Removal of the interrupt cause Interrupt request to the interrupt controller Request becomes inactive when cause flip-flop is cleared...
Page 551: Sample Programs For The Dtp/External Interrupt Circuit
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT 18.7 Sample Programs for the DTP/External Interrupt Circuit This section contains sample programs for the external interrupt function and the DTP function. ■ Sample Program for the External Interrupt Function ● Processing • The rising edge of the pulse input to the INT0 pin is detected, and an external interrupt is generated. ●...
Page 552 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT RETI ;Returns from interrupt CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------------------ VECT CSEG ABS=0FFH 0FFACH ;Sets vector for interrupt #20 (14H) WARI 0FFDCH ;Sets reset vector START ;Sets single-chip mode VECT ENDS START ■ Sample Program for the DTP Function ●...
Page 553 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ;Enables EI OS. Channel 0 BAPL,#00H ;Sets the address of the output data BAPM,#06H BAPH,#00H ISCS,#12H ;Byte transfer. I/O address fixed. Buffer address + 1. Transfer from memory to I/O IOAL,#00H ;Specifies port 0 (PDR0) as the transfer destination IOAH,#00H ;address pointer DCTL,#0AH...
Page 554: Chapter 19 Delayed Interrupt Generator Module
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE This chapter describes the functions and operation of the delayed interrupt generator module. 19.1 Overview of the Delayed Interrupt Generator Module 19.2 Delayed Interrupt Generator Module Register 19.3 Operation of the Delayed Interrupt Generator Module 19.4 Usage Notes on the Delayed Interrupt Generator Module...
Page 555: Overview Of The Delayed Interrupt Generator Module
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE 19.1 Overview of the Delayed Interrupt Generator Module The delayed interrupt generator module generates interrupts for task switching. By using this module, software can issue and cancel interrupt requests for the F MC-16LX CPU. ■...
Page 556: Delayed Interrupt Generator Module Register
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE 19.2 Delayed Interrupt Generator Module Register This section lists the delayed interrupt generator module register. ■ Delayed Interrupt Generator Module Register (DIRR) Figure 19.2-1 Delayed Interrupt Generator Module Register (DIRR) Address bit Initial value —...
Page 557: Operation Of The Delayed Interrupt Generator Module
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE 19.3 Operation of the Delayed Interrupt Generator Module When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch in the delayed interrupt generator module is set and an interrupt request is generated to the interrupt controller.
Page 558: Usage Notes On The Delayed Interrupt Generator Module
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE 19.4 Usage Notes on the Delayed Interrupt Generator Module Notes on using the delayed interrupt generator module are given below. ■ Usage Notes on the Delayed Interrupt Request Latch • This latch is set by writing "1" to the relevant bit of DIRR and cleared by writing "0" to the same bit. Note that interrupt processing is restarted at the moment control returns from interrupt processing unless software is created to clear the cause in the interrupt processing routine.
Page 559 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE...
Page 560 CHAPTER 20 8/10-BIT A/D CONVERTER This chapter describes the functions and operation of the 8/10-bit A/D converter. 20.1 Overview of the 8/10-bit A/D Converter 20.2 Block Diagram of the 8/10-bit A/D Converter 20.3 8/10-bit A/D Converter Pins 20.4 8/10-bit A/D Converter Registers 20.5 8/10-bit A/D Converter Interrupts 20.6 Operation of the 8/10-bit A/D Converter 20.7 Usage Notes on the 8/10-bit A/D Converter...
Page 561: Chapter 20 8/10-Bit A/D Converter
CHAPTER 20 8/10-BIT A/D CONVERTER 20.1 Overview of the 8/10-bit A/D Converter Using the RC-type successive approximation conversion method, the 8/10-bit A/D converter converts an analog input voltage into a 10-bit or 8-bit digital value. An input signal is selected from eight channels for analog input pins. The conversion can be activated by software, an internal clock, and 16-bit free-run timer zero detection.
Page 562 CHAPTER 20 8/10-BIT A/D CONVERTER ■ 8/10-bit A/D Converter Interrupts and EI Table 20.1-2 8/10-bit A/D Converter Interrupts and EI Interrupt control register Vector table address Interrupt no. EI²OS Register Address Lower Upper Bank name #11 (0B 0000B0 FFFFD0 FFFFD1 FFFFD2 ICR00 O: Can be used and interrupt request flag is cleared by EI...
Page 563: Block Diagram Of The 8/10-Bit A/D Converter
CHAPTER 20 8/10-BIT A/D CONVERTER 20.2 Block Diagram of the 8/10-bit A/D Converter The 8/10-bit A/D converter has nine blocks, the block diagram is shown in Figure 20.2-1. ■ Block Diagram of the 8/10-bit A/D Converter Figure 20.2-1 Block Diagram of the 8/10-bit A/D Converter D/A converter Sequential compare register Comparator...
Page 564 CHAPTER 20 8/10-BIT A/D CONVERTER ● Clock selector The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer channel 1 output or 16-bit free-run timer zero detection can be used as the activation clock. ● Decoder This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and ANS0 to ANS2 bits of the A/D control status register (ADCS0).
Page 565: 8/10-Bit A/D Converter Pins
CHAPTER 20 8/10-BIT A/D CONVERTER 20.3 8/10-bit A/D Converter Pins This section describes the 8/10-bit A/D converter pins and provides pin block diagrams. ■ 8/10-bit A/D Converter Pins The A/D converter pins are also used as general ports. Table 20.3-1 lists the pin functions, I/O formats, and settings required to use the 8/10-bit A/D converter.
Page 566 CHAPTER 20 8/10-BIT A/D CONVERTER Notes: • The MB90460/465 series runs only in single-chip mode so only internal ROM and RAM and internal peripheral address space can be accessed. • To use the pin as an analog input pin, set the corresponding bit of the ADER register to "1". The value read from the PDR5 register is "0".
Page 567: 8/10-Bit A/D Converter Registers
CHAPTER 20 8/10-BIT A/D CONVERTER 20.4 8/10-bit A/D Converter Registers This section lists the 8/10-bit A/D converter registers. ■ 8/10-bit A/D Converter Registers Figure 20.4-1 8/10-bit A/D Converter Registers Analog Input Enable Register Address: 000017 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0...
Page 568: A/D Control Status Register 1 (Adcs1)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.4.1 A/D Control Status Register 1 (ADCS1) A/D control status register 1 (ADCS1) selects activation by software or activation trigger, enables or disables interrupt requests, and indicates interrupt request status and whether conversion is halted or in progress. ■...
Page 569 CHAPTER 20 8/10-BIT A/D CONVERTER Table 20.4-1 A/D Dontrol Status Register 1 (ADCS1) Bit name Function • This bit indicates the operating status of the A/D converter. • If the value read from this bit is "0", A/D conversion has halted. If the read value is "1", A/D conversion is in progress.
Page 570: A/D Control Status Register 0 (Adcs0)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.4.2 A/D Control Status Register 0 (ADCS0) A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion channel. ■ A/D Control Status Register 0 (ADCS0) Figure 20.4-3 A/D Control Status Register 0 (ADCS0) Address Initial value (ADCS: H)
Page 571 CHAPTER 20 8/10-BIT A/D CONVERTER Table 20.4-2 A/D Control Status Register 0 (ADCS0) Bit name Function • These bits select the conversion mode of the A/D conversion function. • The two-bit value of the MD1 and MD0 bits determines the mode that is selected from among four modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode.
Page 572 CHAPTER 20 8/10-BIT A/D CONVERTER Table 20.4-2 A/D Control Status Register 0 (ADCS0) Bit name Function • These bits set the A/D conversion end channel. • When activated, A/D conversion is performed up to the channel specified by these bits. bit2 ANE2 to ANE0: •...
Page 573: A/D Data Register (Adcr0/Adcr1)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.4.3 A/D Data Register (ADCR0/ADCR1) The A/D data register (ADCR0/ADCR1) holds the result of A/D conversion and selects the resolution of A/D conversion. ■ A/D Data Register (ADCR0/ADCR1) Figure 20.4-4 A/D Data Register (ADCR0/ADCR1) Initial value 000037 CT1 CT0 00000...
Page 574 CHAPTER 20 8/10-BIT A/D CONVERTER Table 20.4-3 Function Description of Each bit of A/D Control Status Register 0 (ADCS0) Bit name Function • This bit selects an A/D conversion resolution. S10: • Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a A/D conversion bit15 resolution of 8 bits.
Page 575: 8/10-Bit A/D Converter Interrupts
CHAPTER 20 8/10-BIT A/D CONVERTER 20.5 8/10-bit A/D Converter Interrupts The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D conversion is set in the A/D data register. This function supports the extended intelligent I/O service (EI OS).
Page 576: Operation Of The 8/10-Bit A/D Converter
CHAPTER 20 8/10-BIT A/D CONVERTER 20.6 Operation of the 8/10-bit A/D Converter The 8/10-bit A/D converter has three conversion modes: single conversion mode, continuous conversion mode, and stop conversion mode. This section describes operation in each mode. ■ Operation in Single Conversion Mode In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted.
Page 577 CHAPTER 20 8/10-BIT A/D CONVERTER Figure 20.6-2 Settings for Continuous Conversion Mode BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS ADCR Holds the conversion data. : Used : Set to "1" the bit corresponding to the pin used. ADER 1 : Set "1".
Page 578 CHAPTER 20 8/10-BIT A/D CONVERTER Reference: The following are sample conversion sequences in stop conversion mode: ANS = 000 , ANE = 011 AN0 → Pause → AN1 → Pause → AN2 → Pause → AN0 → Repeat ANS = 110 , ANE = 001 AN6 →...
Page 579: Conversion Using Ei 2 Os
CHAPTER 20 8/10-BIT A/D CONVERTER 20.6.1 Conversion using EI The 8/10-bit A/D converter can use EI OS transfer the A/D conversion result to memory. ■ Conversion using EI Figure 20.6-4 shows the operation flow when EI OS is used. Figure 20.6-4 Sample Operation Flowchart when EI OS is used Starting A/D conversion Sample and hold...
Page 580: A/D Conversion Data Protection Function
CHAPTER 20 8/10-BIT A/D CONVERTER 20.6.2 A/D Conversion Data Protection Function When A/D conversion is performed in the interrupt enabled state, the conversion data protection function operates. ■ A/D Conversion Data Protection Function The A/D converter has just one data register that holds conversion data. When a single A/D conversion is completed, the data in the data register is rewritten.
Page 581 CHAPTER 20 8/10-BIT A/D CONVERTER Figure 20.6-5 Operation Flowchart of the Data Protection Function when EI OS is used Set EI Start continuous A/D conversion End first conversion Store data in the data register Activate EI End second conversion Has EI Halt A/D ended? Store data in the data...
Page 582: Usage Notes On The 8/10-Bit A/D Converter
CHAPTER 20 8/10-BIT A/D CONVERTER 20.7 Usage Notes on the 8/10-bit A/D Converter Notes on using the 8/10-bit A/D converter. ■ Usage Notes on the 8/10-bit A/D Converter ● Analog input pin The A/D input pins are also used as the I/O pins of port 5. The port 5 data register (DDR5) and analog input enable register (ADER) determine which pin is used for which purpose.
Page 583: Sample Program 1 For The 8/10-Bit A/D Converter (Single Conversion Mode Using Ei 2 Os)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.8 Sample Program 1 for the 8/10-bit A/D Converter (Single Conversion Mode Using EI This section contains a sample program for A/D conversion in single conversion mode using EI ■ Sample Program for Single Conversion Mode using EI ●...
Page 584 CHAPTER 20 8/10-BIT A/D CONVERTER ADCR0 000036H ;A/D data register ADCR1 000037H ;-------Main program------------------------------------------------------------------------------------------------------ CODE CSEG START: ;Assumes that the stack pointer (SP) has already been initialized CCR,#0BFH ;Disables interrupts ICR00,#00H ;Interrupt level: 0 (highest priority) BAPL,#00H ;Sets the address to which the conversion data is transferred and stored BAPM,#02H ;(Uses 200H to 205H.)
Page 585: Sample Program 2 For The 8/10-Bit A/D Converter (Continuous Conversion Mode Using Ei 2 Os)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.9 Sample Program 2 for the 8/10-bit A/D Converter (Continuous Conversion Mode Using EI This section contains a sample program for A/D conversion in continuous conversion mode using EI ■ Sample Program for Continuous Conversion Mode using EI ●...
Page 586 CHAPTER 20 8/10-BIT A/D CONVERTER START: ;Assumes that the stack pointer (SP) has already been initialized CCR,#0BFH ;Disables interrupts ICR10,#08H ;Interrupt level; 0 (highest priority). Enables interrupts BAPL,#00H ;Sets the address to which conversion data is stored BAPM,#06H ;(Uses 600H to 60BH.) BAPH,#00H ISCS,#18H ;Transfers word data, adds 1 to the address, then...
Page 587: Sample Program 3 For The 8/10-Bit A/D Converter (Stop Conversion Mode Using Ei Os)
CHAPTER 20 8/10-BIT A/D CONVERTER 20.10 Sample Program 3 for the 8/10-bit A/D Converter (Stop Conversion Mode Using EI This section contains a sample program for A/D conversion in stop conversion mode using EI ■ Sample Program for Stop Conversion Mode using EI ●...
Page 588 CHAPTER 20 8/10-BIT A/D CONVERTER TMRD1 000088H ;16-bit reload register 1 ;-------Main program------------------------------------------------------------------------------------------------ CODE CSEG START: ;Assumes that the stack pointer (SP) has already been initialized CCR,#0BFH ;Disables interrupts ICR00,#08H ;Interrupt level: TMCSR1:L0 (highest priority) BAPL,#00H ;Sets the address to which conversion data is stored BAPM,#06H ;(Uses 600H to 617H.) BAPH,#00H...
Page 589 CHAPTER 20 8/10-BIT A/D CONVERTER...
Page 590: Chapter 21 Rom Correction Function
CHAPTER 21 ROM CORRECTION FUNCTION This chapter describes the functions and operation of the ROM correction function. 21.1 Overview of the ROM Correction Function 21.2 Block Diagram of ROM Correction Function 21.3 ROM Correction Function Registers 21.4 Operation of the ROM Correction Function 21.5 Example of Using ROM Correction Function...
Page 591: Overview Of The Rom Correction Function
CHAPTER 21 ROM CORRECTION FUNCTION 21.1 Overview of the ROM Correction Function An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code (01 ) when the corresponding address is equal to the value set in a program address detect register.
Page 592: Block Diagram Of Rom Correction Function
CHAPTER 21 ROM CORRECTION FUNCTION 21.2 Block Diagram of ROM Correction Function The block diagram of ROM correction function is shown as below. ■ Block Diagram of ROM Correction Function Figure 21.2-1 Block Diagram of ROM Correction Function Address latch INT9 Comparator command...
Page 593: Rom Correction Function Registers
CHAPTER 21 ROM CORRECTION FUNCTION 21.3 ROM Correction Function Registers The section lists the ROM correction function registers. ■ ROM Correction Function Registers Figure 21.3-1 Registers of ROM Correction Function Program Address Detection Register 0/1 Upper byte Middle byte Lower byte PADR0 Address : 1FF2 /1FF1...
Page 594: Program Aaddress Detection Register (Padr0/Padr1)
CHAPTER 21 ROM CORRECTION FUNCTION 21.3.1 Program Aaddress Detection Register (PADR0/PADR1) The program address detection register (PADR0/PADR1) is a 24-bit register and used to store the address to be compared with internal address bus. ■ Program Address Detection Register 0/1 (PADR0/PADR1) Figure 21.3-2 Program Address Detection Register 0/1 Program Address Detection Register 0/1 Upper byte...
Page 595: Program Address Detection Control Status Register (Pacsr)
CHAPTER 21 ROM CORRECTION FUNCTION 21.3.2 Program Address Detection Control Status Register (PACSR) The program address detection control status register (PACSR) is an 8-bit register and used to control the operation of ROM correction function. ■ Program Address Detection Control Status Register (PACSR) Figure 21.3-3 Program Address Detection Control Status Register Address bit 7...
Page 596 CHAPTER 21 ROM CORRECTION FUNCTION Table 21.3-2 Program Address Detection Control Status Register Bit name Function bit7 • Always write “0” to these bits. Reserved bits bit4 • ADR1 operation enable bit. AD1E: • When this bit is “1”, the value set in the PADR1 register is compared with the bit3 Address detection register 1 address.
Page 597: Operation Of The Rom Correction Function
CHAPTER 21 ROM CORRECTION FUNCTION 21.4 Operation of the ROM Correction Function If the program counter specifies the same address as that in program address detection register (PADR), the INT9 instruction is executed. The ROM correction function can be done by processing the INT9 instruction routine. ■...
Page 598: Example Of Using Rom Correction Function
CHAPTER 21 ROM CORRECTION FUNCTION 21.5 Example of Using ROM Correction Function This section contains example of Using the Address Match Detection Function. ■ System Configuration Figure 21.5-1 System Configuration Example PROM MC-16LX Pull-up resistor Connector (UART) ■ E PROM Memory Map Table 21.5-1 E PROM Memory Map Address...
Page 599 CHAPTER 21 ROM CORRECTION FUNCTION ■ If a Program Error Occurs The original of a patch program and its address is transferred to the MCU via the connector (UART). The MCU writes the information to E PROM. ■ Reset Sequence After the reset sequence is completed, the MCU reads the value of E PROM.
Page 600 CHAPTER 21 ROM CORRECTION FUNCTION Figure 21.5-3 Flowchart of Program Patch Processing Reset Read the 00 of E PROM INT9 0000 PROM) = 0 Clear interrupt program Read the address 0001 to 0003 PROM) PADR0 (MCU) To patch program JMP 000400H Read the patch program 0010 to 0090...
Page 601 CHAPTER 21 ROM CORRECTION FUNCTION...
Page 602: Chapter 22 Rom Mirroring Function Selection Module
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE This chapter explains the function and operation of the MB90460/465 series ROM mirroring function selection module. 22.1 Overview of the ROM Mirroring Function Selection Module 22.2 ROM Mirroring Function Selection Register (ROMM)
Page 603: Overview Of The Rom Mirroring Function Selection Module
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 22.1 Overview of the ROM Mirroring Function Selection Module The ROM mirroring function selection module can access bank FF located in ROM from bank 00 by setting the register. ■ ROM Mirroring Function Selection Module Register ROM Mirror Function Selection Register Address : 00006F —...
Page 604: Rom Mirroring Function Selection Register (Romm)
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 22.2 ROM Mirroring Function Selection Register (ROMM) The ROM mirroring function selection register (ROMM) is used to enable mirroring function. ■ ROM Mirroring Function Selection Register (ROMM) Figure 22.2-1 ROM Mirroring Function Selection Register Reset value Reserved ReservedReservedReservedReserved ReservedReserved XXXXXXX1...
Page 605 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE MB90462 MB90467 MB90F462 MB90F462A MB90F463A MB90V460 FF0000 FF0000 FF0000 FF0000 FE0000 FF0000 Address 1 000900 000900 000900 000900 000900 002100 Address 2 Figure 22.2-2 Memory Space Address FFFFFF ROM area ROM area Address 1 010000 ROM area 004000...
Page 606: Chapter 23 512K / 1024K Bit Flash Memory
CHAPTER 23 512K / 1024K BIT FLASH MEMORY The following explains the functions and operations of the 512K / 1024K bit flash memory. Three methods of data writing/deleting to the flash memory are provided: 23.1 Overview of the 512K / 1024K Bit Flash Memory 23.2 512K / 1024K Bit Flash Memory Sector Configuration 23.3 Flash Memory Control Status Register (FMCS) 23.4 Method of Starting the Automatic Algorithm in Flash Memory...
Page 607: Overview Of The 512K / 1024K Bit Flash Memory
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.1 Overview of the 512K / 1024K Bit Flash Memory The 512K bit flash memory is allocated in the FF bank on the CPU memory map while 1024K bit flash memory is allocated in FE and FF bank. The function of the flash memory interface circuit enables the read/access or program access from the CPU to the flash memory, same as the mask ROM.
Page 608: 1024K Bit Flash Memory Sector Configuration
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.2 512K / 1024K Bit Flash Memory Sector Configuration Figure 23.2-1 and Figure 23.2-2 and shows the sector configuration in the 512K bit flash memory. The address indicated in Figure 23.2-1 and Figure 23.2-2 is classified into the upper address and lower address of each sector.
Page 609: Flash Memory Control Status Register (Fmcs)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.3 Flash Memory Control Status Register (FMCS) The FMCS, which exists in the flash memory interface circuit, is used when data is written to or erased from flash memory. ■ Control Status Register (FMCS) LPM1 LPM0 INTE...
Page 610 CHAPTER 23 512K / 1024K BIT FLASH MEMORY [bit4] RDY (Ready) This bit is the flash memory write/delete permission bit. While this bit is "0", the write/delete cannot be executed to the flash memory. Even in this state, however, suspend commands such as the read/reset command and the sector deletion temporary stop can be accepted.
Page 611: Method Of Starting The Automatic Algorithm In Flash Memory
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.4 Method of Starting the Automatic Algorithm in Flash Memory There are four types of commands for starting the automatic algorithm in the flash memory, i.e., the read/reset command, write command, and chip deletion command. In addition, the sector deletion command can be temporarily stopped and restarted.
Page 612: Verifying Automatic Algorithm Execution Status
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.5 Verifying Automatic Algorithm Execution Status The flash memory contains the hardware for posting the internal flash memory operating status or the flash memory operation completion, because the automatic algorithm executes the sequence of data writing/deleting procedures. This automatic algorithm can verify the internal flash memory operating status, depending on the following hardware sequence.
Page 613 CHAPTER 23 512K / 1024K BIT FLASH MEMORY Table 23.5-2 Hardware Sequence Flag Functions State Write operation --> Write DQ7 --> Toggle --> 0 --> 0 --> completion (when the DATA:7 DATA:6 DATA:5 DATA:3 write address is specified) Chip/sector deletion Toggle -->...
Page 614: Data Polling Flag (Dq7)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.5.1 Data Polling Flag (DQ7) The data polling flag (DQ7) indicates whether the automatic algorithm is being executed or has been terminated, using the data polling function. Table 23.5-3 shows the data polling flag status transition.
Page 615 CHAPTER 23 512K / 1024K BIT FLASH MEMORY Table 23.5-3 Data Polling Flag Station Transition - Status transition during normal operation Sector deletion Sector deletion During the sector -->Deletion temporary stop Chip/sector Operating deletion temporary Sector deletion Write operation temporary stop -->Restart deletion status...
Page 616: Toggle Bit Flag (Dq6)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.5.2 Toggle Bit Flag (DQ6) The toggle bit flag specifies whether the automatic algorithm is being executed or has been terminated, using the toggle bit function, the same as the data polling flag. Table 23.5-4 shows the toggle bit flag status transition.
Page 617: Time Limit Exceeded Flag (Dq5)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.5.3 Time limit Exceeded Flag (DQ5) The time limit exceeded flag indicates that the automatic algorithm execution time has exceeded the time defined within the flash memory (i.e., internal pulse count). Table 23.5-5 shows the transition of the time limit exceeded flag status.
Page 618: Sector Deletion Timer Flag (Dq3)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.5.4 Sector Deletion Timer Flag (DQ3) After starting the sector deletion command, the sector deletion timer flag indicates whether it is "during the sector deletion waiting period". Table 23.5-6 shows the sector deletion timer flag status transition.
Page 619: Detailed Explanation On The Flash Memory Write/Delete
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6 Detailed Explanation on the Flash Memory Write/Delete This section explains the procedures for issuing the command to start the automatic algorithm, reading/resetting the flash memory, writing the data to the flash memory, deleting the chip, deleting the sector, temporarily stopping the sector deletion, and restarting the sector deletion.
Page 620: Setting The Read/Reset Status
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.1 Setting the Read/Reset Status This section explains the procedure of issuing the read/reset command and setting the flash memory to the read/reset status. ■ Setting the Read/Reset Status When the flash memory is set to the read/reset status, the read/reset command can be executed by continuously sending the read/reset command, listed in the command sequence table (see "23.4 Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
Page 621: Writing The Data
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.2 Writing the Data This section explains the procedure of issuing the write command and writing the data to the flash memory. Figure 23.6-1 shows an example of procedure of writing data to the flash memory.
Page 622 CHAPTER 23 512K / 1024K BIT FLASH MEMORY Figure 23.6-1 Example of Procedure of Writing the Data to the Flash Memory Start the write FMCS:WE (bit5) Flash memory write enabled Write command sequence 1.FxAAAA XXAA 2.Fx5554 XX55 3.FxAAAA XXA0 4.Write address Write data Next address Internal address read...
Page 623: Deleting The Data (Chip Deletion)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.3 Deleting the Data (Chip Deletion) This section explains the procedure of issuing the chip deletion command and deleting all the data in the flash memory. ■ Deleting the data (Chip deletion) All the data can be deleted from the flash memory by continuously sending the chip deletion command, listed in the command sequence table (see "23.4 Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
Page 624: Deleting The Data (Sector Deletion)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.4 Deleting the Data (Sector Deletion) This section explains the procedure of issuing the sector deletion command and deleting any sector from the flash memory. This command enables each sector to be deleted, and two or more sectors to be specified at the same time.
Page 625 CHAPTER 23 512K / 1024K BIT FLASH MEMORY Figure 23.6-2 Example of Procedure of Deleting the Sector from the Flash Memory Start the deletion. FMCS:WE(bit5) Flash memory deletion enabled Deletion command sequence XXAA 1. FFAAAA 2. FF5554 XX55 XX80 3. FFAAAA 4.
Page 626: Temporarily Stopping The Sector Deletion
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.5 Temporarily Stopping the Sector Deletion This section explains the procedure of issuing the sector deletion temporary stop command and temporarily stopping the deletion of a sector from the flash memory. This command can read the data from the sector not being deleted. ■...
Page 627: Restarting The Sector Deletion
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.6.6 Restarting the Sector Deletion This section explains the procedure of issuing the sector deletion restart command and restarting the operation of deleting a sector from the flash memory, which has been temporarily stopped.
Page 628: Flash Security Feature
This is to avoid unnecessary protection during the programming. In order to re-program the once protected flash memory, the chip erase operation should be preformed. For further information, please contact Fujitsu.
Page 629: Programming Example Of 512K Bit Flash Memory
CHAPTER 23 512K / 1024K BIT FLASH MEMORY 23.8 Programming Example of 512K Bit Flash Memory This section presents a programming example for the use of 512K bit flash memory. ■ Programming Example Using 512K Bit Flash Memory NAME FLASHWE TITLE FLASHWE ;--------------------------------------------------------------------------- ;512-KB FLASH Sample program for 512-KB FLASH...
Page 630 CHAPTER 23 512K / 1024K BIT FLASH MEMORY DATA ENDS ;/////////////////////////////////////////////////////////////// ;Main program (SA1) ;/////////////////////////////////////////////////////////////// CODE CSEG START: ;////////////////////////////////////////////////////// ;Initialization ;////////////////////////////////////////////////////// CKSCR,#0BAH ;Set a frequency multiplier of three. RP,#0 A,#!STA_T SSB,A MOVW A,#STA_T MOVW SP,A ROMM,#00H ;Mirror OFF PDR0,#00H ;For error check DDR0,#0FFH PDR1,#00H ;Data input port...
Page 631 CHAPTER 23 512K / 1024K BIT FLASH MEMORY PDR3,#00H ;Switch initialization DDR3,#00H PDR3:0,WAIT1 ;Writing starts if PDR3:0 Hi. WAIT1 ;///////////////////////////////////////////////// ; Write (SA0) ;///////////////////////////////////////////////// A,PDR1 MOVW @RW0+00,A ;PDR1 data is stored in RAM. FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H...
Page 632 CHAPTER 23 512K / 1024K BIT FLASH MEMORY MOVW @RW2+00,#0030H ;Issuing the erase command to the sector to be erased. 6 ; Wait-time check ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// When the "time-limit-exceeded" check flag is set and toggling is on, branches to ERROR. ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 A,#20H...
Page 633 CHAPTER 23 512K / 1024K BIT FLASH MEMORY...
Page 634: Chapter 24 Example Of F
This chapter describes examples of F MC-16LX MB90F462/F462A/F463A connections for serial writing. 24.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard) 24.2 Example of Connection for Serial Writing (When Power Supplied by User) 24.3 Example of Connection for Serial Writing (When Power Supplied from Writer) 24.4 Example of Minimum Connection with Flash Microcontroller...
Page 635: Standard Configuration For Serial On-Board Writing (Fujitsu Standard)
Contact Yokogawa Digital Computer Co., Ltd. for the functionality and operation of the AF200 flash microcontroller programmer and information on the general-purpose common cable (AZ210) and connectors. Table 24.1-1 Pins used for Fujitsu Standard Serial On-board Writing Function Description MD2, MD1, MD0 Mode pin Used to enable write mode for the flash microcomputer programmer.
Page 636 Flash microcontroller programmer/power supply adapter with overseas specification AZ201 RS232C cable for PC/AT AZ210 Standard target probe (a) Length: 1 m FF001 Control module for Fujitsu F MC-16LX flash microcontroller FF001 P2 2 MB PC Card (Option) FF001 P4 4 MB PC Card (Option) For more information, contact the Sales Department, Equipment Business Division, Yokogawa Digital Computer Co., Ltd.
Page 637: Example Of Connection For Serial Writing (When Power Supplied By User)
CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING 24.2 Example of Connection for Serial Writing (When Power Supplied by User) Figure 24.2-1 is an example of serial write connection when power is supplied by the user. MD2=1 and MD0=0 are input from TAUX3 and TMODE respectively in AF200 flash microcontroller programmer.
Page 638 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING • When the user system also uses pins SIN0, SOT0 and SCK0, the control circuit shown below is necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash microcontroller programmer /TICS signal.) •...
Page 639: Example Of Connection For Serial Writing (When Power Supplied From Writer)
CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING 24.3 Example of Connection for Serial Writing (When Power Supplied from Writer) Figure 24.3-1 is an example of serial write connection when power is supplied from the writer. MD2=1 and MD0 are input from TAUX3 and TMODE respectively in AF200 flash microcontroller programmer.
Page 640 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING • When the SIN0, SOT0 and SCK0 pins are also used by the user system, the control circuit shown below is necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash microcontroller /TICS signal.) •...
Page 641: Example Of Minimum Connection With Flash Microcontroller Programmer (When Power Supplied By User)
CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING 24.4 Example of Minimum Connection with Flash Microcontroller Programmer (When Power Supplied by User) Figure 24.4-1 is an example of the minimum connection with the flash microcontroller programmer when power is supplied by the user. Serial write mode: MD2, MD1, MD0 = 110 ■...
Page 642 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING • When the user system also uses the SIN0, SOT0 and SCK0 pins the control circuit shown below is necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller programmer /TICS signal.) •...
Page 643: Example Of Minimum Connection With Flash Microcontroller Programmer (When Power Supplied From Writer)
CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING 24.5 Example of Minimum Connection with Flash Microcontroller Programmer (When Power Supplied from Writer) Figure 24.5-1 is an example of the minimum connection with the flash microcontroller programmer when power is supplied from the writer. ■...
Page 644 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING • When the user system also uses the SIN0, SOT0, SCK0 pins, the control circuit shown below is necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller programmer /TICS signal.) •...
Page 645 CHAPTER 24 EXAMPLE OF F MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING...
Page 646: Appendix
APPENDIX The appendixes contain an I/O map and F MC-16LX instructions description. APPENDIX A I/O MAP APPENDIX B Instructions...
Page 647: Appendix A I/O Map
APPENDIX APPENDIX A I/O MAP Table A-1 lists the addresses assigned to the registers for peripheral functions in the MB90460/465 series. ■ I/O Map Table A-1 I/O Map (1/6) Address Abbreviation Register Byte access Word access Resource name Initial value 000000 XXXXXXXX PDR0...
Page 648 APPENDIX A I/O MAP Table A-1 I/O Map (2/6) Address Abbreviation Register Byte access Word access Resource name Initial value 000024 00000000 SMR1 Serial mode register 1 000025 00000100 SCR1 Serial control register 1 UART1 SIDR1 / Input data register 1 / 000026 XXXXXXXX SODR1...
Page 649 APPENDIX Table A-1 I/O Map (3/6) Address Abbreviation Register Byte access Word access Resource name Initial value 000050 XXXXXXXX TMRR0 16-bit timer register 0 000051 XXXXXXXX 000052 XXXXXXXX TMRR1 16-bit timer register 1 000053 XXXXXXXX 000054 XXXXXXXX Waveform TMRR2 16-bit timer register 2 generator 000055 XXXXXXXX...
Page 650 APPENDIX A I/O MAP Table A-1 I/O Map (4/6) Address Abbreviation Register Byte access Word access Resource name Initial value 000070 XXXXXXXX OCCPB0 / Output compare buffer register / Output compare OCCP0 register 0 000071 XXXXXXXX 000072 XXXXXXXX OCCPB1 / Output compare buffer register / Output compare OCCP1 register 1...
Page 651 APPENDIX Table A-1 I/O Map (5/6) Address Abbreviation Register Byte access Word access Resource name Initial value 0000B0 00000111 ICR00 Interrupt control register 00 0000B1 00000111 ICR01 Interrupt control register 01 0000B2 00000111 ICR02 Interrupt control register 02 0000B3 00000111 ICR03 Interrupt control register 03 0000B4...
Page 652 APPENDIX A I/O MAP Table A-1 I/O Map (6/6) Address Abbreviation Register Byte access Word access Resource name Initial value 003FE0 00000000 Output data buffer register 0 OPDBR0 003FE1 00000000 Output data buffer register 0 003FE2 00000000 Output data buffer register 1 OPDBR1 003FE3 00000000...
Page 653 APPENDIX ● Meaning of abbreviations used for reading and writing R/W:Read and write enabled R:Read-only W:Write-only ● Explanation of initial values 0:The bit is initialized to 0. 1:The bit is initialized to 1. X:The initial value of the bit is undefined. -:The bit is not used.
Page 654: Appendix B Instructions
APPENDIX B Instructions APPENDIX B Instructions APPENDIX B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F MC-16LX Instruction List B.9 Instruction Map...
Page 655: Instruction Types
APPENDIX Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 656: Addressing
APPENDIX B Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 657 APPENDIX ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the (RL1) byte, word, and long word types in order from the None left.
Page 658: Direct Addressing
APPENDIX B Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2 2 3 3...
Page 659 APPENDIX Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6 2 5 3 4 Memory space After execution A 0 7 1 6 2 5 6 4 Memory space...
Page 660 APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.)
Page 661 APPENDIX ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 662 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 663 APPENDIX ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)
Page 664: Indirect Addressing
APPENDIX B Instructions Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 665 APPENDIX Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0 7 1 6 2 5 3 4 Memory space RW1 D 3 0 F...
Page 666 APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.)
Page 667 APPENDIX ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general- purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.)
Page 668 APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 669 APPENDIX Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E × × × × 0 2 0 1 ×...
Page 670 APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB).
Page 671 APPENDIX ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0...
Page 672: Execution Cycle Count
APPENDIX B Instructions Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■...
Page 673 APPENDIX ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in Code Operand each addressing mode Execution cycle count in each addressing mode See the instruction list.
Page 674 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address...
Page 675: Effective Address Field
APPENDIX Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order from the left.
Page 676: How To Read The Instruction List
APPENDIX B Instructions How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Description...
Page 677 APPENDIX Table B.7-1 Description of Items in the Instruction List (2/2) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change S: Set upon instruction execution.
Page 678 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing addr16 Direct addressing addr24...
Page 679: F 2 Mc-16Lx Instruction List
APPENDIX MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. ■ F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) A,dir byte (A) ← (addr16) A,addr16 byte (A) ←...
Page 680 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi) MOVW A,RWi word (A) ← (ear) MOVW A,ear word (A) ←...
Page 681 APPENDIX Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ← (A) + (eam) A,eam 4 + (a) byte (ear) ←...
Page 682 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 2 × (b) byte (eam) ← (eam) + 1 5+(a) byte (ear) ← (ear) - 1 2 × (b) byte (eam) ← (eam) - 1 5+(a) word (ear) ←...
Page 683 APPENDIX Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) DIVU A,eam word (A) / byte (eam)
Page 684 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) A,eam word (A) / byte (eam) quotient →...
Page 685 APPENDIX Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam) A,eam 4+(a) byte (ear) ← (ear) and (A) ear,A 2 ×...
Page 686 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ← (A) or (eam) A,eam 7+(a) long (A) ←...
Page 687 APPENDIX Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← Right rotation with carry RORC byte (A) ← Right rotation with carry ROLC byte (ear) ← Right rotation with carry RORC 2 × (b) byte (eam) ← Right rotation with carry RORC 5+(a) byte (ear) ←...
Page 688 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 BC/BLO rel Branch on (C) = 1 BNC/ Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0...
Page 689 APPENDIX Table B.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9 Branch on byte (eam) not equal to imm8...
Page 690 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (PS) PUSHW (SP) ←...
Page 691 APPENDIX Table B.8-16 21 Bit Operand Instructions Mnemonic Operation byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp 2 × (b) bit (dir:bp)b ← (A) MOVB dir:bp,A 2 × (b) bit (addr16:bp)b ← (A) MOVB addr16:bp,A 2 ×...
Page 692 APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic Operation byte transfer @AH+ ← @AL+, counter = RW0 MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter = RW0 SCEQ / SCEQI byte search @AH- ←...
Page 693: Instruction Map
APPENDIX Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1 Character string...
Page 694 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand Operand code [Basic page map] [Extended page map]* *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 695 APPENDIX Table B.9-2 Basic Page Map...
Page 696 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6C...
Page 697 APPENDIX Table B.9-4 Character String Operation Instruction Map (First Byte = 6E...
Page 698 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6F...
Page 699 APPENDIX Table B.9-6 ea Instruction 1 (First Byte = 70...
Page 700 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71...
Page 701 APPENDIX Table B.9-8 ea Instruction 3 (First Byte = 72...
Page 702 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73...
Page 703 APPENDIX Table B.9-10 ea Instruction 5 (First Byte = 74...
Page 704 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75...
Page 705 APPENDIX Table B.9-12 ea Instruction 7 (First Byte = 76...
Page 706 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77...
Page 707 APPENDIX Table B.9-14 ea Instruction 9 (First Byte = 78...
Page 708 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79...
Page 709 APPENDIX Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A...
Page 710 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B...
Page 711 APPENDIX Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C...
Page 712 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D...
Page 713 APPENDIX Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E...
Page 714 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F...
Page 715 APPENDIX...
Page 716: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 717 INDEX Index Numerics 16-bit Reload Timer Pins ........235 16-bit Reload Timer Registers......236 1024K Bit Flash Memory 16-bit Reload Timer Settings......244 Characteristics of the 512K/1024K Bit Flash Memory Baud Rates determined using the Internal Timer ............588 (16-bit Reload Timer 0) ....... 495 16-bit Free-run TImer Block Diagram of the 16-bit Reload Timer ..
Page 718 INDEX 8/10-bit A/D Converter Pins......546 8/10-bit A/D Converter Registers ...... 548 Block Diagram of the 8/10-bit A/D Converter..544 Accumulator (A) ..........42 Block Diagrams of the 8/10-bit A/D Converter Pins A/D Control Status Register ............546 A/D Control Status Register 0 (ADCS0) .....551 OS Function of the 8/10-bit A/D Converter A/D Control Status Register 1 (ADCS1) .....549 ............
Page 719 INDEX Block Diagram of the Clock Generation Block ..80 Block Diagram of the Delayed Interrupt Generator Bank Addressing Module ..........536 Bank Addressing and Default Space..... 36 Block Diagram of the DTP/external Interrupt Circuit Linear Addressing and Bank Addressing ....33 ............
Page 720 INDEX Circuit Compare Clear Buffer Register DTTI1 Circuit Block Diagram......421 Compare Clear Buffer Register (CPCLRB) ..293 Circuit Timing Diagram Compare Clear Register DTTI1 Circuit Timing Diagram (D1,D0=00 Compare Clear Register (CPCLR)......293 ............422 Compare Clear Register (CPCR) ......388 CKSCR Compare Control Register Configuration of the Clock Selection Register Compare Control Register,Upper Byte...
Page 721 INDEX CPCLRB Procedure for Writing/Deleting the data to the Flash Compare Clear Buffer Register (CPCLRB)..293 Memory ..........588 Procedure of Deleting a Sector ......605 CPCR Compare Clear Register (CPCR)......388 Deletion Operation When the Chip/Sector Deletion Operation is Executed............
Page 722 INDEX Interrupt of the DTP/external Interrupt Circuit and Multi-pulse Generator Interrupts and EI OS..396 OS ..........515 Operation flow of the Extended Intelligent I/O Service Operation of the DTP/external Interrupt Circuit .. 526 OS) ..........145 Setting the DTP/external Interrupt Circuit ..525 Operation of the Extended Intelligent I/O Service Usage Notes on the DTP/external Interrupt Circuit OS) ..........140...
Page 723 Sample Program for 16-bit Free-run Timer..351 Block Diagrams of the External Reset Pin .... 69 Usage Notes on the 16-bit Free-run Timer ..349 Fujitsu Standard Standard Configuration for Fujitsu Standard Serial On-board Writing........ 616 MC-16LX Instruction List MC-16LX Instruction List ......660 Fetch Mode Fetch............
Page 724 INDEX Indirect Specification Addressing by Indirect Specification with a 32-bit Handling Devices ............34 Notes on Handling Devices ......... 24 Initial State Hardware Interrupt Initial State ............579 Hardware Interrupt........... 126 Input Capture Hardware Interrupt Activation......129 16-bit Input Capture ( 4)........281 Hardware Interrupt Operation......
Page 725 INDEX Internal Peripheral Interrupt Mask Function Internal Peripheral Features........3 Interrupt Mask Function ........330 Internal Timer Interrupt Request Interrupt Request Generation ....453, 458 Baud Rates determined using the Internal Timer (16-bit Reload Timer 0) ....... 495 Interrupt Vectors Interrupt Interrupt Causes and Interrupt Vectors/interrupt DTTI0 Interrupt ..........
Page 726 INDEX Measurement Result Measurement Result Data........456 Latch Memory Map Usage Notes on the Delayed Interrupt Request Latch PROM Memory Map........579 ............539 Memory Maps Linear Addressing Memory Maps ............31 Linear Addressing and Bank Addressing ....33 Memory Space Linear Addressing by 24-bit Operand Specification Memory Space ...........29 ............
Page 727 INDEX Operation Mode Selection......... 450 Multi-functional Timer Pins ......286 PWM Mode (PCNTL: MDSE=0)....... 273 Operation of Multi-functional Timer....324 Relationship between Mode Pins and Mode Data Multiple Interrupts ............161 Multiple Interrupts ........... 133 Release of Sleep Mode........99 Multiplier Release of Stop Mode .......
Page 728 INDEX One-shot Position Detection Timing Generated by One-shot Position Detection OPDR Register Write Timing Diagram ) ......418 ) ......402 (OPS2 to OPS0=110 (OPS2 to OPS0=000 Timing Generated by One-shot Position Detection and OPDR Register Write Timing Diagram (OPS2 to Timer Underflow (OPS2 to OPS0 = 111 OPS0=001 ,010...
Page 729 INDEX Output Compare Making Non-overlap Signals by using PPG in Normal 16-bit Output Compare (×6) ......280 Polarity (DTCR0/DTCR1/DTCR2:TMD2 to 16-bit Output Compare Interrupts ...... 321 ) ........345 TMD0=111 16-bit Output Compare Interrupts and EI OS ..321 Making Non-overlap Signals by using RT1/RT3/RT5 16-bit Output Compare Operation ......
Page 730 INDEX PLL Clock Multiplier Operation of Port 5 ...........196 Selection of a PLL Clock Multiplier ....84 Port 5 Configuration .........193 Port 5 Pins ............193 Pointer Port 5 Registers ..........194 Register Bank Pointer (RP) ......... 50 Port 6 Polarity Block Diagram of Port 6 Pins ......199 Making Non-overlap Signals by using PPG in Inverted Functions of Port 6 Registers ......200 Polarity (DTCR0/DTCR1/DTCR2:TMD2 to...
Page 731 INDEX Processing Time Example of Minimum Connection with Flash Microcontroller Programmer (when Power Hardware Interrupt Processing Time....135 Supplied from Writer)......624 Processing Time (one transfer time) of the Extended OS)..... 147 Intelligent I/O Service (EI 16-bit PPG Timer (×3,PPG1 is not present in Processor Status MB90465 Series) ........
Page 732 INDEX PWC Control Status Register Compare Control Register,Upper Byte (OCS1/OCS3/OCS5) ......301 PWC Control Status Register,Upper Byte (PWCSH0/PWCSH1)......439 Condition Code Register (CCR) Configuration..48 Control Status Register (FMCS)......590 PWC control Status Register Delayed Interrupt Generator Module Register (DIRR) PWC control Status Register,Lower Byte ............537 (PWCSL0/PWCSL1)......
Page 733 INDEX ROM Mirroring Function Selection Register Signal Flow Diagram for Reload Timer 0 or Position (ROMM) ..........585 Detection by Setting OPS2 to OPS0 = 100 Serial Control Register (SCR0/SCR1) ....476 or 101 ........... 404 Serial Mode Register (SMR0/SMR1) ....478 Signal Flow Diagram for Reload Timer 0 Underflow Serial Status Register (SSR0/SSR1) ....
Page 734 Serial Mode Register (SMR0/SMR1) ....478 Extended Intelligent I/O Service (EI Serial On-board Writing ............153 Standard Configuration for Fujitsu Standard Serial Sample Program for 16-bit Free-run Timer ..351 On-board Writing ........616 Sample Program for 16-bit Output Compare ..352...
Page 735 INDEX Signal Flow Diagram for Reload Timer 0 or Position Standard Configuration Detection by Setting OPS2 to OPS0 = 100 Standard Configuration for Fujitsu Standard Serial ........... 404 On-board Writing........ 616 or 101 Signal Flow Diagram for Reload Timer 0 Underflow...
Page 736 INDEX Transfer Operation of the Interval Timer Function (Time-base Timer) ......212 Operation of Data Transfer of Output Data Register Operation of the Time-base Timer ..... 215 ............407 Sample Program for the Time-base Timer ..216 transfer Time-base Timer Interrupts....... 211 Processing Time (one transfer time) of the Extended Time-base Timer Interrupts and EI OS ....
Page 737 INDEX OS ..323 Timing Generated by Reload Timer Underflow Waveform Generator Interrupts and EI )......410 Waveform Generator Registers ......292 (OPS2 to OPS0=001 When One-shot Position Detection and Timer Waveform Sequencer Underflow .......... 419 Block Diagram of Waveform Sequencer .... 360 When One-shot Position Detection or Timer Function of Waveform Sequencer......
Page 738 CM44-10120-4E FUJITSU MICROELECTRONICS • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90460/465 Series HARDWARE MANUAL August 2008 the fourth edition FUJITSU MICROELECTRONICS LIMITED Published Business & Media Promotion Dept. Edited...

This manual is also suitable for:

Mb90465 series

Fujitsu MB90460 Series Hardware Manual

Chapter 1 Overview

Chapter 2 Notes on Handling Devices

Chapter 3 Cpu

Chapter 4 Reset

Chapter 5 Clock

Chapter 6 Low Power Consumption Mode

Chapter 7 Interrupt

Chapter 8 Mode Setting

Chapter 9 I/O Port

Chapter 10 Time-Base Timer

Chapter 11 Watchdog Timer

Chapter 12 16-Bit Reload Timer

Chapter 13 16-Bit Ppg Timer

Chapter 14 Multi-Functional Timer

Chapter 15 Multi-Pulse Generator

CHAPTER 16 PWC Timer

Chapter 17 Uart

Chapter 18 Dtp/External Interrupt Circuit

Chapter 19 Delayed Interrupt Generator Module

Chapter 20 8/10-Bit A/D Converter

Chapter 21 Rom Correction Function

Chapter 22 Rom Mirroring Function Selection Module

Chapter 23 512K / 1024K Bit Flash Memory

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Summary of Contents for Fujitsu MB90460 Series