Page 1 FUJITSU SEMICONDUCTOR CM71-10121-3E CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91350A Series HARDWARE MANUAL...
Page 3 Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Page 5 ■ Objectives and Intended Reader The MB91350A series is one of the FR60 family of microcontrollers. The FR60 family of microcontrollers is based on the FR30/40 family of CPUs, which use a 32-bit high-performance RISC CPU as the core CPU.
Page 6 This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations. CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION This chapter describes the serial onboard writing connection (Fujitsu standard) using the AF220/AF210/ AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation.
Page 7 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS This chapter outlines a function that restricts access to data internal RAM and instruction internal RAM. It also explains the configuration and functions of registers and internal RAM operations. APPENDIX This appendix consists of the following parts: I/O map, interrupt vectors, pin state for each CPU state, and the instruction lists.
Page 8 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 Features .............................. 2 Block Diagram ............................ 7 Package Dimensions .......................... 9 Pin Layout ............................11 List of Pin Functions ......................... 13 Input-output Circuit Forms ........................ 27 CHAPTER 2 HANDLING THE DEVICE ................31 Precautions on Handling the Device ....................32 Precautions on Using the Little-Endian Area ..................
Page 10 3.9.2 Reset Sources ..........................96 3.9.3 Reset Sequence .......................... 98 3.9.4 Oscillation Stabilization Wait Time ....................99 3.9.5 Reset Operation Modes ......................102 3.10 Clock Generation Control ....................... 104 3.10.1 PLL Controls ..........................105 3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ............ 106 3.10.3 Clock Distribution ........................
Page 11 6.1.1 Overview of 8/16-bit Up/Down Counters/Timers ............... 247 6.1.2 8/16-bit Up/Down Counters/Timer Registers ................252 6.1.3 Operation of the 8/16-bit Up/Down Counters/Timers ..............259 U-TIMER ............................268 6.2.1 Overview of the U-TIMER ......................269 6.2.2 U-TIMER Registers ........................270 6.2.3 Operation of the U-TIMER ......................
Page 12 10.3 Operation of the External Interrupt and NMI Controller ..............348 CHAPTER 11 REALOS-RELATED HARDWARE ............351 11.1 Delayed Interrupt Module ....................... 352 11.1.1 Overview of the Delayed Interrupt Module ................353 11.1.2 Delayed Interrupt Module Registers ..................354 11.1.3 Operation of the Delayed Interrupt Module ................
Page 13 CHAPTER 15 I C INTERFACE ..................439 15.1 Overview of the I C Interface ......................440 15.2 C Interface Registers ........................444 15.2.1 Bus Status Register (IBSR) ....................... 445 15.2.2 Bus Control Register (IBCR) ..................... 448 15.2.3 Clock Control Register (ICCR) ....................455 15.2.4 10-bit Slave Address Register (ITBA) ..................
Page 14 ........................567 18.1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection ..568 18.2 Pins Used for Fujitsu Standard Serial Onboard Writing ..............569 18.3 Examples of Serial Programming Connection ................570 18.4 System Configuration of Flash Microcontroller Programmer ............572 18.5...
Page 15 Main changes in this edition Page Changes (For details, refer to main body.) Products were changed. (MB91F353A/352A/353A → MB91F353A/351A/352A/353A) (MB91F35 → MB91F353A/351A/352A/353A) (MB91F35A → MB91F353A/351A/352A/353A) (MB91F355A/353A → MB91F353A/F355A/F356B/F357B) (MB91F355A/355A/354A → MB91F355A/355A/354A/F356B/F357B) "flash memories" were changed. (256 KB flash memories → 256K bytes/128K bytes flash memories) (512 KB flash memories →...
Page 16 Page Changes (For details, refer to main body.) 3.1 Memory Space "■ Memory Map" was changed. (For the MB91V350A, a 512K-byte internal ROM area is used as emulation RAM for the MB91355A, F355A, 353A, and F353A memory map. In addi- tion, the instruction internal RAM is extended from 8 KB to 16 KB.
Page 17 Serial Programming Con- internal ROM external bus mode is selected to write." was added.) nection 18.2 Pins Used for Fujitsu "Table 18.2-1 Function of Pins Used for Fujitsu Standard Serial Onboard Writ- Standard Serial Onboard ing" was changed. Writing 18.5 Other Precautionary "●...
Page 19: Chapter 1 Overview
I/O resources and bus control configuration for embedded controllers that require high-performance or high-speed CPU processing. This model is an FR60 family model that is based on the FR30/40 family of CPUs, and offers enhanced bus access. The FR family is a single-chip microcontroller with built-in peripheral resources.
Page 20: Features
CHAPTER 1 OVERVIEW Features This section describes the features of the FR60 family microcontrollers. ■ FR CPU Features • 32-bit RISC, load/store architecture, five stages pipeline • Maximum operating frequency of 50 MHz [PLL used: Oscillation at 12.5 MHz] •...
Page 21 ■ Internal Memory Table 1.1-1 provides details about internal memory. Table 1.1-1 Internal Memory Details Memory MB91V350A MB91F355A MB91F356B MB91F357B MB91355A MB91354A MB91F353A MB91353A MB91352A MB91351A None 512K bytes 256K bytes 512K bytes 512K bytes 384K bytes 512K bytes 512K bytes 384K bytes 384K bytes Stack RAM...
Page 22 CHAPTER 1 OVERVIEW ■ UART • UART full-duplex double buffer • 5 channels, (MB91F353A/351A/352A/353A: 4 channels) • Parity or no parity can be selected. • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. • Built-in timer for dedicated baud rates •...
Page 23 • Supply voltage: 3.3 V (-0.3 V to +0.3 V) *: I C license Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Rights to use, these components in an I C system provided that the system conforms to the I C Standard Specification as defined by Philips.
Page 24 CHAPTER 1 OVERVIEW ■ Comparison of Functions Table 1.1-2 compares the functions of FR60 family microcontrollers. Table 1.1-2 Comparison of Functions: Internal Memory (Products whose Memory Capacity is to be Extended and the Configuration of Memory are Currently under Study.)
Page 25: Block Diagram
Block Diagram Figure 1.2-1 is a block diagram of the MB91F353A/353A/352A/351A. Figure 1.2-2 is a block diagram of the MB91355A/354A/F355A/F356B/F357B. ■ MB91F353A/353A/352A/351A Block Diagram Figure 1.2-1 MB91F353A/353A/352A/351A Block Diagram FR CPU Core DMAC Bit search (5 channels) Stack RAM to 00 ROM/Flash Bus converter to 16...
Page 26 CHAPTER 1 OVERVIEW ■ MB91355A/354A/F355A/F356B/F357B Block Diagram Figure 1.2-2 MB91355A/354A/F355A/F356B/F357B Block Diagram FR CPU Core to 2 DREQ0 to 2 DACK0 DMAC EOP/DSTP to 2 Bit search (5 channels) IOWR IORD Stack RAM to 00 ROM/Flash 512KB Bus converter to 16 (F356B only : 256 KB) External (Instruction execution...
Page 27: Package Dimensions
+.008 .059 –.004 0.10±0.10 (.004±.004) 0 ˚ ~8 ˚ (Stand off) INDEX 0.25(.010) 0.50±0.20 (.020±.008) "A" 0.60±0.15 (.024±.006) LEAD No. 0.50(.020) 0.22±0.05 0.08(.003) (.009±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003 FUJITSU LIMITED F176006S-c-4-6...
Page 28 –.004 INDEX 0~8 ˚ "A" 0.10±0.05 LEAD No. (.004±.002) +0.05 (Stand off) 0.60±0.15 0.22±0.05 0.145 –0.03 0.50(.020) 0.08(.003) (.024±.006) (.009±.002) +.002 .006 –.001 0.25(.010) Dimensions in mm (inches). 2002 FUJITSU LIMITED F120033S-c-4-4 Note: The values in parentheses are reference values.
Page 29: Pin Layout
Pin Layout Figure 1.4-1 , Figure 1.4-2 show the FR60 family pin layouts. ■ Pin Layout of the MB91F355A/354A/355A/F356B/F357B The installed package is FPT-176P-M02. Figure 1.4-1 Pin Layout of the MB91F355A/354A/355A/F356B/F357B PG5/SCK5 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN5/PPG5 PN4/PPG4 PN3/PPG3 PN2/PPG2 PN1/PPG1 PN0/PPG0...
Page 30 CHAPTER 1 OVERVIEW ■ Pin Layout of the MB91F353A/351A/352A/353A The installed package is FPT-120P-M21. Figure 1.4-2 Pin Layout of the MB91F353A/351A/352A/353A PI1/SO0 P20/D16 PI0/SI0 P21/D17 PK7/INT7/ATG P22/D18 PK6/INT6/FRCK P23/D19 PK5/INT5 P24/D20 PK4/INT4 P25/D21 PK3/INT3 P26/D22 PK2/INT2 P27/D23 PK1/INT1 P30/D24 MB91F353A/MB91351A/ PK0/INT0 P31/D25 PM5/SCK7...
Page 31: List Of Pin Functions
List of Pin Functions Table 1.5-1 lists the functions of the pins. Table 1.5-2 lists the power supply and GND pins. See Figure 1.4-1 , Figure 1.4-2 for the pin layouts. ■ List of Pin Functions Table 1.5-1 Pin Functions (1 / 13) Pin number Pin name circuit...
Page 32 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (2 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [OC0] is an output compare output pin. [PO0] is a general-purpose I/O port. This function can be used as a port when output compare output is not used.
Page 33 Table 1.5-1 Pin Functions (3 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SI6] is data input for serial I/O6. Since this input is always used when serial I/O6 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation.
Page 34 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (4 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SI7] is data input for serial I/O7. Since this input is always used when serial I/O7 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation.
Page 35 Table 1.5-1 Pin Functions (5 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SCK7] is clock I/O for serial I/O7. SCK7 This function is valid when clock output from serial I/O7 is allowed or when external shift clock input is used. [ZIN1] is input for the up/down timer.
Page 36 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (6 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [INT6] is external interrupt input. Since this input is always used when the corresponding INT6 external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation.
Page 37 Table 1.5-1 Pin Functions (7 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SCK0] is clock I/O for UART0. SCK0 This function is valid when UART0 clock output is allowed or when external clock input is used. [PI2] is a general-purpose I/O port.
Page 38 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (8 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SI3] is data input for UART3. Since this input is always used when UART3 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation.
Page 39 Table 1.5-1 Pin Functions (9 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [SO5] is data output from serial I/O5. This function is valid when serial I/O5 data output is allowed. [PG4] is a general-purpose I/O port. This function is valid when serial I/O5 data output is not allowed.
Page 40 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (10 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [DEOP2] is DMA external transfer end output. DEOP2 This function is valid when DMA external transfer end output is allowed. [DSTP2] is DMA external transfer stop input.
Page 41 Table 1.5-1 Pin Functions (11 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [DACK1] is DMA external transfer request acceptance output. DACK1 This function is valid when DMA transfer request acceptance output is allowed. [PB4] is a general-purpose I/O port. This function is valid when DMA external transfer request acceptance output is not allowed.
Page 42 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (12 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [CS3] is chip select 3 output. This function is valid when chip select 3 output is allowed. [PA3] is a general-purpose I/O port. This function is valid when chip select 3 output is not allowed.
Page 43 Table 1.5-1 Pin Functions (13 / 13) Pin number Pin name circuit Function 176 pins 120 pins type [WR0] is external bus write strobe output. This function is valid in external bus mode. [P80] is a general-purpose I/O port. This function is valid in single-chip mode. [WR1] is external bus write strobe output.
Page 44 CHAPTER 1 OVERVIEW Table 1.5-2 Power Supply and GND Pins Pin number Pin name Function 176 pins 120 pins 17,35,65,79,93,96,114, 18,40,43,59,76,9 GND pins. Use the same potential for all pins. 136,145,162,175 6,112 18,36,66,80,97,115,142,14 3.3 V power supply pins. Use the same potential 19,44,56,77,95 6,163,176 for all pins.
Page 45: Input-Output Circuit Forms
Input-output Circuit Forms This section describes the I/O circuit types listed in Table 1.6-1 . ■ Input-Output Circuit Types Table 1.6-1 Input-Output Circuit Types (1 / 3) Classification Circuit type Remarks • Oscillation feedback resistor for high- speed operation (main clock oscillation) : About 1 MΩ...
Page 46 CHAPTER 1 OVERVIEW Table 1.6-1 Input-Output Circuit Types (2 / 3) Classification Circuit type Remarks • CMOS level output • CMOS level hysteresis input Pull-up control With standby control With pull-up control Digital output Pull-up resistance = about 50 kΩ (Typ) Digital output = 4 mA Digital input...
Page 47 Table 1.6-1 Input-Output Circuit Types (3 / 3) Classification Circuit type Remarks • CMOS level hysteresis input Digital input • CMOS level hysteresis input With pull-up resistor Pull-up resistance = about 50 kΩ (Typ) Digital input • CMOS level input (flash memory products only) Control signal Mode input...
Page 48 CHAPTER 1 OVERVIEW...
Page 49: Chapter 2 Handling The Device
CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling FR family microcontrollers. 2.1 Precautions on Handling the Device 2.2 Precautions on Using the Little-Endian Area...
Page 50: Precautions On Handling The Device
CHAPTER 2 HANDLING THE DEVICE Precautions on Handling the Device This section contains information on the prevention of latch-ups, pin processing, handling of circuits, input at power-on and so on. ■ Preventing a Latch-up A latch-up can occur if, on a CMOS IC, a voltage higher than V or a voltage lower than V is applied to an input or output pin or a voltage higher than the rating is applied between V...
Page 51 ■ Note for the Case of Using No Subclock When the oscillator is not connect to the X0A,X1A pins, set the X0A pin to the pull-down operation and open the X1A pin. Figure 2.1-2 Setting for the Case of Using No Subclock OPEN MB91350A ■...
Page 52 CHAPTER 2 HANDLING THE DEVICE ■ Pull-up Control The AC specification will not be guaranteed if pull-up resistor is connected to pins that are used as external bus pins. In addition, ports for which pull-up resistor is connected will be disabled in stop mode with HIZ = 1 and for hardware standby.
Page 53 ■ Prefetch When prefetch to an area set as little endian is allowed, restrict access to that area to word (32-bit) access. Access will be incorrect if byte or halfword access is allowed. ■ Accessing I/O Ports Only byte access is supported for port access. ■...
Page 54 CHAPTER 2 HANDLING THE DEVICE ■ Precautions on the Debuggers ● Single-step execution of the RETI instruction In an environment where interrupts frequently occur, only the relevant interrupt processing routines are executed repeatedly during single-step execution. As a result, the main routines and programs that have a low interrupt level will not be executed. (For example, if the RETI is executed in single-step mode with timebase timer interrupts allowed, the break will always be at the beginning of the timebase routine.) For stages in which debugging of the relevant interrupt processing routines is not required, disable the...
Page 55: Precautions On Using The Little-Endian Area
Precautions on Using the Little-Endian Area This section provides precautions on using the little-endian area. ■ Precautions on Using the Little-Endian Area Note the precautions for the following items when using the little-endian area: • C compiler • Assembler • Linker •...
Page 56: C Compiler (Fcc911)
CHAPTER 2 HANDLING THE DEVICE 2.2.1 C Compiler (fcc911) When programming with the C language, operation will be unpredictable if the following operations are executed for the little-endian area: • Mapping of variables with initial values • Structure assignment • Manipulation of arrays other than character-type arrays using character string operation functions •...
Page 57 ■ Structure Assignment When structures are assigned among structures, the compiler selects the optimum transfer method and executes transfer for each byte, halfword, and word. As a result, the correct result will not be obtained if structure assignment spans structure variables assigned to the regular area and structure variables assigned to the little-endian area.
Page 58 CHAPTER 2 HANDLING THE DEVICE ■ Specification of the -K lib Option when Character String Operation Functions are Used When the -K lib option is specified, the compiler expands several character string operation functions inline. Because the compiler selects the optimum processing method at this time, processing may change for each halfword or word.
Page 59: Assembler (Fasm911)
2.2.2 Assembler (fasm911) Note the following points regarding the little-endian area when programming with the FR assembly language: ■ Sections Since the main purpose of the little-endian area is to exchange data with little-endian system CPUs, define the little-endian area as a data section without initial values. Access by the MB91101 will be unpredictable if a code, stack, or data section with initial values is specified in the little-endian area.
Page 60: Linker (Flnk911)
CHAPTER 2 HANDLING THE DEVICE 2.2.3 Linker (flnk911) When creating programs that use the little-endian area, note the following points regarding section mapping at link time: ■ Restriction on Section Types Only data sections without initial values can be mapped in the little-endian area. If a data section with initial values, a stack section, or a code section is mapped in the little-endian area, arithmetic operations such as address decisions will be executed internally in the linker using the big- endian method, causing program operation that is unpredictable.
Page 61: Debuggers (Sim911, Eml911, And Mon911)
2.2.4 Debuggers (sim911, eml911, and mon911) When creating programs that use the little-endian area, note the following points regarding the debuggers: ■ Simulator Debugger There is no memory space specification command for displaying the little-endian area. Therefore, when memory operator commands or instructions that manipulate memory are executed, the area is handled as a big-endian area.
Page 62 CHAPTER 2 HANDLING THE DEVICE...
Page 63: Chapter 3 Cpu And Control Units
CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the core CPU functions of FR family microcontrollers. It covers architecture, specifications, and instructions. 3.1 Memory Space 3.2 Internal Architecture 3.3 Programming Model 3.4 Data Configuration 3.5 Memory Map 3.6 Branch Instructions 3.7 EIT (Exception, Interrupt, and Trap)
Page 64: Memory Space
CHAPTER 3 CPU AND CONTROL UNITS Memory Space FR family microcontrollers have a logical address space of 4 GB (2 addresses). The CPU accesses this space linearly. ■ Direct Addressing Area The areas in the address space listed below are used for input-output. These areas called the direct addressing area.
Page 65 Figure 3.1-2 MB91351A Memory Map Internal ROM External ROM Single-chip mode external bus mode external bus mode 0000 0000 Direct addressing area 0000 0400 Reference to I/O map 0001 0000 Access not Access not Access not allowed allowed allowed 0003 E000 Internal Internal Internal...
Page 66 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.1-4 MB91F356B Memory Map Internal ROM External ROM Single-chip mode external bus mode external bus mode 0000 0000 Direct addressing area 0000 0400 Reference to I/O map 0001 0000 Access not Access not Access not allowed allowed...
Page 67: Internal Architecture
Internal Architecture This section describes the structure of the internal architecture and instructions of the FR family microcontrollers. ■ Overview of Internal Architecture The FR family CPUs employ RISC architecture to create a high-performance core with instructions that provide high-level functions for embedded applications.
Page 68: Internal Architecture
CHAPTER 3 CPU AND CONTROL UNITS 3.2.1 Internal Architecture This section describes the features and structure of the internal architecture. ■ Features of the Internal Architecture • RISC architecture used Basic instruction: One instruction per cycle • 32-bit architecture General-purpose register: 32 bits x 16 •...
Page 69 ■ Structure of the Internal Architecture The FR CPU uses the Harvard architecture, in which the instruction bus and data buses are independent of each other. A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the CPU and peripheral resources.
Page 70 CHAPTER 3 CPU AND CONTROL UNITS ■ CPU The CPU is a compact implementation of the 32-bit RISC FR architecture. Five instruction pipelines are used to execute one instruction per cycle. A pipeline consists of the following stages: Figure 3.2-2 shows the structure of the instruction pipeline. •...
Page 71: Overview Of Instructions
3.2.2 Overview of Instructions The FR supports the general RISC instruction set as well as logical operation, bit manipulation, and direct addressing instructions optimized for embedded applications. For the instruction set, see the APPENDIX D "Instruction Lists". Each instruction is 16-bit long (except for some instructions are 32- or 48-bit long), resulting in superior efficiency of memory use.
Page 72 CHAPTER 3 CPU AND CONTROL UNITS ■ Logical Operation and Bit Manipulation Logical operation instructions perform the AND, OR, and EOR logical operations between general-purpose registers or a general-purpose register and memory (and I/O). Bit manipulation instructions directly manipulate the contents of memory (and I/O). They access memory using general register indirect addressing.
Page 73: Programming Model
Programming Model This section describes the programming model, general-purpose registers, and dedicated registers of the FR family microcontrollers. ■ Basic Programming Model Figure 3.3-1 shows the FR family basic programming model. Figure 3.3-1 Basic Programming Model 32 bits [Initial value] XXXX XXXX General-purpose register...
Page 74: General-Purpose Registers
CHAPTER 3 CPU AND CONTROL UNITS 3.3.1 General-Purpose Registers Registers R0 to R15 are general-purpose registers. They are used as the accumulator for various arithmetic operations and as pointers for memory access. ■ General-Purpose Registers Figure 3.3-2 shows the configuration of the general-purpose registers. Figure 3.3-2 Configuration of General-Purpose Registers 32 bits [Initial value]...
Page 75: Dedicated Registers
3.3.2 Dedicated Registers The dedicated registers are used for specific applications. FR family microcontrollers provide the following dedicated registers: • PS (Program Status) • CCR (Condition Code Register) • SCR (System Condition Code Register) • ILM • PC (Program Counter) •...
Page 76 CHAPTER 3 CPU AND CONTROL UNITS ■ CCR (Condition Code Register) The configuration of the condition code register (CCR) is shown below: [Initial value] --00XXXX [Bit 5] Stack flag This bit specifies the stack pointer to be used as R15. Value Description The system stack pointer (SSP) is used as R15.
Page 77 [Bit 2] Zero flag This bit indicates whether the operation result is "0". Value Description Indicates that the operation result is not "0". Indicates that the operation result is "0". • The initial value after reset is undefined. [Bit 1] Overflow flag This bit indicates whether an overflow has occurred as a result of the operation when the operand using the operation is regarded as an integer represented by its 2's complement.
Page 78 CHAPTER 3 CPU AND CONTROL UNITS ■ SCR (System Condition Code Register) The configuration of the system condition code register (SCR) is shown below: [Initial value] [Bits 10 and 9] Step division flag These bits hold the intermediate data when step division is executed. Do not change these bits during step division.
Page 79 ■ ILM The configuration of the ILM register is shown below: [Initial value] 01111 ILM4 ILM3 ILM2 ILM1 ILM0 The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM is used as a level mask. An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated in this ILM.
Page 80 CHAPTER 3 CPU AND CONTROL UNITS ■ RP (Return Pointer) The configuration of the return pointer (RP) register is shown below: [Initial value] XXXXXXXX The return pointer holds the address returned from a subroutine. When a CALL instruction is executed, the PC value is transferred to this RP. When a RET instruction is executed, the RP contents are transferred to PC.
Page 81 ■ Multiply & Divide Register The configuration of the multiply & divide register is shown below: The multiply and divide registers are 32-bit long. The initial value after reset is undefined. • When multiplication is executed For a 32-bit-by-32-bit multiplication, the 64-bit long operation result is stored in the multiply and divide registers as follows: MDH: High-order 32 bits MDL: Low-order 32 bits...
Page 82: Data Configuration
CHAPTER 3 CPU AND CONTROL UNITS Data Configuration This section describes the data structure in FR family microcontrollers. ■ Bit Ordering FR family microcontrollers use the little endian method for bit ordering. Figure 3.4-1 shows the data configuration in bit ordering. Figure 3.4-1 Data Configuration in Bit Ordering ■...
Page 83 ■ Word Alignment ● Program access An FR family program must be placed at an address that is a multiple of 2. Bit 0 of the PC is set to "0" if the PC is updated when an instruction is executed. Bit 0 can be set to "1"...
Page 84: Memory Map
CHAPTER 3 CPU AND CONTROL UNITS Memory Map This section describes the memory maps of the FR family microcontrollers. ■ Memory Map The address space is 32 bits linear. Figure 3.5-1 shows the memory map. Figure 3.5-1 Memory Map 0000 0000 Byte data 0000 0100 Halfword data...
Page 85: Branch Instructions
Branch Instructions This section describes the branch instructions used in the FR family microcontrollers. ■ Overview of Branch Instructions In the FR family microcontrollers, both operations with and without a delay slot can be specified for the branch instructions.
Page 86: Operations With A Delay Slot
CHAPTER 3 CPU AND CONTROL UNITS 3.6.1 Operations with a Delay Slot This section describes operation when operations with a delay slot are specified for a branch instruction. ■ Branch Instructions with Delay Slot Instructions written as follows perform a branch operation with a delay slot: JMP:D CALL:D label12...
Page 87 [Example] LDI:32 #Label, JMP:D Branch to Label LDI:8 No effect on the branch destination address 2) RP referred by the RET:D instruction is not affected even though RP is updated by the instruction in the delay slot. [Example] RET:D Branch to address defined beforehand in RP No effect on the return operation 3) The flag referred by the Bcc:D rel instruction is not affected by the instruction in the delay slot.
Page 88 CHAPTER 3 CPU AND CONTROL UNITS ● Step trace trap A step trace trap does not occur between the execution of a branch instruction with a delay slot and the delay slot. ● Interrupt NMI An interrupt /NMI is not accepted between the execution of a branch instruction with a delay slot and the delay slot.
Page 89: Operation Without Delay Slot
3.6.2 Operation without Delay Slot This section describes operation when operations without a delay slot are specified for a branch instruction. ■ Instructions not Using a Delay Slot The instructions below execute branch operations without a delay slot: CALL label12 CALL @Ri label9 label9...
Page 90: Eit (Exception, Interrupt, And Trap)
CHAPTER 3 CPU AND CONTROL UNITS EIT (Exception, Interrupt, and Trap) EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program. An exception is an event that occurs related to the execution context. Execution restarts from the instruction that caused the exception.
Page 91: Eit Interrupt Levels
3.7.1 EIT Interrupt Levels The interrupt levels are 0 to 31 and are managed with five bits. ■ EIT Interrupt Levels Table 3.7-1 shows the allocation of the levels. Table 3.7-1 Interrupt Levels Level Binary Decimal 00000 (Reserved for system) 00011 (Reserved for system) If the original ILM value is between 16...
Page 92 CHAPTER 3 CPU AND CONTROL UNITS ■ I Flag A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as Bit 4 of the PS register. Value Description Interrupts prohibited Cleared to "0" if the INT instruction is executed. (Note that a value saved on the stack is the value before it is cleared.) Interrupts permitted The mask processing of an interrupt request is controlled by the value in the ILM...
Page 93: Icr (Interrupt Control Register)
3.7.2 ICR (Interrupt Control Register) The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus.
Page 94 CHAPTER 3 CPU AND CONTROL UNITS Table 3.7-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors Interrupt control register Corresponding interrupt vector Interrupt Number source Number Address Address Hexadecimal Decimal TBR initial value: 000F FC00 Note: See "CHAPTER 9 INTERRUPT CONTROLLER".
Page 95: Ssp (System Stack Pointer)
3.7.3 SSP (System Stack Pointer) SSP (System Stack Pointer) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs. ■ System Stack Pointer (SSP) The configuration of the SSP register is shown below: 31...
Page 96: Interrupt Stack
CHAPTER 3 CPU AND CONTROL UNITS 3.7.4 Interrupt Stack The PC and PS values are saved and restored using the area pointed to by the SSP. After an interrupt, the PC is stored at the address pointed to by the SSP and the PS is stored at the address SSP + 4.
Page 97: Tbr (Table Base Register)
3.7.5 TBR (Table Base Register) TBR (Table Base Register) indicates the beginning address of the vector table for EIT. ■ Table Base Register (TBR) The configuration of the TBR register is shown below: 31..0 [Initial value] 000FFC00 Obtain a vector address by adding to the TBR the offset value predetermined for an EIT cause. The table base register (TBR) is initialized to 000FFC00 by a reset.
Page 98: Eit Vector Table
CHAPTER 3 CPU AND CONTROL UNITS 3.7.6 EIT Vector Table A 1K bytes area from the address indicated in the table base register (TBR) is the vector area for EIT. ■ EIT Vector Table The size for each vector is 4 bytes. The relationship between a vector number and a vector address can be expressed as follows: vctadr = TBR + vctofs = TBR + (3FC H - 4 x vct)
Page 99 Table 3.7-3 Vector Table (2 / 4) Interrupt number Interrupt Default address of Interrupt source Offset level Decimal Hexadecimal 000FFFC8 NMI request (tool) 000FFFC4 Undefined instruction exception Fixed to 000FFFC0 NMI request 15(F 000FFFBC External Interrupt 0 ICR00 000FFFB8 External Interrupt 1 ICR01 000FFFB4 External Interrupt 2...
Page 100 CHAPTER 3 CPU AND CONTROL UNITS Table 3.7-3 Vector Table (3 / 4) Interrupt number Interrupt Default address of Interrupt source Offset level Decimal Hexadecimal 000FFF60 ICR23 Maskable interrupt source 000FFF5C ICR24 Maskable interrupt source 000FFF58 ICR25 Maskable interrupt source 000FFF54 ICR26 Maskable interrupt source...
Page 101 Table 3.7-3 Vector Table (4 / 4) Interrupt number Interrupt Default address of Interrupt source Offset level Decimal Hexadecimal Reserved for system (used in 000FFEF8 REALOS) 000FFEF4 Reserved for system 000FFEF0 Reserved for system 000FFEEC Reserved for system 000FFEE8 Reserved for system 000FFEE4 Reserved for system 000FFEE0...
Page 102: Multiple Eit Processing
CHAPTER 3 CPU AND CONTROL UNITS 3.7.7 Multiple EIT Processing If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause.
Page 103 In consideration of masking other causes after an EIT cause is accepted, the handlers of EIT causes that occur at the same time are executed in the order shown in Table 3.7-5 . Table 3.7-5 Order of Executing EIT Handlers Order of executing handlers Cause Reset...
Page 104: Operations
CHAPTER 3 CPU AND CONTROL UNITS 3.7.8 Operations This section describes the operation of FR family microcontrollers. In the following, it is assumed that the transfer source PC indicates the address of the instruction that detected an EIT cause. In addition, "address of the next instruction" means that the instruction that detected EIT is as follows: •...
Page 105 handler. There is no problem of operation, however, because the same values are set twice for the registers in the CPU. Do not perform any process desiring the contents of the PS resister before the EIT branch in the EIT process routine.
Page 106 CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of Step Trace Trap Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every time an instruction is executed. [Step trace trap detection conditions] 1.
Page 107 ■ No-coprocessor Trap If a coprocessor instruction using a coprocessor that is not installed is executed, a no-coprocessor trap occurs. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5.
Page 108: Operating Modes
CHAPTER 3 CPU AND CONTROL UNITS Operating Modes This section describes the operating modes of the FR family microcontrollers. ■ Overview of Operating Modes The two operating modes are bus mode and access mode. ■ Bus Mode Bus mode refers to a mode in which the operations of internal ROM and the external access function are controlled.
Page 109: Bus Modes
3.8.1 Bus Modes FR family microcontrollers have the three types of bus modes listed below. For details, see Section "3.1 Memory Space". ■ Bus Mode 0 (Single-chip Mode) In this mode, internal I/O, D-bus RAM, F-bus RAM, and F-bus ROM are valid. Access to other areas is invalid.
Page 110: Mode Settings
CHAPTER 3 CPU AND CONTROL UNITS 3.8.2 Mode Settings In the FR family microcontrollers, the mode pins (MD2, MD1, and MD0) and the mode register (MODR) are used to set the operating mode. ■ Mode Pins Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch. Table 3.8-1 lists the specifications related to mode vector fetch.
Page 111 [Detailed explanation of the register] MODR Initial value 000FFFF8 ROMA WTH1 WTH0 XXXXXXXX Operation mode setting bits [Bits 7 to 3] Reserved bits Be sure to set bits 7 to 3 to 00000. If any other value is set for these bits, operation is unpredictable. [Bit 2] ROMA (Internal ROM enable bit) This bit indicates whether to enable internal F-bus RAM and F-bus ROM areas.
Page 112: Reset (Device Initialization)
CHAPTER 3 CPU AND CONTROL UNITS Reset (Device Initialization) This section describes a reset (that is, initialization) of the MB91350A. ■ Overview of Reset (Device Initialization) If a reset source occurs, the device stops all the programs and hardware operations and completely initializes the state.
Page 113: Reset Levels
3.9.1 Reset Levels The reset operations of the MB91350A are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels. ■ Settings Initialization Reset (INIT) The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT). A settings initialization reset (INIT) mainly performs the following initialization: [Items initialized in a settings initialization reset (INIT)] •...
Page 114: Reset Sources
CHAPTER 3 CPU AND CONTROL UNITS 3.9.2 Reset Sources This section describes the reset sources and the reset levels in the MB91350A. To determine reset sources that have occurred in the past, read the RSRR (reset source register). (For more information about registers and flags described in this section, see Section "3.10.5 Block Diagram of Clock Generation Controller"...
Page 115 ■ Software Reset (STCR: SRST Bit Writing) If "0" is written to Bit 4 (SRST bit) of the standby control register (STCR), a software reset request occurs. A software reset request is an operation initialization reset (RST) request. When the request is accepted and a operation initialization reset (RST) is generated, the software reset request is cleared.
Page 116: Reset Sequence
CHAPTER 3 CPU AND CONTROL UNITS 3.9.3 Reset Sequence When a reset source no longer exists, the device starts to execute the reset sequence. A reset sequence has different operations depending on the reset level. This section describes the operations of the reset sequence for different reset levels. ■...
Page 117: Oscillation Stabilization Wait Time
3.9.4 Oscillation Stabilization Wait Time If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized.
Page 118 CHAPTER 3 CPU AND CONTROL UNITS ● Returning from an abnormal state when PLL is selected If, while the device is operating with PLL as the source clock, an abnormal condition occurs in PLL control, the device automatically enters an oscillation stabilization wait time to assure the PLL lock time. When the oscillation stabilization wait time has elapsed, the device enters the normal operating state.
Page 119 Immediately after power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin. To assure the oscillation stabilization wait time of the oscillation circuit immediately after power-on, maintain "L" level input to the INIT pin for the stabilization wait time required by the oscillation circuit. (INIT generated due to the INIT pin initializes the oscillation stabilization wait time setting to the minimum value.) •...
Page 120: Reset Operation Modes
CHAPTER 3 CPU AND CONTROL UNITS 3.9.5 Reset Operation Modes Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with Bit 7 (SYNCR bit) of the timebase counter control register (TBCR).
Page 121 References: • The DMA controller, which stops transfer when a request is accepted, does not delay transition to another state. • If Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) is set to "1", synchronous reset mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode.
Page 122: Clock Generation Control
CHAPTER 3 CPU AND CONTROL UNITS 3.10 Clock Generation Control This section describes clock generation control. ■ Generation of Internal Operating Clock The internal operating clock of the MB91350A model type is generated as follows: • Selection of a source clock: Select a clock supply source. •...
Page 123: Pll Controls
3.10.1 PLL Controls The settings for enabling and disabling operation (oscillation) and for the multiply-by rate can be controlled for the PLL oscillator circuits that correspond to the main clock. Each control is set in the clock source control register (CLKR). This section describes each control.
Page 124: Oscillation Stabilization Wait Time And Pll Lock Wait Time
CHAPTER 3 CPU AND CONTROL UNITS 3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See Section "3.9.4 Oscillation Stabilization Wait Time").
Page 125 Even if there is a lock wait time, the program can be executed if the source clock has been selected to use a PLL. Fujitsu recommends using a timebase timer interrupt for the PLL lock wait time in this case.
Page 126: Clock Distribution
CHAPTER 3 CPU AND CONTROL UNITS 3.10.3 Clock Distribution An operating clock for each function is generated based on the base clock generated from the source clock. A total of three internal operating clocks are provided. A divide- by rate can be set independently for each of them. This section describes these internal operating clocks.
Page 127 ■ Peripheral Clock (CLKP) This clock is used for peripheral circuits and peripheral buses. It is used by the following circuits: • Peripheral bus • Clock controller (only for the bus interface) • Interrupt controller • Peripheral I/O ports • I/O port bus •...
Page 128: Clock Division
CHAPTER 3 CPU AND CONTROL UNITS 3.10.4 Clock Division A divide-by rate from the base clock can be set independently for each of the internal operating clocks. With this function, an optimal operating frequency can be set for each circuit. ■...
Page 129: Block Diagram Of Clock Generation Controller
3.10.5 Block Diagram of Clock Generation Controller Figure 3.10-1 shows a block diagram of the clock generation controller. For a detailed explanation of the registers shown in the figure, see Section "3.10.6 Register of Clock Generation Controller". ■ Block Diagram of Clock Generation Controller Figure 3.10-1 Block Diagram of Clock Generation Controller Peripheral circuit operation stop control register [Clock generator]...
Page 130: Register Of Clock Generation Controller
CHAPTER 3 CPU AND CONTROL UNITS 3.10.6 Register of Clock Generation Controller This section describes the clock generation controller registers. ■ Reset Source Register/Watchdog Timer Control Register (RSRR) The configuration of the reset source and watchdog timer control registers is shown below: Address: 00000480 INIT WDOG...
Page 131 [Bit 13] WDOG (WatchDOG reset occurred) This bit indicates whether a reset (INIT) occurred due to the watchdog timer. Value Explanation No INIT occurred due to the watchdog timer. INIT occurred due to watchdog timer. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. •...
Page 132 CHAPTER 3 CPU AND CONTROL UNITS ■ Standby Control Register (STCR) The configuration of the standby control register is shown below: Address: 00000481 STOP SLEEP SRST OSCD2 OSCD1 Initial value (INIT pin) Initial value (HST pin)* Initial value (INIT) Initial value (RST) * : Occurs only at the same time as initialization due to the INIT pin.
Page 133 [Bit 6] SLEEP (SLEEP mode) This bit specifies entry into sleep mode. If "1" is written to both Bit 7 (STOP bit) and this bit, this bit (STOP) has precedence and the device enters stop mode. Value Explanation Sleep mode not entered (initial value) Sleep mode entered •...
Page 134 CHAPTER 3 CPU AND CONTROL UNITS [Bits 3, 2] OS1, OS0 (Oscillation Stabilization time select) These bits set the oscillation stabilization wait time used after a reset (INIT), return from stop mode, etc. The values written to these bits determine the oscillation stabilization wait time, which can be selected from the four types shown in the following table.
Page 135 ■ Timebase Counter Control Register (TBCR) The configuration of the timebase counter control register is shown below: Address: 00000482 TBIF TBIE TBC2 TBC1 TBC0 SYNCR SYNCS Initial value (INIT) Initial value (RST) The timebase counter control register controls timebase timer interrupts, among other things. This register enables timebase timer interrupts, selects an interrupt interval time, and sets an optional function for the reset operation.
Page 136 CHAPTER 3 CPU AND CONTROL UNITS [Bits 13 to 11] TBC2, TBC1, TBC0 (TimeBasetimer Counting time select) These bits set the interval time of the timebase counter that is used for the timebase timer. The values written to these bits determine the interval time, which can be selected from the eight types listed in the table below: Timer interval If the source oscillation is 12.5 MHz...
Page 137 [Bit 8] SYNCS (SYNChronous Standby enable) This bit is the synchronous standby enable bit. It is used to select one of the following operations, which is to be used if an standby request (either sleep or stop mode request) occurs: (1) Performing a normal standby operation only by writing to the control bit in the STCR register or (2) performing a synchronous standby operation by reading the STCR register after writing to the control bit in the STCR register.
Page 138 CHAPTER 3 CPU AND CONTROL UNITS ■ Clock Source Control Register (CLKR) The configuration of the clock source control register is shown below: Address: 00000484 PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0 Initial value (INIT) Initial value (RST) The clock source control register is used to select the clock source that will be used as the base clock of the system and control the PLL.
Page 139 Main PLL multiply-by PLL1S2 PLL1S1 PLL1S0 rate For source oscillator 12.5 (MHz), φ = 80[ns] (12.5 × 1 (equal) (MHz)) For source oscillator 12.5 (MHz), φ = 40[ns] (25 × 2 (multiplied by 2) (MHz)) For source oscillator 12.5 (MHz), φ = 26[ns] (37.5 ×...
Page 140 CHAPTER 3 CPU AND CONTROL UNITS [Bit 10] PLL1EN (PLL1 ENable) This bit is the enable bit of the main PLL. Rewriting of this bit is not allowed while the main PLL is selected as the clock source. In addition, selecting the main PLL as the clock source is not allowed while this bit is 0 (bits 9 and 8: Determined from the settings of the CLKS1 and CLKS0 bits).
Page 141 [Bits 9, 8] CLKS1, CLKS0 (CLocK source Select) These bits set the clock source that will be used by the FRex core. The values written to these bits determine the clock source, which can be selected from the three types listed in the table below: While bit 9 (CLKS1) is set to "1", the value of bit 8 (CLKS0) cannot be changed.
Page 142 CHAPTER 3 CPU AND CONTROL UNITS ■ Watchdog Reset Postpone Register (WPR) The configuration of the watchdog reset postpone register is shown below: Address: 00000485 Initial value (INIT) Initial value (RST) The watchdog reset postpone register postpones a watchdog reset. If {A5 } and {5A } are written successively to this register, the detection FF for the watchdog timer is...
Page 143 ■ Base Clock Division Setting Register 0 (DIVR0) The configuration of base clock division setting register 0 is shown below: Address: 00000486 Initial value (INIT) Initial value (RST) Base clock division setting register 0 (DIVR0) controls the divide-by rate of an internal clock in relation to the base clock.
Page 144 CHAPTER 3 CPU AND CONTROL UNITS • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. [Bits 11 to 8] P3, P2, P1, P0 (clkP divide select 3 to 0) These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set the clock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP).
Page 145 Note: An upper-limit frequency for the operation is set for each clock. If the combination of source clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding this upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you change the settings when selecting the source clock.
Page 146 CHAPTER 3 CPU AND CONTROL UNITS ■ Oscillation Control Register (OSCCR) The configuration of the oscillation control register is shown below: Address: 0000048A OSCDS1 Initial value (INIT) Initial value (RST) The oscillation control register controls the main clock oscillation during operation of the subclock. [Bit 8] OSCDS1 (OSCillation Disable on Subclock for XIN1) This bit is the stop bit for main clock oscillation while the subclock is selected.
Page 147: Peripheral Circuits Of Clock Controller
3.10.7 Peripheral Circuits of Clock Controller This section describes the peripheral circuit functions of the clock controller. ■ Timebase Counter The clock controller has a 26-bit timebase counter that runs on the system base clock. The timebase counter is used to measure the oscillation stabilization wait time in addition to having the uses listed below (For more information about the oscillation stabilization wait time, see Section "3.9.4 Oscillation Stabilization Wait Time").
Page 148 CHAPTER 3 CPU AND CONTROL UNITS [Suspending the watchdog timer (automatic postponement)] If program operation stops on the CPU, the watchdog reset generation flag is initialized and generation of a watchdog reset is postponed. Stopping of program operation specifically refers to the following statuses: •...
Page 149 [Clearing of the timebase counter due to the device state] All bits of the timebase counter are cleared to "0" at the same time if the device enters one of the following states: • Stop state • Settings initialization reset (INIT) state Especially in the stop state, an interval interrupt of the timebase timer may unintentionally be generated because the timebase counter is used to measure the oscillation stabilization wait time.
Page 150 CHAPTER 3 CPU AND CONTROL UNITS ● Main Clock Oscillation Stabilization Wait Timer (When Subclock Selected) The main clock oscillation stabilization wait timer is a 26-bit timer that counts up in synchronization with the main clock. The operation of this timer is not affected by clock source selection or the clock division. The main clock oscillation stabilization wait timer is used to measure the main clock oscillation stabilization wait time during subclock is operating.
Page 151: Device State Control
3.11 Device State Control This section describes the states of the MB91350A and their control. ■ Overview of Device State Control The MB91350A model type has the following device states: • RUN state (normal operation) • Sleep state • Stop state •...
Page 152: Device States And State Transitions
CHAPTER 3 CPU AND CONTROL UNITS 3.11.1 Device States and State Transitions Figure 3.11-1 shows the state transitions of the device. ■ Device States Figure 3.11-1 Device States Priority of state transition requests INTX pin = 0 (INIT) Settings initialization reset INIT pin = 1 (clearance of INIT state) (INIT) request End of oscillation stabilization wait time...
Page 153 ■ Device Operating States The device operating states of the MB91350A model type are as follows: ● RUN state (Normal Operation) In the RUN state, a program is being executed. All internal clocks are supplied and all circuits are enabled. For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not being accessed.
Page 154 CHAPTER 3 CPU AND CONTROL UNITS ● Oscillation stabilization wait RUN state In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after a return from the stop state. All internal circuits except the clock generation controller (timebase counter and device state controller) are stopped.
Page 155 ● Settings initialization reset (INIT) state In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if a settings initialization reset (INIT) request is accepted or the hardware standby state is ended. Execution of a program on the CPU is stopped and the program counter is initialized. All peripheral circuits are initialized.
Page 156: Low-Power Consumption Modes
CHAPTER 3 CPU AND CONTROL UNITS 3.11.2 Low-power Consumption Modes This section describes the low-power consumption modes and their use in the states of the MB91350A model type. The low-power consumption modes of the MB91350A model type are as follows: •...
Page 157 [Circuits that stop in the sleep state] • Program execution on the CPU • Data cache • Bit search module (enabled if DMA transfer occurs) • Various built-in memory (enabled if DMA transfer occurs) • Internal and external buses (enabled if DMA transfer occurs) [Circuits that do not stop in the sleep state] •...
Page 158 CHAPTER 3 CPU AND CONTROL UNITS ■ Stop Mode If "1" is set for Bit 7 (STOP bit) of the standby control register (STCR), stop mode is initiated and the device enters the stop state. The stop state is maintained until a source for return from the stop state occurs. If "1"...
Page 159 [Sources of return from the stop state] • Generation of a specific valid interrupt request (not requiring a clock) Only the external interrupt input pins (INTn pins), main clock oscillation stabilization wait timer interrupt during main clock oscillation, and watch interrupt during subclock oscillation are enabled. If an interrupt request with an interrupt level other than interrupt disabled (1F ) occurs, stop mode is cleared and the RUN state (normal operation state) is entered.
Page 160 CHAPTER 3 CPU AND CONTROL UNITS ■ Normal and Synchronous Standby Operations If "1" is set for Bit 8 (SYNCS bit) of the timebase counter control register (TBCR), synchronous standby operation is enabled. In this case, simply writing to the STOP bit does not cause a transition to the stop state.
Page 161: Watch Timer
3.12 Watch Timer The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the subclock. The watch timer has an interval timer function to generate interrupts repeatedly at fixed time intervals. ■ Interval Time Table 3.12-1 lists the types of interval times. Select a time interval from one of the following four types. Table 3.12-1 Types of Interval Time Subclock cycle Interval time...
Page 162 CHAPTER 3 CPU AND CONTROL UNITS ● Watch timer The watch timer is a 15-bit incremental counter that uses the subclock source oscillation as the count clock. ● Counter clear circuit The counter clear circuit clears the counter not only when the WCL bit of the WPCR register is set to "0" but also when a reset (INIT) request is generated.
Page 163 [Bit 14] WIE (watch timer interrupt enable) This bit enables or disables the interrupt request output to the CPU. If this bit and the watch interrupt request flag bit are "1", a watch timer interrupt request is outputted. Value Explanation Output of watch timer interrupt request disabled (default value) Output of watch timer interrupt request disabled •...
Page 164 CHAPTER 3 CPU AND CONTROL UNITS ■ Watch Timer Interrupt If the set interval time elapses while the watch timer counter is counting with the subclock, the watch timer interrupt flag (WIF) is set to "1". Then, if the watch timer interrupt enable bit (WIE) has been set to "1" (interrupt output enabled), an interrupt request is outputted to the CPU.
Page 165 ■ Operation of Clock Supply Function The MB91350A uses a timebase counter to secure the oscillation stabilization wait time after INIT or stop mode. On the other hand, the MB91350A uses the watch timer to secure the subclock oscillation stabilization wait time while the main clock is selected as the clock source. This is because the watch timer operates with the subclock regardless of clock source selection.
Page 166 CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of the Watch Timer Figure 3.12-2 shows the counter states at start of watch timer, switching to the subclock, and transition to stop mode during operation with the subclock. Figure 3.12-2 Counter States at Transition to Subclock or Stop Mode Value of counter 4000 Subclock oscillation...
Page 167: Main Clock Oscillation Stabilization Wait Timer
3.13 Main Clock Oscillation Stabilization Wait Timer The main clock oscillation stabilization wait timer is a 23-bit counter that performs incremental counting in synchronization with the main clock. The main clock oscillation stabilization wait timer has an interval timer function to generate interrupts repeatedly at fixed time intervals.
Page 168 CHAPTER 3 CPU AND CONTROL UNITS ● Main clock oscillation stabilization wait timer The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses the main clock source oscillation as the count clock. ● Counter clear circuit The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is set to "0"...
Page 169 [Bit 14] WIE (timer interrupt enable) This bit enables or disables the interrupt request output to the CPU. If this bit and main clock oscillation stabilization interrupt request flag bit are "1", a main clock oscillation stabilization wait timer interrupt request is outputted.
Page 170 CHAPTER 3 CPU AND CONTROL UNITS [Bit 8] WCL (timer clear) Writing "0" to this bit clears the main clock oscillation stabilization wait timer to 0. Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation. •...
Page 171 ■ Operation of Clock Supply Function The MB91350A uses a timebase counter to secure the oscillation stabilization wait time after INIT or stop mode. On the other hand, the MB91350A uses the main clock oscillation stabilization wait timer to secure the main clock oscillation stabilization wait time while the subclock is selected as the clock source.
Page 172 CHAPTER 3 CPU AND CONTROL UNITS ■ Precautions on Using the Main Clock Oscillation Stabilization Wait Timer Use the oscillation stabilization wait time as a reference value because the oscillation cycle is unstable immediately after oscillation is started. No main clock oscillation stabilization interrupt is generated while main clock oscillation is stopped. This is because the counter is stopped when main clock oscillation is stopped.
Page 173: Peripheral Stop Control
3.14 Peripheral Stop Control Peripheral stop control reduces the amount of power consumed by the device by stopping the supply of clocks to peripheral resources that are not being used. Because supplying or stopping a clock can be set for each channel of each peripheral resource, detailed settings appropriate for how resources are used can be made.
Page 174 CHAPTER 3 CPU AND CONTROL UNITS ■ Detailed Explanation of the Peripheral Stop Control Registers The bits of each register are described below. When a bit of RSTOP0 to RSTOP3 (peripheral stop register) is "0", a clock is supplied to the corresponding peripheral resource.
Page 175 ● Peripheral stop register 1 (RSTOP1) Peripheral stop register 1 controls the supply of clock signals to the reload timer and PPG. The configuration of peripheral stop register 1 is shown below: RSTOP1 Initial value at INIT at RST Access 00000495 ST17 ST16...
Page 176 CHAPTER 3 CPU AND CONTROL UNITS ● Peripheral stop register 2 (RSTOP2) Peripheral stop register 2 controls the supply of clock signals to the up/down counter, free-running timer, input capture, and output compare. The configuration of peripheral stop register 2 is shown below: RSTOP2 Initial value at INIT...
Page 177 ● Peripheral stop register 3 (RSTOP3) Peripheral stop register 3 controls the supply of clock signals to the I C interface and the A/D and D/A converters. The configuration of peripheral stop register 3 is shown below: RSTOP3 Initial value at INIT at RST Access...
Page 178 CHAPTER 3 CPU AND CONTROL UNITS • Do not stop resources that are operating or the resources in a DMA transfer. • The peripheral stop registers are not initialized at RST (software reset). (They are initialized at INIT.) To initialize a peripheral stop register after a software reset, use a program to reset the register.
Page 179: Chapter 4 External Bus Interface
CHAPTER 4 EXTERNAL BUS INTERFACE The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface. 4.1 Overview of the External Bus Interface 4.2 External Bus Interface Registers 4.3 Setting Example of the Chip Select Area 4.4 Byte Ordering (Endian) and Bus Access...
Page 180: Overview Of The External Bus Interface
CHAPTER 4 EXTERNAL BUS INTERFACE Overview of the External Bus Interface This section describes the features of the external bus interface. ■ Features of the External Bus Interface • Addresses of up to 32 bits can be output. • Various kinds of external memory (8-bit/16-bit modules) can be directly connected and multiple access timings can be mixed and controlled.
Page 181 • Fly-by transfer by DMA can be performed. • Transfer between memory and I/O can be performed in a single access operation. • The memory wait cycle can be synchronized with the I/O wait cycle in fly-by. • The hold time can be secured by only extending transfer source access. •...
Page 182 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Block Diagram of the External Bus Interface Figure 4.1-1 shows the block diagram of the external bus interface. Figure 4.1-1 Block Diagram of the External Bus Interface Internal address bus Internal data bus External data bus write buffer switch read buffer...
Page 183 ■ I/O Pins The I/O pins are external bus interface pins (Some pins have other uses). Ordinary bus interface A23-A00, D31-D16(AD15-AD00) CS0, CS1, CS2, CS3, AS, SYSCLK, MCLK WR0, WR1, RDY, BRQ, BGRNT Memory interface MCLK DMA interface IOWR, IORD, DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2...
Page 184 CHAPTER 4 EXTERNAL BUS INTERFACE ■ List of External Bus Interface Registers The configuration of the external bus interface registers is shown below: Address 24 23 16 15 00000640 ASR0 ACR0 00000644 ASR1 ACR1 00000648 ASR2 ACR2 0000064C ASR3 ACR3 00000650 ASR4 ACR4...
Page 185: External Bus Interface Registers
External Bus Interface Registers This section describes the registers of the external bus interface. ■ Register Overview of External Bus Interface The following registers are used by the external bus interface: • Area Select Registers (ASR0 to ASR3) • Area Configuration Registers (ACR0 to ACR7) •...
Page 186: Asr0 To Asr3 (Area Select Register)
CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.1 ASR0 to ASR3 (Area Select Register) This section describes the area select registers in detail. ■ Configuration of ASR0 to ASR3 (Area Select Registers) The configuration of ASR0 to ASR3 is shown below: Initial value ASR0 at INIT at RST...
Page 187: Acr0 To Acr7 (Area Configuration Registers)
4.2.2 ACR0 to ACR7 (Area Configuration Registers) This section describes the area configuration registers in detail. ■ Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) The configuration of ACR0 to ACR7 is shown below: Initial value ACR0H INIT Access 00000642...
Page 188 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value ACR6H INIT Access 0000065A ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx xxxxxxxx ACR6L 0000065B SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx xxxxxxxx ACR7H 0000065E ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx xxxxxxxx ACR7L 0000065F...
Page 189 The maximum burst length of the bus width 32-bit area must be set to four bursts or less. Setting of two bursts or less is recommended. Fujitsu recommends setting no more than two bursts for the maximum burst length of the bus width 16-bit area.
Page 190 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 7] SREN (ShaRed ENable) This bit enables or disables sharing of each chip select area by BRQ/BGRNT as indicated in the following table: SREN Sharing enable/disable Disable sharing by BRQ/BGRNT (CS cannot be high impedance) Enable sharing by BRQ/BGRNT (CS can be high impedance) In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the bus is open (during BGRNT=Low output).
Page 191 [Bits 3 to 0] TYP[3:0] (TYPe select) These bits set the access type of each chip select area as indicated in the following table: TYP3 TYP2 TYP1 TYP0 Access type Normal access (asynchronous SRAM, I/O, and single/page) Address data multiplex access (8/16-bit bus width only) Disable WAIT insertion by the RDY pin.
Page 192 CHAPTER 4 EXTERNAL BUS INTERFACE • Bit [5]WREN: Write-enable setting (For this setting only, only a setting that is the same as that of the base setting area is allowed) • Bit [4]LEND: Little endian setting • For the following ACR setting, the setting on the base setting area side is valid: •...
Page 193: Awr0 To Awr3 (Area Wait Register)
4.2.3 AWR0 to AWR3 (Area Wait Register) This section describes the area wait registers in detail. ■ Configuration of AWR0 to AWR3 (Area Wait Registers) The configuration of AWR0 to AWR3 is shown below: Initial value AWR0H at INIT at RST Access 00000660 W08 01111111...
Page 194 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value AWR6H at INIT at RST Access 0000066C W08 xxxxxxxx xxxxxxxx AWR6L 0000066D W00 xxxxxxxx xxxxxxxx AWR7H 0000066E W08 xxxxxxxx xxxxxxxx AWR7L 0000066F W00 xxxxxxxx xxxxxxxx Registers AWR0 to AWR7 specify various kinds of waits for each chip select area. The function of each bit depends on the setting of the access type (bits TYP3 to TYP0) for registers ACR0 to ACR7.
Page 195 [Bits 11 to 8] W11 to 08 (Inpage Access Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the inpage access cycle during burst access. They are valid only for burst cycles. Inpage access wait cycle Auto-wait cycle 0 Auto-wait cycle 1 Auto-wait cycle 15...
Page 196 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 3] W03 (WR0 to WR1 Output Timing Selection) The WR0 to WR1 output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO. The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an ASIC).
Page 197 If no delay is selected by setting "0", assertion of CS0 to 3 starts at the same timing that AS is asserted. If, at this point, successive accesses are made to the same chip select area, assertion of CS0 to CS3 without change between two access operations may continue.
Page 198 CHAPTER 4 EXTERNAL BUS INTERFACE cycle is not inserted. If a hold extension cycle for determining the address is required, set the W02 bit and insert the address → CS delay. Since CS is negated for each access operation, this hold extension cycle is enabled.
Page 199: Iowr0 To Iowr3 (I/O Wait Registers For Dmac)
4.2.4 IOWR0 to IOWR3 (I/O Wait Registers for DMAC) This section describes the I/O wait registers for DMAC in detail. ■ Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) The configuration of IOWR0 to IOWR3 is shown below: IOWR0 Initial value Access...
Page 200 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 30, 22, 14] HLD0,1,2 (Hold Wait Setting: HoLD wait control) These bits control the hold cycle of the read strobe signal on the transfer source access side during DMA fly-by access. HLDn Hold wait setting Do not insert a hold extension cycle.
Page 201: Chip Select Enable Register (Cser)
4.2.5 Chip Select Enable Register (CSER) This section describes the chip select enable register in detail. ■ Configuration of the Chip Select Enable Register (CSER) The configuration of CSER is shown below: Initial value Access at INIT at RST 00000680 CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001 00000001 This register enables or disables each chip select area.
Page 202: Tcr (Terminal And Timing Control Register)
CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.6 TCR (Terminal and Timing Control Register) This section describes the terminal and timing control register in detail. ■ Configuration of the Terminal and Timing Control Register (TCR) The configuration of the TCR is shown below: Initial value Access at INIT...
Page 203 [Bit 5] PCLR (Prefetch buffer all clear: Prefetch buffer CleaR) This bit completely clears the prefetch buffer. PCLR Prefetch buffer control Normal state Clear the prefetch buffer. If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically returns to "0".
Page 204: Setting Example Of The Chip Select Area
CHAPTER 4 EXTERNAL BUS INTERFACE Setting Example of the Chip Select Area In the external bus interface, a total of four chip select areas can be set. The address space of each area can be placed, in units of a minimum of 64K bytes, anywhere in the 4 GB space using ASR0 to 3 (Area Select Registers) and ACR0 to 3 (Area Configuration Registers).
Page 205 Figure 4.3-1 Chip Select Area (Initial value) (Example) 00000000 00000000 00030000 Area 1 64 KB 00040000 Area 0 00100000 Area 3 1 MB 00200000 0FFC0000 Area 2 256 KB 0FFFFFFF FFFFFFFF FFFFFFFF...
Page 206: Byte Ordering (Endian) And Bus Access
CHAPTER 4 EXTERNAL BUS INTERFACE Byte Ordering (Endian) and Bus Access This section describes byte ordering and bus access. ■ Overview of Byte Ordering Except for specific areas, FR family devices enable switching between the big endian and little endian methods for each chip select.
Page 207: Relationship Between Data Bus Widths And Control Signals
4.4.1 Relationship Between Data Bus Widths and Control Signals There is a one-to-one correspondence between the [3:0] control signals and the location of the bytes on the data bus regardless of the data bus width. This section summarizes the location of the bytes on the data bus used for the specified data bus width and the corresponding control signal for each bus mode.
Page 208: Big Endian Bus Access
CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.2 Big Endian Bus Access Except for the CS0 area, the FR family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "0", the chip select area is treated as big endian.
Page 209 Figure 4.4-5 shows the relationship between the internal register and external data bus based on the data format of byte access (when the LDUB and STB instructions are executed). Figure 4.4-5 Byte Access (When LDUB and STB Instructions Executed) a) Output address b) Output address c) Output address d) Output address...
Page 210 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Bus Width of Big Endian Data Figure 4.4-6 shows the data bus width for a bus width of 16 bits. Figure 4.4-6 Data Bus Width for 16-bit Bus Width Internal register External bus Output address low-order digits "00"...
Page 211 ■ External Bus Access For big endian ordering for external bus access, the following items are arranged as illustrated later for bus widths of 16 and 8 bits and for word, halfword, and byte access: • Access byte location • Program address and output address •...
Page 212 CHAPTER 4 EXTERNAL BUS INTERFACE ● 16-bit bus width Figure 4.4-8 shows the access operations for a bus width of 16 bits. Figure 4.4-8 16-bit Bus Width Access (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (1) Output A1/A0="00"...
Page 213 ● 8-bit bus width Figure 4.4-9 shows the access operations for bus width of 8 bits. Figure 4.4-9 8-bit Bus Width Access (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00"...
Page 214 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Example of Connection with External Devices Figure 4.4-10 shows an example of connection between the MB91350A device and external devices. Figure 4.4-10 Connection With External Devices This LSI Note : For 16/8-bit devices, use the data bus on D15 D08 D07 D00 8-bit device 16-bit device...
Page 215: Little Endian Bus Access
4.4.3 Little Endian Bus Access Except for the CS0 area, the FR family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "1", the chip select area is treated as little endian. ■...
Page 216 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Little Endian Data Format Figure 4.4-11 shows the relationship between the internal register and external data bus based on the data format of word access (when the LD and ST instructions are executed). Figure 4.4-11 Word Access (When LD and ST Instructions Executed) Internal External register...
Page 217 ■ Bus Width of Little Endian Data Figure 4.4-14 shows the data bus width for a bus width of 16 bits. Figure 4.4-14 Data Bus Width for 16-bit Bus Width Internal register External bus Output address low-order digits "00" "10" read/write Figure 4.4-15 shows the data bus width for a bus width of 8 bits.
Page 218 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Connection Between the MB91350A Device and the Endian Areas Figure 4.4-16 shows connection between the MB91350A device and endian. Figure 4.4-16 Connection Between MB91350A Device and Endian 16-bit bus width This LSI D16 WR1 D15 D08 D07 D15 D08 D07 big endian area...
Page 219: External Access
4.4.4 External Access This section describes the relationship between the internal register and external data bus based on the byte ordering (endian method) and the bus width. ■ Word Access External access using word access is shown below: Big endian mode Little endian mode 16-bit bus width...
Page 220 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Halfword Access External access using halfword access is shown below: Big endian mode Little endian mode 16-bit bus width Internal External Control Internal External Control terminal terminal terminal terminal address: "0" address: "0" Internal External Control Internal...
Page 221 ■ Byte Access External access using byte access is shown below: Big endian mode Little endian mode 16-bit bus width Internal External Control Internal External Control terminal terminal terminal terminal address: "0" address: "0" Internal External Control Internal External Control terminal terminal terminal...
Page 222 CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode Little endian mode 8-bit bus width Internal External Control Internal External Control terminal terminal terminal terminal address: "0" address: "0" Internal External Control Internal External Control terminal terminal terminal terminal address: "1" address: "1"...
Page 223: Ordinary Bus Interface
Ordinary Bus Interface For an ordinary bus interface, the two clock cycles required for both read access and write access become the basic bus cycle. ■ Basic Timing (For Successive Accesses) (TYP[3:0]=0000 ,AWR=0008 Figure 4.5-1 shows the basic timing for successive accesses. Figure 4.5-1 Basic Timing For Successive Accesses MCLK A[23:0]...
Page 224 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Read → Write Timing (TYP[3:0]=0000 ,AWR=0048 Figure 4.5-2 shows the read → write timing. Figure 4.5-2 Read → Write Timing Read Idle Write MCLK A[23:0] D[31:16] • Setting of the W07/W06 bits of the AWR register enables [0:3] idle cycles to be inserted. •...
Page 225 ■ Write → Write Timing (TYP[3:0]=0000 ,AWR=0018 Figure 4.5-3 shows the write → write timing. Figure 4.5-3 Write → Write Timing Read Write recovery Write MCLK A[23:0] D[31:16] • Setting of the W05/W04 bits of the AWR register enables 0-3 write recovery cycles to be inserted. •...
Page 226 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Auto-Wait Timing (TYP[3:0]=0000 ,AWR=2008 Figure 4.5-4 shows the auto-wait timing. Figure 4.5-4 Auto-Wait Timing Basic cycle Wait cycle MCLK A[23:0] D[31:16] D[31:16] Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set. In Figure 4.5-4 , two auto-wait cycles are inserted, making a total of four cycles for access.
Page 227 ■ External Wait Timing (TYP[3:0]=0001 ,AWR=2008 Figure 4.5-5 shows the external wait timing. Figure 4.5-5 External Wait Timing Basic cycle 2 auto-wait cycles Wait cycle by RDY MCLK A[23:0] D[31:16] D[31:16] Release Wait • Setting "1" for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait cycles to be inserted.
Page 228 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Synchronous Write Enable Output Timing (TYP[3:0]=0000 ,AWR=0000 Figure 4.5-6 shows the synchronous write enable output timing. Figure 4.5-6 Synchronous Write Enable Output Timing MCLK A[23:0] Read D[31:16] Write D[31:16] • If synchronous write enable output is enabled (If the W03 bit of the AWR is "1"), operation is as follows.
Page 229 ■ CS Delay Setting (TYP[3:0]=0000 , AWR=000C Figure 4.5-7 shows setting of a CS delay. Figure 4.5-7 Setting of CS Delay MCLK A[23:0] READ D[31:16] WRITE D[31:16] • If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For successive accesses, a negation period is inserted.
Page 230 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Setting of CS → RD/WR Setup and of RD/WR → CS Hold (TYP[3:0]=0000 ,AWR=000B Figure 4.5-8 shows setting of the CS → RD/WR setup and setting of RD/WR → CS hold. Figure 4.5-8 Setting of CS → RD/WR Setup and RD/WR → CS Hold MCLK A[23:0] CS->RD/WR...
Page 231 ■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = Figure 4.5-9 shows DMA fly-by transfer (I/O → memory). • No wait setting in memory side Figure 4.5-9 DMA Fly-by Transfer (I/O → Memory) I/O wait I/O wait I/O idle...
Page 232 CHAPTER 4 EXTERNAL BUS INTERFACE ■ DMA Fly-by Transfer (Memory → I/O) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = Figure 4.5-10 shows DMA fly-by transfer (memory → I/O). • No wait setting in memory side Figure 4.5-10 DMA Fly-by Transfer (Memory → I/O) I/O wait I/O hold I/O idle...
Page 233: Address/Data Multiplex Interface
Address/data Multiplex Interface This section describes setting of the address/data multiplex interface. ■ Without External Wait (TYP[3:0] = 0100 and AWR = 0008 Figure 4.6-1 shows setting of the address/data multiplex interface when there is no external wait. Figure 4.6-1 Setting of Address/Data Multiplex Interface Without an External Wait MCLK address[23:0] A[23:0]...
Page 234 CHAPTER 4 EXTERNAL BUS INTERFACE As with the normal interface, auto-wait (AWR[15:12]), read → write idle cycle (AWR[7:6]), write • recovery (AWR[5:4]), address → CS delay (AWR[2]), CS → RD/WR setup delay (AWR[1]), and RD/ WR → CS hold delay (AWR[0]) can be set. •...
Page 235 ■ CS → RD/WR Setup (TYP[3:0] =0101 , AWR=100B Figure 4.6-3 shows setting of the CS → RD/WR setup. Figure 4.6-3 Setting of CS → RD/WR Setup MCLK address[23:0] A[23:0] READ D[31:16] address[15:0] data[15:0] WRITE data[15:0] address[15:0] D[31:16] Setting "1" for the CS → RD/WR setup delay (AWR1) enables the multiplex address output cycle to be •...
Page 236: Prefetch Operation
CHAPTER 4 EXTERNAL BUS INTERFACE Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 × 8 bits. If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN bit of the ACR register is set to "1"...
Page 237 ■ Optional Clear and Temporary Stopping of a Prefetch Access Setting "1" for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted by setting the PSUS bit to "0". At this point, the contents of the buffer are retained if no error occurs or a buffer clear such as occurs when the PCLR bit is set does not occur.
Page 238 CHAPTER 4 EXTERNAL BUS INTERFACE Generally, when connecting asynchronous memory to which burst/page access cannot be applied, it is best to set the burst length to "1" (single access). Conversely, when memory whose burst/page access cycle is short is connected, it is better to set the burst length to any value other than "1" (single access). In this case, it is best to make the setting so that 8 bytes (half of the buffer) are read in one read operation according to the bus width.
Page 239 In this case, the external bus is accessed again, but no prefetch access is performed before a new read access occurs. ■ Restrictions on Prefetch-enabled Areas If prefetch to a little endian area is enabled, be sure to access the area using word access. If data read into the prefetch buffer is accessed with any length other than word length, the correct endian conversion is not performed and thus the wrong data will be read.
Page 240: Dma Access Operation
CHAPTER 4 EXTERNAL BUS INTERFACE DMA Access Operation This section explains DMA access operation. ■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = Figure 4.8-1 shows setting of DMA fly-by transfer (I/O → memory). Figure 4.8-1 Setting of DMA Fly-by Transfer (I/O →...
Page 241 • When successive accesses are made within the same chip select area without negating the chip select, neither CS → RD/WR setup delay nor RD/WR → CS hold delay is inserted. • If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1"...
Page 242 CHAPTER 4 EXTERNAL BUS INTERFACE • Setting "1" for the HLD bit of the IOWR0 to 3 registers extends the I/O read cycle by one cycle. • Setting bits WR[1:0] bits of the IOWR0 to 3 registers enables 0-3 write recovery cycles to be inserted. •...
Page 243 ■ 2-Cycle Transfer (The Timing is the Same for Internal RAM → External I/O and RAM and for External I/O and RAM → Internal RAM.) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = 00 Figure 4.8-3 shows setting of 2-cycle transfer. When a wait has not been set on the I/O side Figure 4.8-3 Setting of 2-Cycle Transfer MCLK...
Page 244 CHAPTER 4 EXTERNAL BUS INTERFACE ■ 2-Cycle Transfer (External → I/O) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = 00 Figure 4.8-4 shows setting of 2-cycle transfer (external → I/O). When a wait has not been set on the memory and the I/O side Figure 4.8-4 Setting of 2-Cycle Transfer (External →...
Page 245 ■ 2-Cycle Transfer (I/O → External) (TYP[3:0] = 0000 , AWR = 0008 , and IOWR = 00 Figure 4.8-5 shows setting of 2-cycle transfer (I/O → external). When a wait has not been set on the memory and the I/O side Figure 4.8-5 Setting of 2-Cycle Transfer (I/O →...
Page 246: Bus Arbitration
CHAPTER 4 EXTERNAL BUS INTERFACE Bus Arbitration This section describes the settings for executing bus arbitration. ■ Releasing the Bus Right Figure 4.9-1 shows setting of releasing for the bus right. Figure 4.9-1 Setting of Releasing the Bus Right MCLK A23 to A0 Read D31 to D16...
Page 247 ■ Acquiring the Bus Right Figure 4.9-2 shows setting of acquiring the bus right. Figure 4.9-2 Setting of Acquiring the Bus Right MCLK A23 to A0 D31 to D16 BGRNT 1 cycle • Setting "1" for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed.
Page 248: Procedure For Setting A Register
CHAPTER 4 EXTERNAL BUS INTERFACE 4.10 Procedure for Setting a Register Observe the following rules when setting the external bus interface: ■ Procedure for Setting the External Bus Interface 1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used (0).
Page 249: Chapter 5 I/O Port
CHAPTER 5 I/O PORT This chapter describes the I/O ports and the configuration and functions of registers. 5.1 Overview of the I/O Port 5.2 I/O Port Registers...
Page 250: Overview Of The I/O Port
CHAPTER 5 I/O PORT Overview of the I/O Port This section provides an overview of the I/O port. ■ Basic Block Diagram of the I/O Port The pins of the MB91350A device can be used as I/O ports. To do so, set so that the corresponding pins are not used for I/O with the external bus interface or peripherals.
Page 251 Notes: • Use byte access to access the ports. When ports 0 to A (excluding bit 3 of port 9) are being used as external bus pins, the external bus functions have priority. Therefore, when the ports operate as external bus pins, I/O switching will not occur even though the DDR register is rewritten.
Page 252: I/O Port Registers
CHAPTER 5 I/O PORT I/O Port Registers This section describes the configuration and functions of the I/O port registers. ■ Port Data Registers (PDR) The configuration of the port data registers (PDR) is shown below: PDR2 Initial value Access Address : 00000002 XXXXXXXX PDR3...
Page 253 ■ Data Direction Registers (DDR) The configuration of the data direction registers (DDR) is shown below: DDR2 Initial value Access Address : 00000602 00000000 DDR3 Initial value Access Address : 00000603 00000000 DDR4 Initial value Access Address : 00000604 00000000 DDR5 Initial value Access...
Page 254 CHAPTER 5 I/O PORT ■ Pull-up Control Registers (PCR) The configuration of the pull-up control registers (PCR) is shown below: PCR2 Initial value Access Address: 00000622 00000000 PCR3 Access Initial value Address: 00000623 00000000 PCR4 Initial value Access Address: 00000624 00000000 PCR5 Access...
Page 255 ■ Port Function Registers (PFR) The configuration of the port function registers (PFR) is shown below: PFR6 Initial value Access Address : 00000616 *A23E *A22E *A21E A20E A19E A18E A17E A16E 11111111 PFR8 Initial value Access WR1XE BRQE Address : 00000618 --1--0-- PFR9 Initial value...
Page 256 CHAPTER 5 I/O PORT ■ Initial Values and Functions of the Port Function Registers (PFRs) Table 5.2-1 lists the initial values and functions of the port function registers (PFRs). When the registers are used in single-chip mode, the external bus functions of PFR6, 8, 9, A, B1, B2, and C cannot be used.
Page 257 Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (2 / 7) Register name Bit name Function PFR9(ASXE) ASXE General-purpose port (initial value) [P94/AS] Set when using address strobe output. PFRA(CS0XE to CS3XE) CS0XE General-purpose port [PA0/CS0 to PA3/CS3] CS0 output (initial value) CS1XE General-purpose port...
Page 258 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (3 / 7) Register name Bit name Function PFRB1(AK12,AK11,AK10) AK12,AK11,AK10* 0,0,0 General-purpose port (initial value) [PB4/DACK1]* DACK1, DEOP1 output (FR30 compatible for fly-by 0,0,1 transfer) DACK1, DEOP1 output (FR30 compatible for 2- 0,1,0...
Page 259 Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (4 / 7) Register name Bit name Function PFRC(AK22,AK21,AK20) AK22,AK21,AK20* 0,0,0 General-purpose port (initial value) [PC1/DACK2]* DACK2, DEOP2 output (FR30 compatible for fly-by 0,0,1 transfer) DACK2, DEOP2 output (FR30 compatible for 2- 0,1,0 cycle transfer RD timing) DACK2, DEOP2 output (FR30 compatible for 2-...
Page 260 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (5 / 7) Register name Bit name Function PFRH(SOE3) SOE3 General-purpose port (initial value) [PH4/SO3] S03 output PFRH(SCE3) SCE3 General-purpose port (initial value) [PH5/SCK3] SCK3 output PFRI(SOE0) SOE0...
Page 261 Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (6 / 7) Register name Bit name Function PFRN(PGE0 to 7) PGE0 General-purpose port (initial value) [PN0/PPG0 to PN7/PPG7]* PPG0 output PGE1* General-purpose port (initial value) PPG1 output PGE2 General-purpose port (initial value) PPG2 output...
Page 262 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (7 / 7) Register name Bit name Function PFRP(TOE0 to TOE3) TOE0 General-purpose port (initial value) [PP0/TOT0 to PP3/TOT3]* TOT0 output TOE1 General-purpose port (initial value) TOT1 output TOE2 General-purpose port (initial value)
Page 263: 8/16-Bit Up/Down Counters/Timer And U-Timers
CHAPTER 6 8/16-bit Up/Down Counters/ Timer and U-Timers This chapter describes the overview of the 8/16-bit up/ down counters/timers and the U-TIMER, the configuration and functions of registers, and 8/16-bit up/ down counter/timer and U-TIMER operation. 6.1 8/16-bit Up/Down Counters/Timers 6.2 U-TIMER...
Page 264: 8/16-Bit Up/Down Counters/Timers
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 8/16-bit Up/Down Counters/Timers This section describes the overview of the 8/16-bit up/down counters/timers, the configuration and functions of registers, and counter/timer operation. ■ Overview of the 8/16-bit Up/Down Counters/Timers The 8/16-bit up/down counters/timers consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and control circuits.
Page 265: Overview Of 8/16-Bit Up/Down Counters/Timers
6.1.1 Overview of 8/16-bit Up/Down Counters/Timers The 8/16-bit up/down counters/timers consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits. ■ Characteristics of the 8/16-bit Up/Down Counters/Timers • With the 8-bit count register, counting can be performed in a range between 0 and 255 (decimal numbers).
Page 266 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers Compare and reload function (compare interrupt request output, counter clearing, underflow interrupt request output, and reloading) Compare and reload disabled • With the count direction flag, the counting direction immediately before the current count can be identified.
Page 267 ● Counter status register (CSR) The bit configuration of the counter status register (CSR) is shown below. Counter status register (channel 0, 1) Address : 0000B7 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 (CSR0, CSR1) 0000BB ● Counter control register (CCRL) The bit configuration of the counter control register (CCRL) is shown below.
Page 268 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0) Figure 6.1-1 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 0). Figure 6.1-1 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0) Data bus 8 bits To channel 1...
Page 269 ■ Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1) Figure 6.1-2 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 1). Figure 6.1-2 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1) Data bus 8 bits RCR1 (Reload/ CGE1 CGE0 CGSC compare register 1) Control...
Page 270: 8/16-Bit Up/Down Counters/Timer Registers
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.1.2 8/16-bit Up/Down Counters/Timer Registers This section describes the configuration and functions of the registers used by the 8/ 16-bit up/down counters/timers. ■ Counter Control Register High/Low ch0 (CCR H/L ch0) The bit configuration of the counter control register high/low (ch0) (CCRH/L ch0) is shown below. Initial value Address : 0000B4 M16E CDCF...
Page 271 [Bit 13] CFIE: Count direction change interrupt enable bit This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count direction is changed at least once during counting. CFIE Direction change interrupt output Disables direction change interrupt output (initial value).
Page 272 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bit 6] CTUT: Counter write bit This bit transfers data from RCR to UDCR. When this bit is set to "1", data is transferred from RCR to UDCR. Writing "0" to this bit has no effect. The read value is always "0". Do not set this bit to "1"...
Page 273 [Bits 1 and 0] CGE1 and CGE0: Counter clear/gate edge selection bit This bit selects the detection edge/level of the external pin ZIN. When counter clear function When gate function is CGE1 CGE0 is selected selected Disables edge detection (initial Disables level detection (count value).
Page 274 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ Counter Control Register High/Low ch1 (CCR H/L ch1) The bit configuration of the counter control register high/low (ch1) (CCRH/L ch1) is shown below. Initial value Address : 0000B8 Reserved CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 00000000...
Page 275 [Bit 5] UDIE: Overflow/underflow interrupt output control bit This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF is set (when overflow or underflow occurs). UDIE Overflow/underflow interrupt output Disables overflow/underflow output (initial value). Enables overflow/underflow output. [Bit 4] CMPF: Compare detection flag This flag indicates that the comparison result of the UDCR value and RCR value is that the values are equal.
Page 276 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bits 1 and 0] UDF1 and UDF0: Up/down flag These bits indicate the type of a counting operation (up or down) immediately preceding the current operation. Only reading is allowed. No writing is allowed. UDF1 UDF0 Detection edge...
Page 277: Operation Of The 8/16-Bit Up/Down Counters/Timers
6.1.3 Operation of the 8/16-bit Up/Down Counters/Timers This section describes the 8/16-bit up/down counter/timer operation ■ Selecting Counting Mode The 8/16-bit up/down counters/timers have four counting modes. The CMS1 and CMS0 bits of the CCR register are used to select the counting modes. Table 6.1-1 lists the values of the CMS1 and CMS0 bits and corresponding counting modes.
Page 278 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers For the phase difference between AIN pin input and BIN pin input in two multiplication or four multiplication mode, count up if the AIN is faster, and count down if the BIN is faster. In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period between the rising and falling edges of the BIN pin.
Page 279 ■ Reload and Compare Functions The 8/16-bit up/down counters/timers have reload and compare clear functions, which can be combined for processing. Table 6.1-3 presents examples of selecting the reload and compare clear functions. Table 6.1-3 Selecting the Reload and Compare Clear Functions RLDE, UCRE Reload/compare function Disables clear by reload/compare (initial value).
Page 280 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ● When the compare clear function is enabled The compare clear function can be used in all modes other than timer mode. When the compare function is started, if the value of RCR and the value of UDCR match, CMPF is set and an interrupt request is generated.
Page 281 Figure 6.1-7 Overview of the Operation when the Reload and Compare Functions are Started at the Same Time Compare match Compare match Reload Reload Reload Compare match Counter clear Counter clear Underflow Underflow Underflow Counter clear An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt outputs can be enabled separately.
Page 282 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers Figure 6.1-9 Timing of UDCR Clearing when Counting is Stopped UDCR 0065 0066 0000 Clear event Count clock Count enable Enable (counting permitted) Disable (counting prohibited) • If reloading or clearing occurs while the counter is stopped, reload and clear are performed when the event occurs (the figure shows the state when 080 is reloaded).
Page 283 ● Count clear/gate function The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of the CCR register. When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the CCRL register can control which edge input of the ZIN pin to use for clearing the counter.
Page 284 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers the direction to which counting is changed can be determined. However, note that when the period of direction change is short and multiple direction changes are performed in succession, the direction that the flag indicates after the direction change may return to the original direction so that it appears as if the counting direction has not changed at all in between.
Page 285 ■ Interrupt Generation Timing Table 6.1-7 shows the timing at which interrupts are generated. Table 6.1-7 Interrupt Generation Timing Interrupt flag Flag setting interrupt Reloading Clearing Count direction An interrupt is generated change flag simultaneously with setting of (CDCF) the flag when counting starts immediately after the counting direction is changed.
Page 286: U-Timer
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers U-TIMER This section describes the overview of the U-TIMER, the configuration and functions of registers, and U-TIMER operation. ■ Overview of the U-TIMER The U-TIMER is a 16-bit timer that is used to generate the baud rate for the UART. A baud rate can be specified by a combination of a chip operating frequency and U-TIMER reload value.
Page 287: Overview Of The U-Timer
6.2.1 Overview of the U-TIMER The MB91F355A/355A/354A/F356B/F357B have five built-in U-TIMER channels. The MB91F353A/351A/352A/353A have four built-in U-TIMER channels. ■ U-TIMER Registers The U-TIMER registers are shown below. UTIM UTIMR UTIMC (R/W) ■ Block Diagram of the U-TIMER Figure 6.2-1 shows the block diagram of the U-TIMER. Figure 6.2-1 Block Diagram of the U-TIMER UTIMR (reload register) load...
Page 288: U-Timer Registers
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.2.2 U-TIMER Registers This section describes the configuration and functions of the registers used by the U- TIMER. ■ U-TIMER Registers (UTIM) The bit configuration of the U-TIMER register (UTIM) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4.
Page 289 ■ Reload Register (UTIMR) The bit configuration of the reload register (UTIMR) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4. UTIMR ........ch0 Address : 00000064 ch1 Address : 0000006C ch2 Address : 00000074 Access ch3 Address : 000000C4 Initial value ch4 Address : 000000CC UTIMR is a register that stores the value to be reloaded into UTIM if UTIM underflows.
Page 290 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ U-TIMER Control Register (UTIMC) The bit configuration of the U-TIMER control register (UTIMC) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4. UTIMC ch0 Address : 00000067 UCC1 UTIE UNDR CLKS UTST UTCR ch1 Address : 0000006F...
Page 291 This bit is the interrupt enable bit for a U-TIMER underflow. UTIE Operation Interrupt disabled (initial value) Interrupt enabled [Bit 3] UNDR (UNDeR flow flag) This bit is a flag indicating that an underflow has occurred. The UNDR bit is cleared at reset and when "0"...
Page 292 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bit 0] UTCR (U-TIMER CleaR) Writing "0" to UTCR clears the U-TIMER to 0000 (also clears the f.f. to "0"). The read value is always "1". Notes: • In the stop state, assert the start bit UTST (started) to automatically reload data. •...
Page 293: Operation Of The U-Timer
6.2.3 Operation of the U-TIMER This section describes the U-TIMER operation. ■ Calculation of Baud Rate The UART uses the underflow flip-flop (f.f. in the block diagram shown in Figure 6.2-1 ) of the corresponding U-TIMER (from U-TIMER0 to UART0, from U-TIMER1 to UART1, from U-TIMER2 to UART2, from U-TIMER3 to UART3, or from U-TIMER4 to UART4) as the clock source for baud rates.
Page 294 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers...
Page 295 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER This chapter describes the overview of the 16-bit free- running and 16-bit reload timers, the configuration and functions of registers, and timer operation. 7.1 16-bit Free-Running Timer 7.2 16-bit Reload Timer...
Page 296: Chapter 7 16-Bit Free-Running Timer And 16-Bit Reload Timer
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 16-bit Free-Running Timer This section describes the overview of the 16-bit free-running timer, the configuration and functions of registers, and timer operation. ■ Overview of the 16-bit Free-running Timer The count value of the 16-bit free-running timer is used as the base time (of the base timer) for the output compare and input capture operations.
Page 297: Structure Of The 16-Bit Free-Running Timer
7.1.1 Structure of the 16-bit Free-Running Timer The 16-bit free-running timer consists of a 16-bit up counter and a control status register. • One of four count clocks can be selected. • An interrupt can be generated for a counter overflow. •...
Page 298: 16-Bit Free-Running Timer Registers
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.1.2 16-bit Free-Running Timer Registers This section describes the configuration and functions of the registers used by the 16- bit free-running timer. ■ Timer Data Register (TCDT) The timer data register is used to read the count value of the 16-bit free-running timer. The bit configuration of the timer data register (TCDT) is shown below.
Page 299 ■ Timer Control Status Register (TCCS) The bit configuration of the timer control status register (TCCS) is shown below. TCCS Address: 0000D7 ECLK IVFE STOP MODE CLK1 CLK0 Initial value [Bit 7] ECLK This bit is used to switch the count clock source for the 16-bit free-running timer between internal and external sources.
Page 300 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER [Bit 5] IVFE This bit is the interrupt enable bit for the 16-bit free-running timer. An interrupt is generated when the IVFE bit is "1" and the interrupt flag (bit 6 [IVF]) is set to "1". IVFE Interrupt enable Interrupts disabled (initial value)
Page 301 [Bit 2] CLR This bit is used to initialize the value of the 16-bit free-running timer to 0000 during timer operation. Writing "1" to the CLR bit initializes the counter to 0000 Writing "0" to the CLR bit is ignored. The value read from the CLR bit is always 0. Flag meaning Invalid (initial value) Initialization of counter value to 0000...
Page 302: Operation Of The 16-Bit Free-Running Timer
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.1.3 Operation of the 16-bit Free-Running Timer The 16-bit free-running timer starts counting from counter value 0000 after a reset. This counter value is used as the reference time for 16-bit output compare and 16-bit input capture operation.
Page 303 ■ Timing of Clearing of the 16-bit Free-running Timer The counter is cleared by a reset or by software or on a match with the compare clear register. Clearing of the counter by a reset or by software is performed at the same time that the clearing occurs. However, for clearing on a match with the compare clear register 0, the counter is cleared synchronized with the count timing.
Page 304: 16-Bit Reload Timer
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 16-bit Reload Timer This section describes the overview of the 16-bit reload timer, the configuration and functions of registers, and timer operation. ■ Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an internal count, a prescaler for clock generation, and a control register.
Page 305: Structure Of The 16-Bit Reload Timer
7.2.1 Structure of the 16-bit Reload Timer The clock source can be selected from three internal clocks (machine clocks divided by 2, 8, and 32. However, only ch3 can be selected up to machine clocks divided by 64 and 128.) and external event. •...
Page 306 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ■ Block Diagram of the 16-bit Reload Timer Figure 7.2-1 is a block diagram of the 16-bit reload timer. Figure 7.2-1 Block Diagram of the 16-bit Reload Timer 16-bit reload register (TMRLR) Reload 16-bit down counter (TMR) RELD...
Page 307: 16-Bit Reload Timer Register
7.2.2 16-bit Reload Timer Register This section describes the configuration and functions of the registers used by the 16- bit reload timer. ■ Control Status Register (TMCSR) The bit configuration of the control status register (TMCSR) is shown below. TMCSR Initial value Address : 00004E ----0000 00000000...
Page 308 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER [Bits 9, 8, 7] Reserved These bits are reserved. Be sure to set these bits to "0". [Bit 6] (Reserved) This bit is unused. The read value is always "0". [Bit 5] OUTL This bit sets the output level of the external timer.
Page 309 ■ 16-bit Timer Register (TMR) The bit configuration of the 16-bit timer register (TMR) is shown below. 0 Initial value Address : 00004A XXXX 000052 00005A 0000AA The 16-bit timer register is used to read the count value of the 16-bit timer. The initial value of this register is undefined.
Page 310: Operation Of The 16-Bit Reload Register
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.2.3 Operation of the 16-bit Reload Register This section describes operation of the 16-bit reload register. ■ Clock Operation If the timer operates with a divide-by clock of the clock, one of the clocks generated by dividing the machine clock by 2, 8, or 32 can be selected as the count source.
Page 311 ■ Underflow Operation An underflow is an event in which the counter value changes from 0000 to FFFF . Thus, an underflow occurs at the count of [Reload register setting value + 1]. If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of the reload register are loaded into the counter and the count operation is continued.
Page 312 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ■ Output Pin Function The TOT (0-3) output pin provides a toggle output that is inverted by an underflow in reload mode and a pulse output that indicates that counting is in progress in one-shot mode. The output polarity can be set using the OUTL bit of the register.
Page 313 ■ Operating States of the Counter The counter state is determined by the CNTE bit of the control register and the internal signal WAIT. The counter states that can be set include the stop state (STOP state; when CNTE = 0 and WAIT = 1), the startup trigger wait state (WAIT state;...
Page 314 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER...
Page 315: Chapter 8 Programmable Pulse Generator (Ppg) Timer
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the register configuration and functions and the timer operations. 8.1 Overview of the PPG Timer 8.2 PPG Timer Registers 8.3 Operation of the PPG Timer...
Page 316: Overview Of The Ppg Timer
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER Overview of the PPG Timer The programmable pulse generator (PPG) efficiently outputs highly accurate PWM waveforms. The MB91F355A/355A/354A/F356B/F357B have six built-in PPG timer channels. The MB91F353A/351A/352A/353A have three built-in PPG timer channels. ■ Characteristics of PPG Timer •...
Page 317 ■ Registers of the PPG Timer Figure 8.1-1 shows the registers of the PPG timer. Figure 8.1-1 Registers of the PPG Timer Address 0 Access 00000118 GCN10 R/W General Control Register 10 0000011B GCN20 R/W General Control Register 20 00000120 PTMR0 ch0 timer register 00000122...
Page 318 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ■ Block Diagram of the PPG Timer (Overall Configuration and One Channel) Figure 8.1-2 shows the overall block diagram of the PPG timer. Figure 8.1-2 Block Diagram of the PPG Timer (Overall Configuration) 16-bit reload TRG input PPG0...
Page 319 Figure 8.1-3 shows a block diagram of one PPG timer channel. Figure 8.1-3 Block Diagram of the PPG Timer (One Channel) PCRS PDUT Prescaler Load 16-bit 1/16 down counter Start Borrow 1/64 PPG mask PPG output Peripheral clock Reverse bit Enable Interrupt select...
Page 320: Ppg Timer Registers
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER PPG Timer Registers This section describes the configuration and functions of the registers used by the PPG timer. ■ PPG Timer Registers The PPG timer uses the following six types of registers: • Control status register •...
Page 321: Control Status Register
8.2.1 Control Status Register On the MB91F353A/351A/352A/353A, setting of data in the control status registers for ch1, ch3, and ch5 is invalid. ■ Configurations of Control Status Registers The configurations of the control status registers are shown below. PCNH Address : ch0 000126 CNTE STGR MDSE RTRG...
Page 322 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bit 13] MDSE (Mode Select) This bit is used to select either the PWM mode in which continuous pulses are output or the one-shot mode in which a single pulse is output. Value Meaning PWM mode (initial value) One-shot mode...
Page 323 [Bit 8] (Unused bit) [Bits 7 and 6] EGS1 and EGS0 (Trigger Input Edge Select Bit) These bits are used to select an effective edge for the activation cause selected in general control register 1. Regardless of the mode that is selected, writing "1" to the bit of a software trigger enables the software trigger.
Page 324 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bit 0] OSEL: PPG Output Polarity Specification Bit This bit sets the polarity of the PPG output. The table below lists the polarity settings that can be specified by combinations of the OSEL bit and bit 9 (PGMS bit).
Page 325: Ppg Cycle Setting Register (Pcsr)
8.2.2 PPG Cycle Setting Register (PCSR) The PPG cycle setting register (PCSR) is a register with a buffer for setting a cycle. On the MB91F353A/351A/352A/353A, setting of data in the PPG cycle setting registers for ch1, ch3, and ch5 is invalid. ■...
Page 326: Ppg Duty Setting Register (Pdut)
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.2.3 PPG Duty Setting Register (PDUT) The PPG duty setting register (PDUT) is a register that has a buffer for setting the duty. On the MB91F353A/351A/352A/353A, setting of data in the PPG duty setting registers for ch1, ch3, and ch5 is invalid.
Page 327: Ppg Timer Register (Ptmr)
8.2.4 PPG Timer Register (PTMR) The PPG timer register (PTMR) is a register used to read the value of the 16-bit down counter. On the MB91F353A/351A/352A/353A, setting of data in the PPG timer registers for ch1, ch3, and ch5 is invalid. ■...
Page 328: General Control Register 10
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.2.5 General Control Register 10 General control register 10 is used to select the source of trigger input for the PPG timer. ■ Configuration of General Control Register 10 The configuration of general control register 10 is shown below. GCN10 Address: 000118 TSEL33:30...
Page 329 [Bits 11 to 8] TSEL23 to TSEL20: ch2 trigger input selection bits TSEL23 to 20 ch2 trigger input EN0 bit of GCN2 EN1 bit of GCN2 EN2 bit of GCN2 (initial value) EN3 bit of GCN2 16-bit reload timer ch0 16-bit reload timer ch1 ×...
Page 330 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bits 3 to 0] TSEL03 to TSEL00: ch0 trigger input selection bits TSEL03 to 00 ch0 trigger input EN0 bit of GCN2 (initial value) EN1 bit of GCN2 EN2 bit of GCN2 EN3 bit of GCN2 16-bit reload timer ch0 16-bit reload timer ch1 ×...
Page 331: General Control Register 20
8.2.6 General Control Register 20 General control register 20 is used to generate a start trigger by the software. ■ Configuration of General Control Register 20 The configuration of general control register 20 is shown below. GCN20 Address : 00011B R/W <-- Attribute <-- Initial value General control register 20 does not have functions corresponding to PPG timer channels 4 and 5.
Page 332: Operation Of The Ppg Timer
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER Operation of the PPG Timer This section describes the PPG timer operation. ■ Precautions If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation becomes ineffective.
Page 333: Timing Charts For Pwm Operation
8.3.1 Timing Charts for PWM Operation This section describes the timing charts for PWM operation. ■ When Reactivation is Disabled Figure 8.3-1 shows the timing chart for PWM operation when reactivation is disabled. Figure 8.3-1 Timing Chart for PWM Operation with Reactivation Disabled Rising edge detection Trigger ignored Start...
Page 334 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ■ When Reactivation is Enabled Figure 8.3-2 shows the timing chart for PWM operation when reactivation is enabled. Figure 8.3-2 Timing Chart for PWM Operation with Reactivation Enabled Rising edge detection Trigger restarted Start Trigger (1) = T (n+1) ms...
Page 335: Timing Charts For One-Shot Operation
8.3.2 Timing Charts for One-Shot Operation This section describes the timing charts for one-shot operation. ■ When Reactivation is Disabled Figure 8.3-3 shows the timing chart for one-shot operation when reactivation is disabled. Figure 8.3-3 Timing Chart for One-shot Operation with Reactivation Disabled Rising edge detection Trigger ignored Start...
Page 336: Interrupt Sources And Timing Chart (With Ppg Output Set For Ordinary Polarity)
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.3.3 Interrupt Sources and Timing Chart (with PPG output set for ordinary polarity) This section shows the interrupt sources and timing chart. ■ Interrupt Sources and Timing Chart Figure 8.3-5 shows the interrupt sources and a timing chart. Figure 8.3-5 Interrupt Sources and Timing Chart Start Trigger...
Page 337: Examples Of Methods Of All-L And All-H Ppg Output
8.3.4 Examples of Methods of All-L and All-H PPG Output This section describes the methods used to perform all-L and all-H PPG output. ■ Examples of Methods Used to Perform All-L and All-H PPG Output Figure 8.3-6 shows examples of the methods used to perform all-L and all-H PPG output. Figure 8.3-6 Examples of Methods Used to Perform All-L and All-H PPG Output Using an interrupt by borrow, set the PGMS (mask bit) Reduce the...
Page 338: Activation Of Multiple Channels Using The General Control Register
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.3.5 Activation of Multiple Channels Using the General Control Register If multiple activation triggers are specified using the GCN1 register, multiple channels of PPG timer can be activated at the same time. This section provides an example of multiple-channel activation by software using the GCN2 register.
Page 339 The PPG timer can be reactivated at certain intervals when the output of the 16-bit reload timer is set for toggle output and the following settings are made in the control status register: RTRG: 1 → Reactivation enabled EGS1 and EGS0: 11 → Activation at both rising and falling edges...
Page 340 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER...
Page 341: Chapter 9 Interrupt Controller
CHAPTER 9 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, the configuration and functions of registers, and interrupt controller operation. 9.1 Overview of the Interrupt Controller 9.2 Interrupt Controller Registers 9.3 Operation of the Interrupt Controller...
Page 342: Overview Of The Interrupt Controller
CHAPTER 9 INTERRUPT CONTROLLER Overview of the Interrupt Controller The interrupt controller controls interrupt acceptance and arbitration processing. ■ Hardware Configuration of the Interrupt Controller The interrupt controller module consists of the following components: • ICR register • Interrupt priority decision circuit •...
Page 343 ■ Interrupt Controller Registers Figure 9.1-1 shows the registers used by the interrupt controller. Figure 9.1-1 Interrupt Controller Registers 00000440 ICR00 Address : ICR4 ICR3 ICR2 ICR1 ICR0 00000441 ICR01 Address : ICR4 ICR3 ICR2 ICR1 ICR0 00000442 Address : ICR4 ICR3 ICR2...
Page 344 CHAPTER 9 INTERRUPT CONTROLLER (Continued) 00000464 ICR36 Address : ICR4 ICR3 ICR2 ICR1 ICR0 00000465 ICR37 Address : ICR4 ICR3 ICR2 ICR1 ICR0 00000466 Address : ICR4 ICR3 ICR2 ICR1 ICR0 ICR38 00000467 ICR39 Address : ICR4 ICR3 ICR2 ICR1 ICR0 00000468 ICR40...
Page 345 ■ Block Diagram of the Interrupt Controller Figure 9.1-2 shows the block diagram of the interrupt controller. Figure 9.1-2 Block Diagram of the Interrupt Controller UNMI WAKEUP (LEVEL 11111: '1') Priority decision LEVEL4 to 0 processing HLDREQ MHALTI cancellation LEVEL request LEVEL decision VECTOR...
Page 346: Interrupt Controller Registers
CHAPTER 9 INTERRUPT CONTROLLER Interrupt Controller Registers This section describes the configuration and functions of the registers used by the interrupt controller. ■ Details of the Interrupt Controller Registers The interrupt controller uses the following two types of registers: • Interrupt control register (ICR) •...
Page 347: Interrupt Control Register (Icr)
9.2.1 Interrupt Control Register (ICR) An interrupt control register (ICR) is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request. ■ Bit Configuration of the Interrupt Control Register (ICR) The bit configuration of the interrupt control register (ICR) is shown below. Initial value ---11111 ICR4...
Page 348 CHAPTER 9 INTERRUPT CONTROLLER Table 9.2-1 Correspondence Between Possible Interrupt Level Setting Bits and Interrupt Levels ICR3 ICR2 ICR1 ICR0 Interrupt level ICR4 Reserved for system Maximum level that can be set (High) (Low) Interrupt disabled *: ICR4 is always 1; 0 cannot be written to this bit.
Page 349: Hold Request Cancellation Request Register (Hrcl)
9.2.2 Hold request cancellation request register (HRCL) The hold request cancellation request register (HRCL) is used to set an interrupt level for generating a hold request cancellation request. ■ Bit Configuration of the Hold Request Cancellation Request Register (HRCL) The bit configuration of the hold request cancellation request register (HRCL) is shown below. HRCL Address :00000045 MHALTI...
Page 350: Operation Of The Interrupt Controller
CHAPTER 9 INTERRUPT CONTROLLER Operation of the Interrupt Controller This section describes interrupt controller operation. ■ Priority Decision When multiple interrupt sources exist at the same time, the interrupt controller module selects the interrupt source that has the highest priority and outputs the interrupt level and interrupt number of the selected interrupt source to the CPU.
Page 351 Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal − − NMI request (tool) 000FFFC8 − − Undefined instruction exception 000FFFC4 Always 15 −...
Page 352 CHAPTER 9 INTERRUPT CONTROLLER Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal − 000FFF60 ICR23 − 000FFF5C ICR24 UART4 (reception completed) 000FFF58 ICR25 SIO 5 SIO 6...
Page 353 Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (4 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal Reserved for system − − 000FFEFC (used in REALOS) Reserved for system − − 000FFEF8 (used in REALOS) −...
Page 354 CHAPTER 9 INTERRUPT CONTROLLER ■ NMI (Non Maskable Interrupt) An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled by this module. Thus, an NMI is always selected if it occurs at the same time as other interrupt sources. ●...
Page 355 ■ Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) For an interrupt with a higher priority to be processed during CPU hold, the device that has generated the hold request must cancel the request. Set in the HRCL register the interrupt level to be used as the criterion of generating a cancellation request.
Page 356 CHAPTER 9 INTERRUPT CONTROLLER ■ Return from Standby Mode (Sleep/Stop) This module implements a function that causes a return from stop mode if an interrupt request occurs. If at least one interrupt request that includes NMI occurs (with an interrupt level other than 11111) from the peripheral, a return request from stop mode is generated for the clock controller.
Page 357 ● Sequence Figure 9.3-2 shows an INTC-2 interrupt level that is higher than the one set in the HRCL register. Figure 9.3-2 Interrupt Level (HRCL < ICR) [LEVEL] Bus hold Bus hold Interrupt processing (DMA transfer) Example of interrupt routine Bus access request (1) Interrupt source clear...
Page 358 CHAPTER 9 INTERRUPT CONTROLLER...
Page 359: Chapter 10 External Interrupt And Nmi Controller
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the overview of the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. 10.1 Overview of the External Interrupt and NMI Controller 10.2 External Interrupt and NMI Controller Registers 10.3 Operation of the External Interrupt and NMI Controller...
Page 360: Overview Of The External Interrupt And Nmi Controller
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.1 Overview of the External Interrupt and NMI Controller The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT15. "H" level, "L" level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI).
Page 361 ■ Block Diagram of the External Interrupt and NMI Controller Figure 10.1-1 is a block diagram of the external interrupt and NMI controller. Figure 10.1-1 Block Diagram of the External Interrupt and NMI Controller R-bus Enable interrupt register INT0 to INT15 Interrupt Gate Source F/F...
Page 362: External Interrupt And Nmi Controller Registers
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.2 External Interrupt and NMI Controller Registers This section describes the configuration and functions of the registers used by the external interrupt and NMI controller. ■ Details of the Registers for the External Interrupt and NMI Controller The external interrupt and NMI controller uses the following three types of registers: •...
Page 363: Enable Interrupt Request Register (Enirn)
10.2.1 Enable Interrupt Request Register (ENIRn) Enable interrupt request register (ENIRn) controls masking of external interrupt request output. ■ Bit Configuration of Enable Interrupt Request Register (ENIRn) The bit configuration of enable interrupt request register is shown below. Initial value ENIR0 address :000041 00000000 [R/W]...
Page 364: External Interrupt Request Register (Eirrn)
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.2.2 External Interrupt Request Register (EIRRn) The external interrupt request register (EIRRn) indicates the presence or absence of a corresponding external interrupt request when reading from this register and the contents of the flip-flop (NMI flag) that indicates this interrupt request are cleared when writing to this register.
Page 365: External Level Register (Elvrn)
10.2.3 External Level Register (ELVRn) The external level register (ELVRn) specifies how a request is detected. ■ Bit Configuration of External Level Register (ELVRn) The bit configuration of the external level register is shown below. Initial value 00000000 ELVR0 address :000042 Initial value 00000000 000043...
Page 366: Operation Of The External Interrupt And Nmi Controller
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.3 Operation of the External Interrupt and NMI Controller This section describes operation of the external interrupt and NMI controller. ■ Operation of an External Interrupt If, after the required data is set in the ENIR and ELVR registers, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller.
Page 367 ■ External Interrupt Request Level If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. If the request level is a level setting, and request input arrives from outside and is then cancelled, the request to the interrupt controller remains active because a source holding circuit exists internally.
Page 368 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER Figure 10.3-4 NMI Request Detection (NMI flag) NMI request Q SX Falling edge (Stop clearing) detection φ STOP clear (RST, interrupt acknowledge)
Page 369: Chapter 11 Realos-Related Hardware
CHAPTER 11 REALOS-RELATED HARDWARE This chapter describes the hardware related to REALOS. The REALOS-related hardware is used by the real-time operating system (OS). Accordingly, when REALOS is used, the REALOS-related hardware cannot be used by a user program. 11.1 Delayed Interrupt Module 11.2 Bit Search Module...
Page 370: Delayed Interrupt Module
CHAPTER 11 REALOS-RELATED HARDWARE 11.1 Delayed Interrupt Module This section describes the overview of the delayed interrupt module, the configuration and functions of registers, and module operation. ■ Overview of the Delayed Interrupt Module The delayed interrupt module generates an interrupt for switching tasks. Use this module to enable a software program to generate an interrupt request to the CPU and to clear the request.
Page 371: Overview Of The Delayed Interrupt Module
11.1.1 Overview of the Delayed Interrupt Module This section describes the delayed interrupt module, the configuration and functions of its register, and module operation. ■ Register for the Delayed Interrupt Module The register for the delayed interrupt module is shown below. Address : 00000044 DLYI DICR...
Page 372: Delayed Interrupt Module Registers
CHAPTER 11 REALOS-RELATED HARDWARE 11.1.2 Delayed Interrupt Module Registers This section describes the configuration and functions of the registers used by the delayed interrupt module. ■ Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) The delayed interrupt module register (DICR) controls delayed interrupts. The bit configuration of the delayed interrupt module register (DICR) is shown below.
Page 373: Operation Of The Delayed Interrupt Module
11.1.3 Operation of the Delayed Interrupt Module A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request. ■...
Page 374: Bit Search Module
CHAPTER 11 REALOS-RELATED HARDWARE 11.2 Bit Search Module This section describes the overview of the bit search module, the configuration and functions of registers, and module operation. ■ Overview of the Bit Search Module The bit search module searches the data written to an input register for bit values "0" or "1" or points at which the bit value changes and returns the locations where these are detected.
Page 375: Overview Of The Bit Search Module
11.2.1 Overview of the Bit Search Module This section explains the configuration and functions of the registers used by the bit search module. ■ Bit Search Module Registers The registers for the bit search module are shown below. Address : 000003F0 BSD0 0 detection data register Address : 000003F4...
Page 376: Bit Search Module Registers
CHAPTER 11 REALOS-RELATED HARDWARE 11.2.2 Bit Search Module Registers This section describes the configuration and functions of the registers used by the bit search module. ■ 0 Detection Data Register (BSD0) 0 detection is performed for the written data. The configuration of the 0 detection data register (BSD0) is shown below. 000003F0 →...
Page 377 ■ Change Point Detection Data Register (BSDC) Change point detection is performed for the written data. The configuration of the change point detection data register (BSDC) is shown below. 000003F8 → W Read/write → Undefined Initial value The initial value after a reset is undefined. The read value is undefined.
Page 378: Operation Of The Bit Search Module
CHAPTER 11 REALOS-RELATED HARDWARE 11.2.3 Operation of the Bit Search Module This section describes operation of the bit search module. ■ 0 Detection The bit search module scans data written to the 0 detection data register from the MSB to LSB and returns the location where the first 0 is detected.
Page 379 ■ Change Point Detection The bit search module scans data written to the change point detection data register from bit 30 to the LSB for comparison with the MSB value. The first location where a value that is different from that of the MSB is detected is returned. The detection result can be obtained by reading the detection result register.
Page 380 CHAPTER 11 REALOS-RELATED HARDWARE ■ Save/Restore Processing If it is necessary to save and restore the internal state of the bit search module, such as when the bit search module is used in an interrupt handler, use the following procedure: 1.
Page 381: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER This chapter describes the overview of the A/D converter, the configuration and functions of registers, and converter operation. 12.1 Overview of the A/D Converter 12.2 A/D Converter Registers 12.3 Operation of the A/D Converter...
Page 382: Overview Of The A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 Overview of the A/D Converter The A/D converter converts an analog input voltage into digital value. This section describes the A/D converter. ■ Features of the A/D Converter The A/D converter has the following features: Conversion time: Minimum of 1.48 µs per channel •...
Page 383 ■ Block Diagram of the A/D Converter Figure 12.1-1 shows a block diagram of the A/D converter. Note: The MB91F353A/351A/352A/353A do not have analog inputs AN8 to AN11. Figure 12.1-1 Block Diagram of the A/D Converter Analog input , AVRH, AV , AVRL ADT0 10-bit...
Page 384: A/D Converter Registers
CHAPTER 12 A/D CONVERTER 12.2 A/D Converter Registers This section describes the configuration and functions of the registers used by the A/D converter. ■ A/D Converter Registers The A/D converter uses the following four types of registers: • Control status register (ADCS1) •...
Page 385: Control Status Register (Adcs1)
12.2.1 Control Status Register (ADCS1) The control status register (ADCS1) controls the A/D converter and indicates its status. ■ Bit Configuration of the Control Status Register (ADCS1) The bit configuration of the control status register (ADCS1) is shown below. Address : 000079 BUSY INTE STS1...
Page 386 CHAPTER 12 A/D CONVERTER [Bit 6] INT (interrupt) This INT bit is set when conversion ends. (It is set when conversion of the input on a channel ends in single conversion mode or when conversion of all input on all the specified channels ends in scan conversion mode.) Value Meaning...
Page 387 [Bit 1] STAR (start) Writing "1" to the STAR bit starts the A/D converter. Writing "1" to the STAR bit while the A/D converter is operating (BUSY = 1) is ignored. The value read from the STAR bit is always "0". Do not start the A/D converter by software and forcibly stop it at the same time (by writing "1"...
Page 388: Control Status Register (Adcs2)
CHAPTER 12 A/D CONVERTER 12.2.2 Control Status Register (ADCS2) The control status register (ADCS2) controls the A/D converter and indicates its status. ■ Bit Configuration of the Control Status Register (ADCS2) The bit configuration of the control status register (ADCS2) is shown below. Address : 000078 ACS3 ACS2...
Page 389 ACS3 ACS2 ACS1 ACS0 Channel Corresponding data register Remarks ADTH0, ADTL0 ADAH1, ADTL1 ADTH2, ADTL2 ADTH3, ADTL3 ADTH0, ADTL0 ADAH1, ADTL1 ADTH2, ADTL2 ADTH3, ADTL3 ADTH0, ADTL0 ADAH1, ADTL1 AN10 ADTH2, ADTL2 AN11 ADTH3, ADTL3 Setting not allowed Setting not allowed Setting not allowed Setting not allowed Note: Because the MB91F353A/351A/352A/353A do not have channels AN8, AN9, AN10, and AN11, the...
Page 390 CHAPTER 12 A/D CONVERTER [Bit 8] SCAN The SCAN bit specifies the conversion mode. The SCAN bit is cleared to "0" by a reset. Value Function Single conversion mode Scan conversion mode...
Page 391: Conversion Time Setting Register (Adct)
12.2.3 Conversion Time Setting Register (ADCT) The conversion time setting register (ADCT) specifies the lengths of sampling period and conversion periods a to c (see Figure 12.2-1 ). The width of each period is calculated from "(value set in register × 2 + 1) × 0.04 µs" for a peripheral clock of 25 MHz.
Page 392 CHAPTER 12 A/D CONVERTER Note: The A/D conversion time per channel from the start of conversion to the end of conversion is "sampling time + conversion time a + conversion time b + conversion time c + 3 machine cycles". ■...
Page 393: Data Registers (Adthx And Adtlx)
12.2.4 Data Registers (ADTHx and ADTLx) The data registers (ADTHx and ADTLx) store the digital value that is the result of conversion. ■ Overview of the Data Registers (ADTHx and ADTLx) The format of data storage in the data registers depends on the value of the CREG bit of the ADCS2 register.
Page 394: Operation Of The A/D Converter
CHAPTER 12 A/D CONVERTER 12.3 Operation of the A/D Converter The A/D converter uses a 10-bit serial/parallel conversion system and can convert data in a period as short as 1.48 µs. The A/D converter provides two conversion modes (single conversion and scan conversion modes), which can be selected.
Page 395 ■ Scan Conversion Mode The A/D converter enters the scan conversion mode when the SCAN bit of the control status register is set to "1". In scan conversion mode, the A/D converter starts scanning and conversion with the analog input channel specified by the ACS2 to ACS0 bits of the control status register.
Page 396 CHAPTER 12 A/D CONVERTER Figure 12.3-2 shows the conversion operation in scan conversion mode. Figure 12.3-2 Scan Conversion Mode Example: Value of ACS bits = 010B (specifies scan conversion of channels AN0 to AN3) STAR Start of A/D conversion End of A/D conversion Conversion Conversion Conversion...
Page 397 CHAPTER 13 8-BIT D/A CONVERTER This chapter describes the overview of the 8-bit D/A converter, the configuration and functions of registers, and converter operation. 13.1 Overview of the 8-bit D/A Converter 13.2 8-bit D/A Converter Register 13.3 8-bit D/A Converter Operation...
Page 398: Overview Of The 8-Bit D/A Converter
CHAPTER 13 8-BIT D/A CONVERTER 13.1 Overview of the 8-bit D/A Converter The MB91350A has 3 channels of D/A converters with 8-bit resolution. The output of each channel can be controlled separately using the D/A control registers. Note: The MB91F353A/351A/352A/353A have 2 channels of D/A converters. ■...
Page 399 ■ Block Diagram of the 8-bit D/A Converter Figure 13.1-1 shows a block diagram of the 8-bit D/A converter. Note: The MB91F353A/351A/352A/353A do not have D/A converter ch2. Figure 13.1-1 Block Diagram of the 8-bit D/A Converter R-bus D/A data D/A data D/A control D/A data...
Page 400: 8-Bit D/A Converter Register
CHAPTER 13 8-BIT D/A CONVERTER 13.2 8-bit D/A Converter Register This section describes the configuration and functions of the registers used by the 8-bit D/A converter. ■ DADR0 (D/A Data Register 0) The bit configuration of the D/A data register 0 (DADR0) is shown below. Initial value Address : 00008B •...
Page 401 ■ DACR0 (D/A Control Register 0) The bit configuration of D/A control register 0 (DACR0) is shown below. Initial value Address : 000087 D/A control register 0 specifies whether to enable or disable output from D/A converter ch0. Value Meaning D/A output disabled (0.0 V output) D/A output enabled ■...
Page 402: 8-Bit D/A Converter Operation
CHAPTER 13 8-BIT D/A CONVERTER 13.3 8-bit D/A Converter Operation The 8-bit D/A converter outputs the D/A output value set in the D/A data register when 1 is set in the D/A control register. If D/A output from an 8-bit D/A converter channel is disabled, that channel outputs 0.0 V. Such an output also applies to the operation in stop mode.
Page 403: Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, And Output Compare Module
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE MODULE This chapter describes the overview of the UART, serial I/O interface (SIO), input capture module, and output compare module, the configuration and functions of registers, and the operation of each. 14.1 UART 14.2 Serial I/O Interface (SIO) 14.3 Input Capture Module...
Page 404: Uart
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.1 UART This section describes the overview of the UART, the configuration and functions of registers, and UART operation. ■ Overview of the UART The UART is a serial I/O port that is used to perform asynchronous (start-stop synchronization) or CLK synchronous communication.
Page 405: Features Of The Uart
14.1.1 Features of the UART This section describes the features and registers of the UART, and also provides a block diagram of the UART. ■ Features The UART has the following features: • Full-duplex double buffer • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. •...
Page 406 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ UART Registers The UART registers are shown below. (R/W) SIDR(R)/SODR(W) (R/W) DRCL 8bit 8bit Serial input register Serial output register (SIDR /SODR) Serial status register (SSR) RDRF TDRE Serial mode register (SMR)
Page 407 ■ Block Diagram of the UART Figure 14.1-1 is a block diagram of the UART. Figure 14.1-1 Block Diagram of the UART Control signal Receive interrupt (to CPU) SCK (clock) Send clock From U-TIMER Clock Receive clock selection Send interrupt circuit (to CPU) External clock...
Page 408: Uart Registers
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.1.2 UART Registers This section describes the configuration and functions of the registers used by the UART. ■ Serial Mode Register (SMR) The bit configuration of the serial mode register (SMR) is shown below. Note: The MB91F353A/351A/352A/353A do not have SMR ch4.
Page 409 [Bit 3] CS0 (Clock Select) This bit selects the UART operating clock. Value Meaning Built-in timer (U-TIMER) [initial value] External clock [Bit 2, 1] (reserved) Always write "0" to these bits. [Bit 0] (reserved) This bit is unused. ■ Serial Control Register (SCR) The bit configuration of the serial control register (SCR) is shown below.
Page 410 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [Bit 6] P (Parity) This bit specifies that even or odd parity be added to perform data communication. Value Meaning Even parity [initial value] Odd parity [Bit 5] SBL (Stop Bit Length) This bit specifies the number of stop bits, which marks the end of a frame in asynchronous (start-stop synchronization) communication.
Page 411 [Bit 1] RXE (Receiver Enable) This bit controls the UART receive operation. Value Meaning Disables receive operation. [initial value] Enables receive operation. Note: If a receive operation is disabled while it is in progress (while data is being inputted to the receive shift register), reception of the frame is completed.
Page 412 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) The bit configurations of the serial input data register (SIDR) and serial output data register (SODR) are shown below.
Page 413 ■ Serial Status Register (SSR) The bit configuration of the serial status register (SSR) is shown below. Note: The MB91F353A/351A/352A/353A do not have SSR ch4. Address : ch0 000060 Initial value ch1 000068 00001000 RDRF TDRE ch2 000070 ch3 0000C0 ch4 0000C8 The SSR is configured from flags that indicate the operating status of the UART.
Page 414 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [Bit 5] FRE (FRaming Error) This bit, which is an interrupt request flag, is set when a framing error occurs during reception. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the FRE bit is set, the SIDR data becomes invalid.
Page 415 [Bit 2] BDS (Bit Direction Select) This bit selects the transfer direction. Value Meaning Sends starting from the least significant bit (LSB). [initial value] Sends starting from the most significant bit (MSB). Note: Because the high-order and low-order data are switched when the serial data register is written to or read, the data will become invalid if the bit is rewritten after data is written to the SDR register.
Page 416 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ DRCL The bit configuration of the DRCL register is shown below. DRCL Initial value Address : ch0 000066 ch1 00006E -------- ch2 000076 The DRCL register clears a DMAC interrupt source. Write an arbitrary value to the DRCL register to clear a DMAC interrupt source.
Page 417: Operation Of The Uart
14.1.3 Operation of the UART This section describes the UART operation. ■ Operating Modes of the UART The UART has the operating modes shown in Table 14.1-2 . Set a value in the SMR and SCR registers to switch mode. Table 14.1-2 lists the UART operating modes. Table 14.1-2 UART Operating Modes Mode Parity...
Page 418 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Asynchronous (Start-stop Synchronization) Mode ● Transfer data format UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-2 shows the data format. Figure 14.1-2 Transfer Data Format (Modes 0 and 1) SI,SO Start...
Page 419 ■ CLK Synchronous Mode ● Transfer data format The UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-3 shows the relationship between send and receive clocks and data. Figure 14.1-3 Transfer Data Format (Mode 2) Writing to SODR Mark RXE, TXE...
Page 420 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE • SCR register • PEN: 0 • P,SBL,A/D: These bits are meaningless. • CL: 1 • REC: 0 (to initialize the register) • RXE, TXE: At least one of the bits must be set to "1". •...
Page 421 ● Receive operation in Mode 0 The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The SIDR data is invalid while PE, ORE, and FRE are active.
Page 422 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ● Reception operation in Mode 2 The ORE and RDRF flags are set when the last data (D7) is detected after the reception transfer is completed, generating an interrupt request to the CPU. The SIDR data is invalid while ORE is active. Figure 14.1-6 shows the timing of setting ORE and RDRF in Mode 2.
Page 423 ● Send operation in modes 0, 1, and 2 TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the internal shift register and the next data can be written, causing an interrupt request to be generated for the CPU.
Page 424 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Notes: • Writing to the SODR register starts communication. Even for receive only, dummy send data must be written to the SODR register. • Set the communication mode while operation is stopped. Data send and received while the operating mode is being set is unpredictable.
Page 425: Example Of Using The Uart
14.1.4 Example of using the UART UART mode 1 is used in a system in which multiple slave CPUs are connected to a host CPU. ■ Example of System Construction (Using Mode 1) Figure 14.1-9 shows an example of constructing a system using mode 1. This resource supports only a communications interface on the host.
Page 426 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Figure 14.1-10 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1". Set data used to select slave CPUs in D0 to D7, set "1" in A/D, and transfer 1 byte.
Page 427 ■ Example of Setting Baud Rates and U-TIMER Reload Values Table 14.1-3 gives examples of setting values for baud rates and U-TIMER reload values in asynchronous (start-stop synchronization) mode. Table 14.1-4 gives examples of setting values for baud rates and U- TIMER reload values in CLK synchronous mode.
Page 428: Serial I/O Interface (Sio)
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.2 Serial I/O Interface (SIO) This section provides an overview of the serial I/O interface (SIO), describes the register structure and functions, and describes the operation of the SIO. ■...
Page 429: Overview Of The Serial I/O Interface (Sio)
14.2.1 Overview of the Serial I/O Interface (SIO) The serial I/O interface (SIO) allows selection of the data transfer mode from the LSB- first and MSB-first modes. The MB91F355A/354A/355A/F356B/F357B have a 3 channel serial I/O interface. The MB91F353A/351A/352A/353A have a 2-channel serial I/O interface. ■...
Page 430 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Block Diagram of the Serial I/O Interface (SIO) Figure 14.2-1 shows a block diagram of the serial I/O interface (SIO). Figure 14.2-1 Block Diagram of the Serial I/O Interface Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first)
Page 431: Serial I/O Interface Registers
14.2.2 Serial I/O Interface Registers This section describes the configuration and functions of the registers used by the serial I/O interface. ■ Serial Mode Control Status Register (SMCS) The bit configuration of the serial mode control status register (SMCS) is shown below. Initial value: SMCS Address : 000024...
Page 432 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Setting of the communication prescaler (CDCR) (Machine clock) DIV3 DIV2 DIV1 DIV0 These bits are initialized to "000" upon a reset. These bits must not be updated during data transfer. Five types of internal shift clock and an external shift clock are available.
Page 433 [bit 10] Transfer status bit (BUSY) The transfer status bit indicates whether serial transfer is being executed. BUSY Operation Stopped, or standing by for serial data register R/W [default] Serial transfer This bit is initialized to "0" upon a reset. This is a read-only bit. [bit 9] Stop bit (STOP) The stop bit forcibly terminates serial transfer.
Page 434 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Notes: • Be sure to specify the transfer direction before writing data to the serial shift data register (SDR). • The BDS bit is cleared to "0" by a reset. This bit can be read and written [Bits 7 to 4, 1, and 0]: Unused bits These bits are not used.
Page 435 ■ Serial I/O Prescaler Control Register (CDCR) The bit configuration of the serial I/O prescaler control register (CDCR) is shown below. This register must be accessed in byte units. CDCR Address : 000032 DIV3 DIV2 DIV1 DIV0 Initial value: 0---1111 000034 000036 Note:...
Page 436 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ DMAC Interrupt Source Clear Register (SRCL) The bit configuration of the DMAC interrupt source clear register (SRCL) is shown below. This register must be accessed in byte units. SRCL Address : 000039 Initial value: --------...
Page 437: Operation Of The Serial I/O Interface (Sio)
14.2.3 Operation of the Serial I/O Interface (SIO) The serial I/O interface (SIO) consists of a serial mode control status register (SMCS) and a serial shift data register (SDR) and is used to input and output 8-bit serial data. ■ Overview of Serial I/O Interface (SIO) Operation For output, the bit contents of the serial shift data register (SDR) are outputted via a serial output pin (SO5 to SO7) in synchronization with the falling edge of the serial shift clock (external or internal clock).
Page 438 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ● External shift clock mode In external shift clock mode, data is transferred at a rate of 1 bit per clock pulse in synchronization with the external shift clock input via the SCK pin. The transfer speed can be set in a range from DC to 1/(8 peripheral system clock cycles).
Page 439 Figure 14.2-2 Extended I/O Serial Interface Operation Transitions Reset STOP=0 & STRT=0 End of transfer STOP STRT=0, BUSY=0 STRT=0, BUSY=0 STOP=1 MODE=0 MODE=0 STOP=0 & & STOP=0 STOP=1 STOP=0 STOP=1 STRT=1 & & STRT=1 Tra nsfer Serial data register R/W standby MODE=1 &...
Page 440 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Figure 14.2-4 Shift Operation Start/stop Timing (Internal Clock) "1" output SCK5 to SCK7 (Transfer start) (Transfer end) STRT If MODE=0 BUSY S05 to S07 DO7 (Data maintained) Figure 14.2-5 shows the timing of starting and stopping the shift operation in LSB-first mode based on the external clock.
Page 441 Figure 14.2-7 shows the timing of stopping transfer operation when "1" is written to the STOP bit. Figure 14.2-7 Stop Timing when "1" is Written to the STOP Bit "1" output SCK5 to SCK7 (Transfer start) (Transfer stop) STRT If MODE=0 BUSY STOP SO5 to SO7...
Page 442 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Interrupt Function The serial I/O interface can generate an interrupt request for the CPU. An interrupt request is outputted to the CPU when both the serial I/O interrupt request (SIR) bit (i.e., interrupt flag) and the serial I/O interrupt enable (SIE) bit of the SMCS register are "1"...
Page 443: Input Capture Module
14.3 Input Capture Module This section describes the overview of the input capture module, the configuration and functions of registers, and module operation. ■ Overview of the Input Capture Module The input capture module detects either or both of the rising and falling edges for an externally input signal and stores the 16-bit free-running timer value set at that time in a register.
Page 444: Overview Of The Input Capture Module
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.1 Overview of the Input Capture Module The input capture module consists of an input capture data register and an input capture control register. ■ External Input Pin Corresponding to Each Input Capture Channel An external input pin is assigned to each input capture channel.
Page 445 ■ Input Capture Block Diagram Figure 14.3-1 shows a block diagram of the input capture module. Figure 14.3-1 Input Capture Block Diagram 16-bit timer count value (T15 to T00) IN0, 2 Capture data register Edge Input pin detection ch(0,2) EG11 EG10 EG01 EG00...
Page 446: Input Capture Module Registers
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.2 Input Capture Module Registers This section describes the configuration and functions of the registers used by the input capture operation. The input capture module has the following two types of registers: •...
Page 447 [Bits 7 and 6] ICP3 to ICP0 These bits are used as input capture interrupt flags. When a valid edge of the signal input via an external input pin is detected, "1" is written to the corresponding bits in ICP3 to ICP0. If the corresponding interrupt enable bit (ICE3 to ICE0) is set, an interrupt can be generated when the valid edge is detected.
Page 448: Input Capture Operation
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.3 Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register.
Page 449: Output Compare
14.4 Output Compare This section describes the overview of the output compare module, the configuration and functions of registers, and module operation. ■ Overview of the Output Compare Module The output compare module consists of 16-bit compare registers, compare output latches, and control registers.
Page 450: Features Of The Output Compare Module
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.4.1 Features of the Output Compare Module The MB91F355A/355A/354A/F356B/F357B have eight output compare channels. The MB91F353A/351A/352A/353A have two output compare channels. ■ Features of the Output Compare Module The output compare module has the following features: •...
Page 451 ■ Block Diagram of the Output Compare Module Figure 14.4-1 shows a block diagram of the output compare module. Figure 14.4-1 Block Diagram of the Output Compare Module OTD1 OTD0 (Only the compare register for channel 0 is used as the free-running timer clear register.) Compare register Compare...
Page 452: Output Compare Module Registers
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.4.2 Output Compare Module Registers This section describes the configuration and functions of the registers used by the output compare operation. The output compare module has the two types of registers shown below.
Page 453 Note: The MB91F353A/351A/352A/353A do not have OCS45 and OCS67. [Bits 15 to 13] Unused bits "1" is always read from these bits. [bit 12] CMOD CMOD is used to switch the pin output level reverse mode upon a comparison match while pin output is enabled (OTE1=0 or OTE0=1:PFR0).
Page 454 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set to "1".
Page 455: Operation Of The Output Compare Module
14.4.3 Operation of the Output Compare Module In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16- bit free-run timer value. ■...
Page 456 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Timing of 16-bit Output Compare Operation The output level can be changed using two pairs of compare registers (when CMOD = 1). In output compare operation, a compare match signal is generated when the free-running timer value matches the specified compare register value.
Page 457: Chapter 15 I 2 C Interface
CHAPTER 15 C INTERFACE This chapter describes the overview of the I C interface, the configuration and functions of registers, and operation. 15.1 Overview of the I C Interface 15.2 I C Interface Registers 15.3 Explanation of I C Interface Operation 15.4 Operation Flowcharts...
Page 458: Overview Of The I 2 C Interface
CHAPTER 15 I C INTERFACE 15.1 Overview of the I C Interface The I C interface is a serial I/O port that supports the Inter-IC Bus. The I C interface operates as a master or slave device on the I C bus.
Page 459 15.1 Overview of the I C Interface ■ I C Interface Registers The I C interface registers are listed below. • Bus control register (IBCR) Address : 000094 BEIE GCAA INTE Initial value→ • Bus status register (IBSR) Address : 000095 Initial value→...
Page 460 CHAPTER 15 I C INTERFACE • 7-bit slave address mask register (ISMK) Address : 00009A ENSB Initial value→ • Data register (IDAR) Address : 00009D Initial value→ • Clock control register (ICCR) Address : 00009E TEST Initial value→ • Clock disable register (IDBL) Address : 00009F Initial value→...
Page 461 15.1 Overview of the I C Interface ■ Block Diagram of the I C Interface Figure 15.1-1 is a block diagram of the I C interface. Figure 15.1-1 Block Diagram of the I C Interface ICCR C operation enable IDBL Clock enable CLKP ICCR...
Page 462: C Interface Registers
CHAPTER 15 I C INTERFACE 15.2 C Interface Registers This section describes the configuration and functions of registers used by the I interface. ■ Overview of the I C Interface Registers The I C interface has the following nine types of registers: •...
Page 463: Bus Status Register (Ibsr)
15.2 I C Interface Register 15.2.1 Bus Status Register (IBSR) The bus status register (IBSR) is read-only. All bits are cleared when the I C stops operating (EN = 0 in ICCR). ■ Bus Status Register (IBSR) The configuration of the bus status register (IBSR) is shown below. Address : 000095 Initial value→...
Page 464 CHAPTER 15 I C INTERFACE [Bit 4] LRB (Last Received Bit) This bit is an acknowledge storage bit that stores an acknowledge from the receiving device. Value Function Slave acknowledge detected Slave acknowledge not detected This bit is rewritten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START or STOP condition is detected.
Page 465 15.2 I C Interface Register [Bit 1] GCA (General Call Address) This bit is the general call address (00 ) detection bit. Value Function General call address is not received as a slave. General call address is received as a slave. This bit is cleared when a (repeated) START or STOP condition is detected.
Page 466: Bus Control Register (Ibcr)
CHAPTER 15 I C INTERFACE 15.2.2 Bus Control Register (IBCR) All bits except for the BER and BEIE bits are cleared when the I C stops operating (EN = 0 in ICCR). ■ Bus Control Register (IBCR) The configuration of the bus control register (IBCR) is shown below. Address : 000094 BEIE GCAA...
Page 467 15.2 I C Interface Register [Bit 14] BEIE (Bus Error Interrupt Enable) This bit is the bus error interrupt enable bit. Value Function Bus error interrupt disabled Bus error interrupt enabled An interrupt occurs if this bit is set to "1" and the BER bit is set to "1". [Bit 13] SCC (Start Condition Continue) This bit is the repeated [START] condition generation bit.
Page 468 CHAPTER 15 I C INTERFACE the bus has become idle. It is important to check whether the I C interface is specified as a slave (IBSR AAS = 1), and whether data transmission has ended normally (IBCR MSS = 1) at the next interrupt or otherwise data transmission has failed with an error (IBSR AL = 1).
Page 469 15.2 I C Interface Register [Bit 8] INT (INTerrupt) This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, "1" is read. During writing Value Function Clears the transfer end interrupt request flag. Has no meaning.
Page 470 CHAPTER 15 I C INTERFACE When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR register to "1") with no start condition detected (BB bit=0) and with the SDA or SCL pin at the "L" level.
Page 471 15.2 I C Interface Register Figure 15.2-2 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur The INT bit interrupt does not occur Stop Condition Start Condition in the ninth clock cycle. SCL pin SDA pin SLAVE ADDRESS EN bit...
Page 472 CHAPTER 15 I C INTERFACE A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait* for the time for three-bit data transmission at the I transfer frequency set in the clock control register (ICCR). BB bit=0 and AL bit=1? to normal process Set the EN bit to "0"...
Page 473: Clock Control Register (Iccr)
15.2 I C Interface Register 15.2.3 Clock Control Register (ICCR) Clock control register specifies the enabled operation of I C interface and the frequency of serial clock. ■ Clock Control Register (ICCR) The configuration of the clock control register (ICCR) is shown below. Address : 00009E TEST Initial value→...
Page 474 CHAPTER 15 I C INTERFACE Register settings Setting disabled for CS4 to CS0=00000 100K bps 400K bps Clock frequency CLKP [MHz] fsck [kHz] fsck [kHz] 396.8 12.5 101.6 320.5 16.7 97.6 327.4 8.33 95.7 308.5 7.14 95.2 264.4 6.25 99.2 231.4...
Page 475: 10-Bit Slave Address Register (Itba)
15.2 I C Interface Register 15.2.4 10-bit Slave Address Register (ITBA) Rewrite the 10-bit slave address register (ITBA) while operation is stopped (EN = 0 in ICCR). ■ 10-bit Slave Address Register (ITBA) The configuration of the 10-bit slave address register (ITBA) is shown below. Address : 000096 ITBAH Initial value→...
Page 476: 10-Bit Slave Address Mask Register (Itmk)
CHAPTER 15 I C INTERFACE 15.2.5 10-bit Slave Address Mask Register (ITMK) This section describes the 10-bit slave address mask register (ITMK). ■ 10-bit Slave Address Mask Register (ITMK) The configuration of the 10-bit slave address mask register (ITMK) is shown below. Address : 000098 ENTB Initial value→...
Page 477 15.2 I C Interface Register [Bits 9 to 0] 10-bit slave address mask bits These bits mask the bits of the 10-bit slave address register (ITBA). Write to this register when the C interface is disabled (ICCR EN = 0). Value Function This bit is not used for comparison of slave addresses...
Page 478: 7-Bit Slave Address Register (Isba)
CHAPTER 15 I C INTERFACE 15.2.6 7-bit Slave Address Register (ISBA) Rewrite the 7-bit slave address register (ISBA) while operation is stopped (EN = 0 in ICCR). ■ 7-bit Slave Address Register (ISBA) The configuration of the 7-bit slave address register (ISBA) is shown below. Address : 00009B Initial value→...
Page 479: 7-Bit Slave Address Mask Register (Ismk)
15.3 Explanation of I C Operation 15.2.7 7-bit Slave Address Mask Register (ISMK) Rewrite the 7-bit slave address mask register (ISMK) while operation is stopped (EN = 0 in ICCR). ■ 7-bit Slave Address Mask Register (ISMK) The configuration of the 7-bit slave address mask register (ISMK) is shown below. Address : 00009A ENSB Initial value→...
Page 480: Data Register (Idar)
CHAPTER 15 I C INTERFACE 15.2.8 Data Register (IDAR) This section describes the data register (IDAR). ■ Data Register (IDAR) The configuration of the data register (IDAR) is shown below. Address : 00009D Initial value→ [Bits 7 to 0] Data bits (D7 to D0) Bits D7 to D0 are a data register used for serial transfer.
Page 481: Clock Disable Register (Idbl)
15.3 Explanation of I C Operation 15.2.9 Clock Disable Register (IDBL) This section describes the clock disable register (IDBL). ■ Clock Disable Register (IDBL) The configuration of the clock disable register (IDBL) is shown below. Address : 00009F Initial value→ [Bit 0] Clock disable bit (DBL) This bit specifies whether to supply or stop supply of the operating clock for the I C interface.
Page 482: Explanation Of I 2 C Interface Operation
CHAPTER 15 I C INTERFACE 15.3 Explanation of I C Interface Operation The I C bus consists of two bidirectional bus lines used for transfer: one serial data line (SDA) and one serial clock line (SCL). The I C interface has two corresponding open- drain I/O pins (SDA and SCL), enabling wired logic.
Page 483 15.4 Operation Flowcharts ■ Slave Address Detection In slave mode, BB=1 is set after a START condition is generated. The transmitted data from the master is stored in the IDAR register. [When a 7-bit slave address is enabled] (ISMK ENSB=1) After 8-bit data is received, the IDAR and ISBA register values are compared.
Page 484 CHAPTER 15 I C INTERFACE ■ Master Addressing In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and the IDAR register contents are outputted starting with the MSB. After address data is sent and an acknowledge is received from a slave device, bit 0 of the send data (bit 0 of the IDAR register after transmission) is inverted and stored in the TRX bit.
Page 485 15.4 Operation Flowcharts ■ Communication Error that Causes No Error If an incorrect clock is generated on the SCL line due to noise or some other reason during transmission in master mode, the transmission bit counter of the I C interface may run quickly, causing the slave to hang while the "L"...
Page 486: Operation Flowcharts
CHAPTER 15 I C INTERFACE 15.4 Operation Flowcharts This section provides operation flowcharts using slave address, data transfer, and receive data as examples. ■ Example of Slave Address and Data Transfer Figure 15.4-1 is an example of slave address and data transfer. Figure 15.4-1 Example of Slave Address and Data Transfer Transfer data 7-bit slave addressing...
Page 487 ■ Example of Receive Data Figure 15.4-2 is an example of receive data. Figure 15.4-2 Example of Receive Data Start Slave address in read access Clear the ACK bit if data is the last read data from the slave. INT=0 INT=1? Bus error BER=1?
Page 488 CHAPTER 15 I C INTERFACE ■ Interrupt Processing Figure 15.4-3 shows interrupt processing. Figure 15.4-3 Interrupt Processing START Receive INT=1? interrupt from another module Bus error BER=1? Restart GCA=1? General call detected in slave mode AAS=1? Failure of transfer Retry Arbitration lost AL=1? AL=1?
Page 489: Chapter 16 Dma Controller (Dmac)
CHAPTER 16 DMA CONTROLLER (DMAC) This chapter describes the DMAC, the configuration and functions of registers, and DMAC operation. 16.1 Overview 16.2 Detailed Explanation of Registers 16.3 Explanation of Operation 16.4 Operation Flowcharts 16.5 Data Path 16.6 DMA External Interface...
Page 490: Overview
CHAPTER 16 DMA CONTROLLER (DMAC) 16.1 Overview This module implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various data transfer operations can be executed at high speed by bypassing the CPU, enhancing system performance. ■...
Page 491 • Transfer mode Demand transfer, burst transfer, step transfer, and block transfer Note: The MB91F353A/351A/352A/353A do not support demand transfer. Addressing mode: 32-bit full addressing (increment/decrement/fixed) (The address increment/decrement range is from -255 to + 255.) Data types: Byte, halfword, and word length Single shot/reload selectable ■...
Page 492 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Block Diagram Figure 16.1-2 is a block diagram of the DMA controller (DMAC). Figure 16.1-2 Block Diagram of the DMAC Counter DMA activation Buffer source DMA transfer request to Peripheral activation request/stop input selection circuit the bus controller &...
Page 493: Detailed Explanation Of Registers
16.2 Detailed Explanation of Registers This section describes the DMAC registers in detail. ■ Notes on Setting Registers When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while DMA is in progress (during transfer), correct operation cannot be guaranteed. A marked bit indicates that the bit affects operation if it is set during DMAC transfer.
Page 494: Dmac Ch0 To Ch4 Control/Status Registers A
CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.1 DMAC ch0 to ch4 Control/Status Registers A The DMACA0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■ Functions of the DMACA0 to 4 Bits The functions of the DMACA0 to 4 bits are shown below.
Page 495 [Bit 30] PAUS (PAUSe): Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx). If this bit is set before starting, DMA transfer continues to be temporarily stopped.
Page 496 CHAPTER 16 DMA CONTROLLER (DMAC) [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection These bits select the source of the transfer request as listed in the table below. Note that the software transfer request by the STRG bit function is always valid regardless of the settings of these bits. Function 00000 Hardware...
Page 497 External request input is valid only for ch0, 1, and 2. External request input cannot be selected for ch3 and 4. Whether level detection or edge detection is used is determined by the mode setting. (Level detection is selected for demand transfer. For all other cases, edge detection is selected.) When the transfer factor of external interrupt 0 to 2 and A/D interrupt is selected, it is not possible to use it on the condition that the setting of CPU clock and peripheral clock by (DIVR0) of Base Clock Division Setting Register shows in the following.
Page 498 CHAPTER 16 DMA CONTROLLER (DMAC) [Bits 23 to 20] DDNO3 to 0 (direct access number): Fly-by function for built-in peripherals These bits specify the built-in peripheral of the transfer destination/source used by the corresponding channel. DDN0 Function 0000 Setting disabled 0001 Unused 0010...
Page 499 [Bits 19 to 16] BLK3 to 0 (BLocK size): Block size specification These bits specify the block size for block transfer on the corresponding channel. The value specified by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width setting).
Page 500: Dmac Ch0 To Ch4 Control/Status Registers B
CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.2 DMAC ch0 to ch4 Control/Status Registers B The DMACB0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■ Functions of the DMACB0 to 4 Bits The functions of the DMACB0 to 4 bits are shown below.
Page 501 [Bits 29 to 28] MOD (MODe): Transfer mode setting These bits set the operating mode of the corresponding channel as listed in the table below. Function Block/step transfer mode (initial value) Burst transfer mode Demand transfer mode Setting disabled • When reset: Initialized to "00".
Page 502 CHAPTER 16 DMA CONTROLLER (DMAC) [Bit 24] DADM (Destination-ADdr. Count-Mode select): Transfer destination address count mode specification This bit specifies the address processing for the transfer destination address of the corresponding channel in each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer destination address count width (DASZ).
Page 503 [Bit 22] SADR (Source-ADdr.-reg. Reload): Transfer source address register reload specification This bit controls reloading of the transfer source address register for the corresponding channel. If this bit enables the reload operation, the transfer source address register value is restored to its initial value after the transfer is completed.
Page 504 CHAPTER 16 DMA CONTROLLER (DMAC) [Bit 19] EDIE (EnD Interrupt Enable): End interrupt output enable This bit controls the occurrence of an interrupt for normal termination. EDIE Function Disables end interrupt request output. (initial value) Enables end interrupt request output. •...
Page 505 [Bits 7 to 0] DASZ (Des Addr count SiZe): Transfer destination address count size specification These bits specify the increment or decrement width for the transfer destination address (DMADA) of the corresponding channel for each transfer operation. The value set by these bits becomes the address increment/decrement width for each transfer unit.
Page 506: Dmac Ch0 To Ch4 Transfer Source/Transfer Destination Address Setting Registers
CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.3 DMAC ch0 to ch4 Transfer Source/Transfer Destination Address Setting Registers The DMASA0 to 4 registers and DMADA0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■...
Page 507 Note: Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the DMAC’s registers themselves.
Page 508: Dmac Ch0 To Ch4 Dmac All-Channel Control Register
CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.4 DMAC ch0 to ch4 DMAC All-Channel Control Register The DMACR register controls the operation of all five DMAC channels. Always use byte length to access this register. ■ Functions of the DMACR Bits The functions of the DMACR bits are shown below. DMAE PMO1 DMAH [3 : 0]...
Page 509 [Bit 28] PM01 (Priority mode ch0,1 robin): Channel priority rotation This bit is set to alternate priority for each transfer between Channel0 and Channel1. PM01 Function Fixes the priority. ( ch0 > ch1 )(initial value) Alternates priority. ( ch1 > ch0 ) •...
Page 510: Explanation Of Operation
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3 Explanation of Operation This section provides an overview of DMAC operation. It also provides details of transfer request settings and transfer sequences and operational details. ■ Overview of DMAC The DMAC block is a multifunctional DMA controller that controls high-speed data transfer without the use of CPU instructions.
Page 511: Overview Of Operation
16.3.1 Overview of Operation This section provides an overview of DMAC operation. ■ Main DMAC Operations Functions can be set for each transfer channel independently. Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has been detected.
Page 512 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Transfer Type ● 2-cycle transfer (normal transfer) The DMA controller operates using as its unit of operation a read operation and a write operation. Data is read from an address in the transfer source register and then written to another address in the transfer destination register.
Page 513 After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then restored to the temporary storage buffer. Because the contents of this temporary storage buffer are written back to the register (DMADA) after each block transfer unit is completed, the address register (DMADA) value is updated after each block transfer unit is completed, making it impossible to determine the address in real time during transfer.
Page 514: Setting A Transfer Request
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.2 Setting a Transfer Request The following three types of transfer requests are provided to activate DMA transfer: • External transfer request pin • Built-in peripheral request • Software request Software requests can always be used regardless of the settings for other requests. ■...
Page 515: Transfer Sequence
16.3.3 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently for each channel (Settings for TYPE[1:0] and MOD[1:0] of DMACB). ■ Selection of the Transfer Sequence The following sequence can be selected with a register setting: •...
Page 516 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.3-1 shows an example of burst transfer. Figure 16.3-1 Example of Burst Transfer Transfer request ( edge) Bus operation Transfer count Transfer end ■ Burst Fly-by Transfer A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory →...
Page 517 Table 16.3-3 lists the specifiable transfer addresses for demand transfer 2-cycle transfer. Table 16.3-3 Specifiable Transfer Addresses for Demand Transfer 2-Cycle Transfer Transfer source address Direction Transfer destination address → External area External area → External area Built-in I/O → External area Built-in RAM →...
Page 518 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Step Transfer If "1" is set as the block size, a step transfer sequence is generated. [Features of a step transfer] • If a transfer request is received, the transfer request is cleared after one transfer operation and then the transfer is stopped (The DMA transfer request to the bus controller is canceled).
Page 519: General Aspects Of Dma Transfer
16.3.4 General Aspects of DMA Transfer This section describes DMA transfer. ■ Block Size The unit and increment for transfer data is a set of (the number set in the block size specification register x data width) data. Since the amount of data transferred in one transfer cycle is determined by the value specified as the data width, one transfer unit is consists of the number of transfer cycles for the specified block size.
Page 520 CHAPTER 16 DMA CONTROLLER (DMAC) If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is performed the specified number of times is not implemented and only the values of each address register are set. [Special examples of operating mode and the reload operation] If transfer is performed in continuous transfer mode by external pin input level detection and transfer count register reloading is used, transfer continues by reloading even though transfer ends during continuous input.
Page 521: Addressing Mode
16.3.5 Addressing Mode Specify the transfer destination/transfer source address independently for each transfer channel. This section describes the specification method. Specify the addresses based on the transfer sequence. ■ Address Register Specifications In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register (DMASA) and the transfer destination address in the transfer destination address setting register (DMADA).
Page 522: Data Types
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.6 Data Types Select the data length (data width) transferred in one transfer operation from the following: • Byte • Halfword • Word ■ Access Address Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an address with a different data length is specified for the transfer destination/transfer source address.
Page 523: Transfer Count Control
16.3.7 Transfer Count Control Specify the transfer count within the range of the maximum 16-bit length (1 to 65536). Set the transfer count value in the transfer count register (DTC of DMACA). ■ Transfer Count Registers and Reload Operation The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer count counter.
Page 524: Cpu Control
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.8 CPU Control When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts.
Page 525: Hold Arbitration
16.3.9 Hold Arbitration When a device is operating in external bus extended mode, an external hold function can be used. The relationship between external hold requests and DMA transfer requests by this module when the hold function can be used is described below. ■...
Page 526: Operation From Starting To End/Stopping
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.10 Operation from Starting to End/Stopping Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. ■ Enabling Operation for All Channels Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the DMA operation enable bit (DMAE of DMACR).
Page 527: Transfer Request Acceptance And Transfer
16.3.11 Transfer Request Acceptance and Transfer This section describes transfer request acceptance and transfer. ■ Transfer Request Acceptance and Transfer Sampling for transfer requests set for each channel starts after starting. If edge detection is selected for the external pin start source and a transfer request is detected, the request is retained within DMAC until the clear conditions are met (when the external pin start source is selected for block, step, or burst transfer).
Page 528: Clearing Peripheral Interrupts By Dma
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.12 Clearing Peripheral Interrupts by DMA This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is selected as the DMA start source (when IS[4:0]=1xxxx). Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0] are cleared.
Page 529: Temporary Stopping
16.3.13 Temporary Stopping This section describes the temporary stopping of DMA transfer. ■ Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until release of temporary stopping is set again.
Page 530: Operation End/Stopping
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.14 Operation End/Stopping The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ■ Transfer End If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests are disabled after the transfer count register becomes "0"...
Page 531: Stopping Due To An Error
16.3.15 Stopping Due To an Error In addition to normal end after transfer for the number of times specified, stopping as the result of various types of errors and the forced stopping are provided. ■ Transfer Stop Requests from Peripheral Circuits Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an error is detected (Example: Error when data is received at or sent from a communications system peripheral).
Page 532: Dmac Interrupt Control
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.16 DMAC Interrupt Control Independent of peripheral interrupts that become transfer requests, interrupts can also be outputted for each DMAC channel. ■ Interrupts That Enable DMAC Interrupt Control Outputs • Transfer end interrupt: Occurs only when operation ends normally. •...
Page 533: Dma Transfer During Sleep
16.3.17 DMA Transfer during Sleep The DMAC can also operate in sleep mode. This section describes DMA transfer in sleep mode. ■ Notes on DMA Transfer in Sleep Mode If you anticipate operations during sleep mode, note the following: 1. Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is entered.
Page 534: Channel Selection And Control
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.18 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is possible only on 1 channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later).
Page 535 ● Rotation mode (ch.0 to ch.1 only) When operation is enabled, the initial states have the same order that they would have in fixed mode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer request is outputted at the same time, the channel is switched after each transfer unit.
Page 536: Supplement On External Pin And Internal Operation Timing
CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.19 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation timing. ■ Minimum Effective Pulse Width of the DREQ Pin Input. (The MB91F353A/351A/352A/353A do not have 0, 1, and 2 channels.) Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimum effective pulse width of five system clock cycles (five cycles of external bus clock [CLKT]).
Page 537 Figure 16.3-6 shows a negate timing example of the DREQ pin input for 2-cycle external transfer → internal transfer. Figure 16.3-6 Negate Timing Example of the DREQ Pin Input for 2-cycle External Transfer → Internal Transfer Bus operation *1: External Area *2: Internal External D bus...
Page 538 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel ● For burst, step, block, and demand transfers Operation in which transfer is continued over the same channel by the DREQ pin input cannot be guaranteed.
Page 539 ■ If an External Pin Transfer Request is Reentered During Transfer ● For burst, step, and block transfers While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled. However, since operation of the external bus control unit and operation of the DMAC are not completely synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to enable transfer requests by using DREQ input.
Page 540: Operation Flowcharts
CHAPTER 16 DMA CONTROLLER (DMAC) 16.4 Operation Flowcharts Figure 16.4-1 to Figure 16.4-3 show operation flowcharts for DMA transfer. ■ Operation Flowchart for Block Transfer Figure 16.4-1 Block Transfer DMA stop DENB=>0 DENB=1 Activation request wait Reload enable Activation request Load the initial address, transfer count, and number of blocks...
Page 541 ■ Operation Flowchart for Burst Transfer Figure 16.4-2 Burst Transfer DMA stop DENB=>0 DENB=1 Activation request wait Reload enable Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1...
Page 542 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Operation Flowchart for Demand Transfer Figure 16.4-3 Demand Transfer DMA stop DENB=>0 DENB=1 None Activation request wait Reload enable Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer...
Page 543: Data Path
16.5 Data Path This section shows the flow of data during different types of transfer operation. ■ Flow of Data During 2-Cycle Transfer Figure 16.5-1 to Figure 16.5-6 show the flow of data during 2-cycle transfer. Figure 16.5-1 External Area → External Area Transfer External area =>...
Page 544 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.5-3 External Area → Internal I/O Area Transfer External area => built-in I/O area transfer MB91xxx MB91xxx DMAC DMAC Read cycle Write cycle I-bus I-bus X-bus X-bus Bus controller Bus controller D-bus Data buffer D-bus Data buffer F-bus...
Page 545 Figure 16.5-6 Internal RAM Area → Internal I/O Area Transfer Internal RAM area => built-in I/O area transfer MB91xxx MB91xxx DMAC DMAC Write cycle Read cycle I-bus I-bus X-bus X-bus Bus controller Bus controller D-bus D-bus Data buffer Data buffer F-bus F-bus ■...
Page 546 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.5-8 Fly-by Transfer (I/O → Memory) Fly-by transfer (I/O to memory) MB91xxx DMAC Memory write by WR or CSx Read cycle I-bus X-bus Bus controller D-bus Data buffer I/O read by WR or DACK F-bus Fly-by transfer by SDRAM disabled...
Page 547: Dma External Interface
16.6 DMA External Interface This section describes the DMA external interface. Note: The MB91F353A/351A/352A/353A do not have a DMA external interface. ■ Overview of DMA External Interface Operation DMA ch0 to ch2 have DMA-dedicated pins (DREQ, DACK, and DEOP). • DREQ DREQ is a DMA transfer request input pin used to execute demand transfer.
Page 548 CHAPTER 16 DMA CONTROLLER (DMAC) ● Fly-by transfer (I/O → memory transfer and transfer count = 3) Figure 16.6-2 shows a simple waveform for fly-by transfer (I/O → memory transfer and transfer count = Figure 16.6-2 Simple Waveform for Fly-by Transfer (I/O → Memory Transfer and Transfer Count = 3) A24 to A0 IORD DACK...
Page 549 Figure 16.6-4 DREQx Edge Request (2-Cycle Transfer) MCLK DREQ A24 - 0 #RD1 #WR1 #RD2 #WR2 DEOP operation transfer 3 cycles or more Next request after DEOP output Figure 16.6-5 DREQx Level Request (2-Cycle Transfer) MCLK DREQ A24 - 0 #RD1 #WR1 #RD2...
Page 550 CHAPTER 16 DMA CONTROLLER (DMAC) ■ FR30 Compatible Mode of DACK The FR30-compatible mode of this DACK sets the DACK timing to the same timing as that of FR30 family DMA. Use the PFR register corresponding to the DACK pin to set FR30-compatible mode. Match the PFR setting to the transfer mode (fly-by or 2-cycle) of the corresponding DMA channel.
Page 551: Chapter 17 Flash Memory
CHAPTER 17 FLASH MEMORY This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations. 17.1 Outline of Flash Memory 17.2 Flash Memory Registers 17.3 Explanation of Flash Memory Operation 17.4 Automatic Algorithm of Flash Memory 17.5 Writing to and Erasing Flash Memory...
Page 552: Outline Of Flash Memory
The flash memory employed is an internal 256K bytes/128K bytes flash memory that operates on 3.3 V. The flash memory employed here is the same (except for the capacity and sector structure) as the Fujitsu MBM29LV400C flash memory. The flash memory supports writing with a device-external ROM writer.
Page 553 ■ Block Diagram of Flash Memory Figure 17.1-1 shows a block diagram of flash memory. Figure 17.1-1 Block Diagram of Flash Memory Detection of rising RDY/BUSYX edge RESETX 256 KB/128KB Generation of BYTEX control signal flash memory (2 installed) FA17 to 0 DI15 to 0 D031 to 0 Address buffer Data buffer...
Page 554 CHAPTER 17 FLASH MEMORY Figure 17.1-3 Memory Map of MB91F356B Flash Memory Flash memory mode CPU mode 0000_0000 I/O, etc 000C_0000 32-bit 32-bit Internal Internal 256K bytes ROM 2 ROM 1 8-bit/16-bit 0010_0000 0010_0000 Access is not allowed 0011_0000 64K bytes Internal ROM 1 0012_0000 Access is not allowed...
Page 555 ■ Sector Address Table of Flash Memory [Flash memory sector maps] The flash memory sector maps are shown below. • CPU mode (MB91F355A,MB91F353A and MB91F357B) 0xFFFFF SAA9(16K) SAA4(16K) SAB9(16K) SAB4(16K) 0xF0000 0xEF000 SAA8(8K) SAA3(8K) SAB8(8K) SAB3(8K) 0xE8000 0xE7FFF SAA7(8K) ROM1 SAA2(8K) ROM2 SAB7(8K)
Page 556 CHAPTER 17 FLASH MEMORY • FLASH mode (Accessing to SAA0, SAA5, SAB0, and SAB5 is disabled.) (MB91F356B) 0x13FFFF SAB9(16K) SAA9(16K) 0x13C000 0x13BFFF SAB8(8K) SAA8(8K) 0x13A000 0x139FFF SAB7(8K) SAA7(8K) 0x138000 0x137FFF SAB6(32K) SAA6(32K) 0x130000 0x12FFFF 0x120000 ROM2 ROM1 0x11FFFF SAA4(16K) SAB4(16K) 0x11C000 0x11BFFF SAA3(8K)
Page 557: Flash Memory Registers
17.2 Flash Memory Registers This section describes the configuration and functions of the registers used for flash memory. ■ Overview of Flash Memory Registers There are the two following types of flash memory registers: • FLCR: Flash control/status register (CPU mode) •...
Page 558: Flash Control/Status Register (Flcr) (Cpu Mode)
CHAPTER 17 FLASH MEMORY 17.2.1 Flash Control/Status Register (FLCR) (CPU mode) The flash control/status register (FLCR) (CPU mode) indicates the operating status of flash memory. The FLCR controls writing to flash memory. The FLCR can be accessed only in CPU mode. Do not use read modify write instructions to access this register.
Page 559 [Bit 3] RDY This bit indicates the operation status of the automatic algorithm (write/erase). When this bit is set to "0," writing or erasure is in progress with the automatic algorithm and no write and erase command can be accepted. Moreover, data cannot be read from any address in flash memory. The read data indicates the flash memory status as listed in the table below.
Page 560 CHAPTER 17 FLASH MEMORY [Bit 1] WE (Write Enable) This bit controls the writing of data and commands to flash memory in CPU mode. When this bit is "0", data and commands cannot be written to flash memory. In addition, data can be read from flash memory at faster speeds (32-bit, 16-bit, and 8-bit access are enabled).
Page 561: Flash Memory Wait Register (Flwc)
17.2.2 Flash Memory Wait Register (FLWC) The flash memory wait register (FLWC) controls the wait status of flash memory access in CPU mode. ■ Configuration of the Flash Memory Wait Register (FLWC) The configuration of the flash memory wait register (FLWC) is shown below. Address : 00007004 FAC1 FAC0...
Page 562 CHAPTER 17 FLASH MEMORY [Bits 2 to 0] WTC2, WTC1, and WTC0 (wait cycle bits) These bits control the wait status of flash memory. VDD = 3.0V@50MHz VDD = 2.7V@50MHz Wait WTC2 WTC1 WTC0 count WE bit 0 WE bit 1 WE bit 0 WE bit 1 Setting not...
Page 563: Explanation Of Flash Memory Operation
17.3 Explanation of Flash Memory Operation This section describes flash memory operation. ■ Flash Memory Access Modes The following two types of access mode are available for the FR-CPU: • ROM mode: One word (32 bits) can be read but not written in a single cycle. •...
Page 564 CHAPTER 17 FLASH MEMORY ■ FR-CPU Programming Mode (16 Bits, Read/Write Enabled) This mode enables data to be written and erased. As one word (32 bits) cannot be accessed in one cycle, program execution in flash memory is disabled in this mode. •...
Page 565: Automatic Algorithm Of Flash Memory
17.4 Automatic Algorithm of Flash Memory This section describes the command sequence of the flash memory automatic algorithm, the method used to check the operating status of the automatic algorithm, and writing to and erasing flash memory. ■ Overview of the Flash Memory Automatic Algorithm The flash memory automatic algorithm can be started using a read/reset, write, chip erase, or sector erase command.
Page 566: Command Sequence
CHAPTER 17 FLASH MEMORY 17.4.1 Command Sequence This section describes the command sequence for starting the automatic algorithm. ■ Automatic Algorithm Command Sequence At the start of the automatic algorithm, one to six half-words (16 bits) are written continuously. This data is called the command.
Page 567 ■ Read/Reset Command Set flash memory into read/reset mode. The flash memory remains in reading state until another command is entered. When the power is turned on, flash memory is automatically set to the read or reset state. In this case, data can be read without a command of the automatic algorithm.
Page 568 CHAPTER 17 FLASH MEMORY ■ Sector Erase The sector erase command sequence is executed in six access cycles. First, two "unlock" cycles are executed, then a "Setup" command is written. After two more "unlock" cycles, the sector erase command is entered in the sixth cycle for starting the sector erase operation.
Page 569 ■ Temporarily Stop Erase The temporarily stop erase command temporarily stops the automatic algorithm in flash memory when the user is erasing the data of a sector, thereby making it possible to write data to and read data from the other sectors that is not subject to the erase operation.
Page 570: Checking The Automatic Algorithm Operating Status
CHAPTER 17 FLASH MEMORY 17.4.2 Checking the Automatic Algorithm Operating Status Flash memory is provided with hardware to indicate the internal operation status of flash memory and the completion of write/erase operations in the automatic algorithm. The automatic algorithm can check the operating status of internal flash memory using the hardware sequence flag described below.
Page 571 Table 17.4-2 Statuses of the Hardware Sequence Flag Status DPOLL TOGGLE TLOVER SETIMR TOGGL2 Executing Automatic write operation Reverse Toggle data Automatic erase operation Toggle Toggle Temporary Temporary erase Toggle* erase stop stop and read (from mode sectors in temporary erase stop) Temporary erase Data...
Page 572 CHAPTER 17 FLASH MEMORY [bit 7] DPOLL (Data polling flag) This flag is used with the data polling function to report that the automatic algorithm is being executed or terminated. ● Automatic write operation status When read access is performed while the automatic write algorithm is being executed, flash memory outputs the inversion of bit 7 of the last data written regardless of the address indicated by the address signal.
Page 573 ● Temporary sector erase stop status When a read operation is performed during a temporary sector erase stop operation, flash memory outputs "1" if the address indicated by the address signal is included in the sector in erase state. If the address is not included in the sector in erase state, flash memory outputs the data of bit 6 (DATA:6) of the read value at the address indicated by the address signal.
Page 574 CHAPTER 17 FLASH MEMORY ● Sector erase operation status When a read operation is performed during a temporary sector erase stop operation, flash memory outputs "1" if the address indicated by the address signal is included in the sector that is subject to the erase operation.
Page 575: Writing To And Erasing Flash Memory
17.5 Writing to and Erasing Flash Memory This section explains how to issue a command to start the automatic algorithm for a read/reset, write, chip erase, sector erase, temporary sector erase stop, or sector erase restart operation in flash memory. ■...
Page 576: Read/Reset Status
CHAPTER 17 FLASH MEMORY 17.5.1 Read/Reset Status This section explains how to issue read/reset commands to set flash memory into read/ reset status. ■ Reading/Resetting Flash Memory The read/reset operation becomes possible by continuously sending read/reset commands (listed in the command sequence table) to target sectors in flash memory.
Page 577: Data Writing
17.5.2 Data Writing This section explains how to issue a write command to write data to flash memory. ■ Writing Data to Flash Memory The automatic data write algorithm can be started by continuously sending write commands (listed in the command sequence table) to target sectors in flash memory.
Page 578 CHAPTER 17 FLASH MEMORY Figure 17.5-1 Example of Write Procedure Writing start Enable writing to flash memory with WE (bit 1) in FLCR. Write command sequence AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) AAAAA (ROM1)/AAAAE (ROM2) Write address write data Read internal address. Next address Data polling (DPOLL) Time limit (TLOVER)
Page 579: Data Erasure (Chip Erasure)
17.5.3 Data Erasure (Chip Erasure) This section explains how to issue chip erase commands to erase all items of data in flash memory. ■ Erasing Data (Chip Erase) From Flash Memory All items of data can be erased from flash memory by continuously sending chip erase commands (listed in the command sequence table) to target sectors in flash memory.
Page 580: Data Erasure (Sector Erasure)
CHAPTER 17 FLASH MEMORY 17.5.4 Data Erasure (Sector Erasure) This section explains how to issue sector erase commands to erase specified sectors in flash memory. Erasure in sector units is possible and two or more sectors can be specified with this command. Specified sectors can be erased from flash memory by continuously sending sector erase commands (listed in the command sequence table) to the sectors in the flash memory.
Page 581 Figure 17.5-2 Sector Erase Procedure Erase start Erase start Enable erasure in flash memory with WE (bit 1) in FLCR. Sector erase timer (SETIMR) Erase command sequence AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) AAAAA (ROM1)/AAAAE (ROM2) AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) Enter code (30 ) to sector to be erased.
Page 582: Temporary Sector Erase Stop
CHAPTER 17 FLASH MEMORY 17.5.5 Temporary Sector Erase Stop This section explains how to issue temporary sector erase stop commands to temporarily stop a sector erase operation in flash memory. Data can be read from a sector not being erased by using this command. ■...
Page 583: Sector Erase Restart
17.5.6 Sector Erase Restart This section explains how to issue sector erase restart commands to restart a temporarily stopped sector erase operation in flash memory. ■ Restarting Sector Erase in Flash Memory To restart a temporarily stopped sector erase operation, send the sector erase restart command listed in Table 17.4-1 to the target sector in flash memory.
Page 584 CHAPTER 17 FLASH MEMORY...
Page 585 AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. 18.1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection 18.2 Pins Used for Fujitsu Standard Serial Onboard Writing 18.3 Examples of Serial Programming Connection 18.4 System Configuration of Flash Microcontroller Programmer 18.5 Other Precautionary Information...
Page 586: Chapter 18 Mb91F355A/F353A/F356B/F357B Serial Programming Connection
■ Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection Fujitsu standard serial onboard writing uses the AF220/AF210/AF120/AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation. Either a program operating in single-chip mode or a program operating in internal ROM external bus mode is selected to write.
Page 587: Pins Used For Fujitsu Standard Serial Onboard Writing
This section describes pins used for Fujitsu standard serial onboard writing. ■ Pins Used for Fujitsu Standard Serial Onboard Writing Table 18.2-1 shows the functions of pins used for Fujitsu standard serial onboard writing. Table 18.2-1 Function of Pins Used for Fujitsu Standard Serial Onboard Writing...
Page 588: Examples Of Serial Programming Connection
CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION 18.3 Examples of Serial Programming Connection This section shows examples of serial programming connections. ■ Examples of Serial Programming Connections Figure 18.3-1 and Figure 18.3-2 show examples of serial programming connections. Figure 18.3-1 Example of Serial Programming Connection for MB91F353A User system AF200 Flash Microcontroller...
Page 589 Figure 18.3-2 Example of Serial Programming Connection for MB91F355A, MB91F356B and MB91F357B User system AF200 MB91F355A (LQFP-176), Flash Microcontroller MB91F356B (LQFP-176), Programmer Connector DX10-28S MB91F357B (LQFP-176) Pull-UP or Pull-DOWN connection selected by the MODE. (19) TAUX3 MD2 138 MD1 139 TMODE MD0 140 (12)
Page 590: System Configuration Of Flash Microcontroller Programmer
AZ221 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu F MC-16LX flash microcontroller control module AZ290 Remote controller 2M bytes PC Card (Option) FLASH memory capacity up to 128K bytes supported 4M bytes PC Card (Option) FLASH memory capacity of up to 512K bytes supported...
Page 591: Other Precautionary Information
18.5 Other Precautionary Information This section shows notes of MB91F355A/F353A/F356B/F357B serial programming connections. ■ Notes of MB91F355A/F353A/F356B/F357B Serial Programming Connections ● Oscillation Clock Frequency For write operations on flash memory, the range of the oscillation clock frequency that can be used is between 10.0 MHz and 12.5 MHz.
Page 592 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION...
Page 593: Access Restriction Functions
CHAPTER 19 DATA INTERNAL RAM/ INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS This chapter describes the access restriction functions for data internal RAM/instruction internal RAM. 19.1 Overview 19.2 Explanation of Registers 19.3 Explanation of Operation...
Page 594: Chapter 19 Data Internal Ram/Instruction Internal Ram
CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS 19.1 Overview The access restriction functions limit the available area of the internal RAM area installed on the device. In initial device state, the available area is limited to 4K bytes. To use more than 4K bytes requires that the settings of these functions be changed.
Page 595: Explanation Of Registers
19.2 Explanation of Registers This section describes the registers used by the data internal RAM/instruction internal RAM access restriction functions. ■ DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) The configuration of the data RAM limit control register is shown below: Address : 00000390 (R/W) Initial value...
Page 596 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS ■ FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) The configuration of the instruction RAM limit control register is shown below: Address : 00000280 (R/W) Initial value [Bits 7 to 2] Reserved bits These bits are reserved bits.
Page 597: Explanation Of Operation
19.3 Explanation of Operation This section describes the operation of the data internal RAM/instruction internal RAM access restriction functions. ■ Operation of the Data Internal RAM/Instruction Internal RAM Access Restriction Functions These functions limit the available area of the internal RAM area installed on the device. Writing to RAM area that has been specified as unavailable is not allowed.
Page 598 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS...
Page 599: Appendix
APPENDIX The appendixes describe the I/O map, interrupt vectors, and pin states in each CPU state and provide instruction lists. APPENDIX A I/O Map APPENDIX B Interrupt Vector APPENDIX C Pin States in Each CPU State APPENDIX D Instruction Lists...
Page 600: Appendix A I/O Map
APPENDIX APPENDIX A I/O Map The registers of the peripheral functions installed on the device are assigned the addresses listed in Table A-1. ■ Reading the I/O Map register block address 000000 PDR0[R/W]B PDR1[R/W]B PDR2[R/W]B PDR3[R/W]B T-unit XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Port Data Register Read/write attribute...
Page 601 APPENDIX A I/O Map ■ Correspondence between the Memory Space Area and Peripheral Resource Registers Table A-1 I/O Map (1 / 10) Register Address Block PDR2[R/W]B PDR3[R/W]B 000000 ________ ________ XXXXXXXX XXXXXXXX PDR4[R/W]B PDR5[R/W]B PDR6[R/W]B 000004 ________ XXXXXXXX XXXXXXXX XXXXXXXX T-unit port data PDR8[R/W]B PDR9[R/W]B...
Page 602 APPENDIX Table A-1 I/O Map (2 / 10) Register Address Block TMRLR2[W]H,W TMR2[R]H,W 000058 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX Reload timer 2 TMCSR2[R/W]B,H,W 00005C ________ ----000000000000 SIDR0[R] SSR0[R/W]B,H,W SCR0[R/W]B,H,W SMR0[R/W]B,H,W 000060 SORR0[W]B,H,W UART0 00001000 00000100 00--0--- XXXXXXXX UTIM0[R]H(UTIMR0[W]H) DRCL0[W]B UTIMC0[R/W]B 000064 U-timer/UART0 0000000000000000 -------- 000001 SIDR1[R]...
Page 603 APPENDIX A I/O Map Table A-1 I/O Map (3 / 10) Register Address Block RCR0[W]B,H,W UDCR0[R]B,H,W RCR1[W]B,H,W UDCR1[R]B,H,W 0000B0 00000000 00000000 00000000 00000000 8/16-bit Up/ CCRH0[R/W]B,H,W CCRL0[R/W]B,H,W CSR0[R/W]B,H,W Down counter 0, 0000B4 ________ 00000000 00001000 00000000 CCRH1[R/W]B,H,W CCRL1[R/W]B,H,W CSR1[R/W]B,H,W 0000B8 ________ 00000000 00001000...
Page 604 APPENDIX Table A-1 I/O Map (4 / 10) Register Address Block PTMR0[R]H,W PCSR0[W]H,W 000120 1111111111111111 XXXXXXXXXXXXXXXX PPG0 PDUT0[W]H,W PCNH0[R/W]B,H,W PCNL0[R/W] 000124 XXXXXXXXXXXXXXXX 00000000 000000X0 PTMR1[R]H,W PCSR1[W]H,W 000128 1111111111111111 XXXXXXXXXXXXXXXX PPG1 PDUT1[W]H,W PCNH1[R/W]B,H,W PCNL1[R/W]B,H,W 00012C XXXXXXXXXXXXXXXX 00000000 00000000 PTMR2[R]H,W PCSR2[W]H,W 000130 1111111111111111 XXXXXXXXXXXXXXXX PPG2...
Page 605 APPENDIX A I/O Map Table A-1 I/O Map (5 / 10) Register Address Block DMACA3[R/W]B,H,W 000218 000000000000XXXXXXXXXXXXXXXXXXXX DMACB3[R/W]B,H,W 00021C 0000000000000000XXXXXXXXXXXXXXXX DMACA4[R/W]B,H,W DMAC 000220 000000000000XXXXXXXXXXXXXXXXXXXX DMACB4[R/W]B,H,W 000224 0000000000000000XXXXXXXXXXXXXXXX ________ 000228 00022C ________ Reserved 00023C DMACR[R/W]B 000240 DMAC 0XX00000XXXXXXXXXXXXXXXXXXXXXXXX 000244 ________ Reserved 00027C FRLR[R/W]B,H,W Limit on F-Bus...
Page 606 APPENDIX Table A-1 I/O Map (6 / 10) Register Address Block PFRH[R/W]B PFRI[R/W]B PFRG[R/W]B 000410 ________ --00-00- --00-00- --00-00- R-bus port PFRL[R/W]B PFRM[R/W]B PFRN[R/W]B function 000414 ________ ------00 --00-00- --000000 register PFRO[R/W]B PFRP[R/W]B 000418 ________ 00000000 ----0000 ________ 00041C Reserved PCRH[R/W]B PCRI[R/W]B PCRG[R/W]B...
Page 607 APPENDIX A I/O Map Table A-1 I/O Map (7 / 10) Register Address Block WPCR[R/W]B 00048C ________ ________ ________ Watch timer 00---000 Main clock OSCR[R/W]B oscillation 000490 ________ ________ ________ 00---000 stabilization wait timer RSTOP0[W]B RSTOP1[W]B RSTOP2[W]B RSTOP3[W]B Peripheral stop 000494 00000000 00000000...
Page 608 APPENDIX Table A-1 I/O Map (8 / 10) Register Address Block ASR1[R/W]H,W ACR1[R/W]B,H,W 000644 0000000000000000 XXXXXXXXXXXXXXXX ASR2[R/W]H,W ACR2[R/W]B,H,W 000648 0000000000000000 XXXXXXXXXXXXXXXX ASR3[R/W]H,W ACR3[R/W]B,H,W 00064C 0000000000000000 XXXXXXXXXXXXXXXX ASR4[R/W]H,W ACR4[R/W]B,H,W 000650 0000000000000000 XXXXXXXXXXXXXXXX ASR5[R/W]H,W ACR5[R/W]B,H,W 000654 0000000000000000 XXXXXXXXXXXXXXXX ASR6[R/W]H,W ACR6[R/W]B,H,W 000658 0000000000000000 XXXXXXXXXXXXXXXX ASR7[R/W]H,W ACR7[R/W]B,H,W...
Page 609 APPENDIX A I/O Map Table A-1 I/O Map (9 / 10) Register Address Block ESTS0[R/W] ESTS1[R/W] ESTS2[R] 000B00 ________ X0000000 XXXXXXXX 1XXXXXXX ECTL0[R/W] ECTL1[R/W] ECTL2[W] ECTL3[R/W] 000B04 0X000000 00000000 000X0000 00X00X11 ECNT0[W] ECNT1[W] EUSA[W] EDTC[W] 000B08 XXXXXXXX XXXXXXXX XXX00000 0000XXXX EWPT[R] 000B0C ________...
Page 610 APPENDIX Table A-1 I/O Map (10 / 10) Register Address Block 000B70 ________ Reserved 000BFC Interrupt control 000C00 Test register (access is not allowed.) unit 000C04 Test register (access is not allowed.) R-bus test 000C14 000C18 ________ Reserved 000FFC DMASA0[R/W]W 001000 XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0[R/W]W...
Page 611 APPENDIX A I/O Map *1: This is a test register. Access is not allowed. *2: Immediately after release of a reset, the available internal RAM area is limited by the functions described in CHAPTER 19 "DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS". In addition, if the setting for available area is rewritten, insert at least one NOP instruction immediately after that processing.
Page 612: Appendix B Interrupt Vector
APPENDIX APPENDIX B Interrupt Vector Table B-1 shows the interrupt vector table, which gives the interrupt sources and interrupt vector/interrupt control register allocations for the MB91350A. ■ Interrupt Vectors Table B-1 Interrupt Vector Table (1 / 3) Interrupt number TBR default Interrupt source Interrupt level Offset...
Page 613 APPENDIX B Interrupt Vector Table B-1 Interrupt Vector Table (2 / 3) Interrupt number TBR default Interrupt source Interrupt level Offset address Decimal Hexadecimal 000FFF6C DMAC3 (end or error) ICR20 000FFF68 DMAC4 (end or error) ICR21 000FFF64 ICR22 000FFF60 ICR23 000FFF5C ICR24 UART4 (reception completed)
Page 614 APPENDIX Table B-1 Interrupt Vector Table (3 / 3) Interrupt number TBR default Interrupt source Interrupt level Offset address Decimal Hexadecimal Reserved for system 000FFEC0 Used in INT instruction 000FFEBC 000FFC00 *1: The MB91F353A/351A/352A/353A do not have this interrupt source. *2: The MB91F353A/351A/352A/353A do not have UART4 (transmission completed).
Page 615: Appendix C Pin States In Each Cpu State
APPENDIX C Pin States in Each CPU State APPENDIX C Pin States in Each CPU State Table C-1 explains the terms used in the pin state lists. Table C-2 and Table C-3 list the pin states in each CPU state. ■...
Page 616 APPENDIX ■ Pin States in Each CPU State Table C-2 Pin States in External Bus Mode (1 / 3) At initialization (INIT) Stop mode, watch mode Initial value Spec-ified- Port Sleep mode, sub- function Bus open (BGRNT) name clock sleep mode marks External Function...
Page 617 APPENDIX C Pin States in Each CPU State Table C-2 Pin States in External Bus Mode (2 / 3) At initialization (INIT) Stop mode, watch mode Initial value Spec-ified- Port Sleep mode, sub- function Bus open (BGRNT) name clock sleep mode marks External Function...
Page 618 APPENDIX Table C-2 Pin States in External Bus Mode (3 / 3) At initialization (INIT) Stop mode, watch mode Initial value Spec-ified- Port Sleep mode, sub- function Bus open (BGRNT) name clock sleep mode marks External Function name Internal ROM HIZ=0 HIZ=1 ROM mode...
Page 619 APPENDIX C Pin States in Each CPU State Table C-3 Pin States in Single-Chip Mode (1 / 2) At initialization (INIT) Stop mode, watch mode Initial value Specified-func- Sleep mode, sub- Pin No. Port name Re-marks tion name clock sleep mode Function HIZ=0 HIZ=1...
Page 620 APPENDIX Table C-3 Pin States in Single-Chip Mode (2 / 2) At initialization (INIT) Stop mode, watch mode Initial value Specified-func- Sleep mode, sub- Pin No. Port name Re-marks tion name clock sleep mode Function HIZ=0 HIZ=1 Internal ROM name mode vector (MD2 to 0 = 000) Hi-Z output/...
Page 621: Appendix D Instruction Lists
APPENDIX D Instruction Lists APPENDIX D Instruction Lists Table D-1 explains the addressing mode symbols. Figure D-1 shows the instruction format. Table D-2 to Table D-21 list the FR family instructions by instruction type. ■ How to Read the Instruction Lists Mnemonic Type CYCLE...
Page 622 APPENDIX ■ Addressing Mode Symbols Table D-1 explains the addressing mode symbols. Table D-1 Explanation of Addressing Mode Symbols Symbol Meaning Register direct (R0 to R15, AC, FP, SP) Register direct (R0 to R15, AC, FP, SP) Register direct (R13, AC) Register direct (program status register) Register direct (TBR, RP, SSP, USP, MDH, MDL) Register direct (CR0 to CR15)
Page 623 APPENDIX D Instruction Lists ■ Instruction Format Figure D-1 shows the instruction format. Figure D-1 Instruction Format 16 bit i8/08 u4/m4 ADD, ADDN, CMP, LSL, LSR, and ASR instructions only s5/u5 * C ' u8/rel8/dir/reglist SUB-OP rel11...
Page 624 APPENDIX Table D-2 Addition and Subtraction Mnemonic Type CYCLE NZVC Operation Remarks → ADD Rj, Ri CCCC Ri + Rj → *ADD #s5, Ri C’ CCCC The assembler treats the highest- Ri + s5 order bit as the sign. → ADD #u4, Ri CCCC Zero extension...
Page 625 APPENDIX D Instruction Lists Table D-5 Bit Manipulation Mnemonic Type CYCLE NZVC Operation Remarks BANDL #u4, @Ri 1+2a ---- (Ri)&=(0xF0+u4) Low-order 4 bits are manipulated. BANDH #u4, @Ri 1+2a ---- (Ri)&=((u4<<4)+0x0F) High-order 4 bits are manipulated. ---- (Ri)&=u8 *BAND #u8, @Ri BORL #u4, @Ri 1+2a ----...
Page 626 APPENDIX Table D-7 Shift Mnemonic Type CYCLE NZVC Operation Remarks → LSL Rj, Ri CC-C Logical shift Ri << Rj → *LSL #u5, Ri (u5:0 to 31) C’ CC-C Ri << u5 → LSL #u4, Ri CC-C Ri << u4 →...
Page 627 APPENDIX D Instruction Lists Table D-10 Memory Store Mnemonic Type CYCLE NZVC Operation Remarks → STRi, @Rj ---- Word (Rj) → STRi, @(R13,Rj) ---- Word (R13+Rj) → STRi, @(R14,disp10) ---- Word (R14+disp10) → STRi, @(R15,udisp6) ---- (R15+udisp6) → STRi, @-R15 17-0 ---- R15-=4,Ri...
Page 628 APPENDIX Table D-12 Normal Branch (No Delay) Mnemonic Type CYCLE NZVC Operation Remarks → JMP @Ri 97-0 ---- → CALL label12 ---- PC+2 RP , → PC+2+(label12-PC-2) → → CALL @Ri 97-1 ---- PC+2 RP ,Ri → 97-2 ---- Return →...
Page 629 APPENDIX D Instruction Lists Table D-13 Delayed Branch Mnemonic Type CYCLE NZVC Operation Remarks → JMP:D @Ri 9F-0 ---- → → CALL:D ---- PC+4 RP,PC+2+(label12-PC-2) → → label12 9F-1 ---- PC+4 RP,Ri CALL:D @Ri → RET:D 9F-2 ---- Return → BRA:D label9 ---- PC+2+(label9-PC-2)
Page 630 APPENDIX Table D-14 Other Instructions Mnemonic Type CYCLE NZVC Operation Remarks 9F-A ---- No change → ANDCCR #u8 CCCC CCR and u8 → ORCCR #u8 CCCC CCR or u8 → STILM #u8 ---- ILM immediate set ---- R15 += s10 ADD SP instruction ADDSP #s10 →...
Page 631 APPENDIX D Instruction Lists Table D-15 20-Bit Normal Branch Macro Instructions Mnemonic Operation Remarks → *CALL20 label20,Ri Ri: Temporary register (See Reference 1) Address of the next instruction → label20 → *BRA20 label20,Ri Ri: Temporary register (See Reference 2) label20 →...
Page 632 APPENDIX Table D-16 20-Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks → *CALL20:D label20,Ri Ri: Temporary register (See Reference 1) Address of the next instruction → label20 → *BRA20:D label20,Ri Ri: Temporary register (See Reference 2) label20 → *BEQ20:D label20,Ri Ri: Temporary register (See Reference 3) if(Z==1) then label20 ↑...
Page 633 APPENDIX D Instruction Lists Table D-17 32-Bit Normal Branch Macro Instructions Mnemonic Operation Remarks → *CALL32 label32,Ri Ri: Temporary register (See Reference 1) Address of the next instruction → label20 → *BRA32 label32,Ri Ri: Temporary register (See Reference 2) label32 →...
Page 634 APPENDIX Table D-18 32-Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks → *CALL32:D label32,Ri Ri: Temporary register (See Reference 1) Address of the next instruction → label20 → *BRA32:D label32,Ri Ri: Temporary register (See Reference 2) label32 → *BEQ32:D label32,Ri Ri: Temporary register (See Reference 3) if(Z==1) then label20 ↑...
Page 635 APPENDIX D Instruction Lists Table D-19 Direct Addressing Mnemonic Type CYCLE NZVC Operation Remarks → DMOV @dir10, R13 ---- Word (dir10) → DMOV R13, @dir10 ---- Word (dir10) → DMOV @dir10, @R13+ ---- Word (dir10) (R13),R13+=4 → DMOV @R13+, @dir10 ---- Word (R13)
Page 636 APPENDIX Table D-21 Coprocessor Control Instructions Mnemonic Type CYCLE NZVC Operation Remarks COPOP #u4, #u8, CRj, Cri 9F-C ---- Operation instruction → COPLD #u4, #u8, Rj, Cri 9F-D 1+2a ---- No error trap → COPST #u4, #u8, CRj, Ri 9F-E 1+2a ---- →...
Page 637: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 638 INDEX Index Numerics 16-bit Reload Timer Register 16-bit Reload Timer Registers......287 0 Detection 16-bit Timer Register 0 Detection ............360 16-bit Timer Register (TMR) ......291 0 Detection Data Register (BSD0) ..... 358 2-Cycle Transfer 0 Detection Data Register 2-Cycle Transfer (External ->...
Page 639 INDEX Another Transfer Request If Another Transfer Request Occurs During Block A/D Converter Transfer ..........521 A/D Converter ............. 4 Arbitrary Width A/D Converter Registers........366 Up/Down Counting with an Arbitrary Width Block Diagram of the A/D Converter ....365 when the Reload and Compare Functions are Features of the A/D Converter......
Page 640 INDEX Basic Condition Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1)......251 Basic Conditions for Starting External Access Using Prefetch ..........218 Block Diagram of the 8-bit D/A Converter ..381 Block Diagram of the A/D Converter....365 Basic Programming Model Block Diagram of the Bit Search Module ...
Page 641 INDEX Burst 2-Cycle Transfer CDCR Burst 2-Cycle Transfer ........497 Serial I/O Prescaler Control Register (CDCR) ............417 Burst Fly-by Transfer Burst Fly-by Transfer ........498 Change Point Detection Change Point Detection........361 Burst Length Change Point Detection Data Register Burst Length Setting and Prefetch Efficiency ............
Page 642 INDEX CLKT Configuration of the Chip Select Enable Register External Bus Clock (CLKT) ......109 (CSER) ..........183 Configuration of the Flash Control/Status Register Clock Control Register (FLCR) (CPU Mode) ......540 Clock Control Register (ICCR)......455 Configuration of the Flash Memory Wait Register Clock Controller (FLWC) ..........
Page 643 INDEX DADR2 (D/A Data Register 2) ......382 List of Registers of the 8/16-bit Up/Down Counters/Timers ......... 248 DACK Operating States of the Counter ......295 FR30 Compatible Mode of DACK .....532 Other Interval Timers and Counters ....... 4 Timing of DACK Pin Output ......520 Overview of the 8/16-bit Up/Down DACR Counters/Timers .........
Page 644 INDEX Limitations on Operation with Delay Slot ..... 69 Base Clock Division Setting Register 1 Operation with Delay Slot ........68 (DIVR1) ..........126 Operation without Delay Slot ......71 DLYI Bit Delayed Interrupt DLYI Bit of DICR ........... 355 Overview of the Delayed Interrupt Module ..
Page 645 INDEX DMAC Interrupt Control Output ELVRn Interrupts That Enable DMAC Interrupt Control Bit Configuration of External Level Register (ELVRn) Outputs ..........514 ............347 DMAC Interrupt Source Clear Register Emulator DMAC Interrupt Source Clear Register (SRCL) Emulator and Monitor Debuggers ......43 ............
Page 646 INDEX External Bus Access External Transfer Request Pin External Bus Access ......... 193 External Transfer Request Pin ......496 External Bus Clock External Wait External Bus Clock (CLKT) ......109 With External Wait (TYP[3:0]=0101 ,AWR=1008 )..216 External Bus Interface Without External Wait Block Diagram of the External Bus Interface ..
Page 647 HRCL ............578 Bit Configuration of the Hold Request Cancellation Fujitsu Standard Serial Onboard Request Register (HRCL) .....331 Pins Used for Fujitsu Standard Serial Onboard HRCR Writing ..........569 Example of Using the Hold Request Cancellation Function Request Function (HRCR)....338 Functions of the DMACA0 to 4 Bits ....
Page 648 INDEX C Bus Interface (400 kbps Supported) ....5 2-Cycle Transfer (I/O -> External) C Interface Registers ........441 (TYP[3:0] = 0000 , AWR = 0008 , and )........227 C Interface Registers ..... 444 IOWR = 00 Overview of the I 2-Cycle Transfer C Interface Register (The Timing is the Same for Internal RAM...
Page 649 INDEX Initializing Internal Architecture Initializing the Divide-By Rate ......110 Features of the Internal Architecture.....50 Overview of Internal Architecture ......49 Input Capture Structure of the Internal Architecture....51 16-bit Input Capture Operation ......430 External Input Pin Corresponding to Each Input Internal Memory Capture Channel .........
Page 650 INDEX IPCP Interrupts That Enable DMAC Interrupt Control Outputs ..........514 Input Capture Data Register (IPCP0 to IPCP3) Level Mask for Interrupt and NMI ....... 74 ............428 Main Clock Oscillation Stabilization Wait Timer Interrupt ..........152 [Bits 28 to 24] IS4 to 0 (Input Select): Major Functions of the Interrupt Controller..
Page 651 INDEX Mode 1 Example of System Construction Main Clock (Using Mode 1) ........407 Wait Time after Switching From the Subclock to the Mode Pin Main Clock ........107 Mode Pins............92 Main Clock Oscillation Stabilization Wait Timer Mode Pins (MD0 to MD2)........33 Block Diagram of the Main Clock Oscillation Mode Register Stabilization Wait Timer......
Page 652 INDEX Note Operation of the Main Clock Oscillation Stabilization Note for the Case of Using No Subclock....33 Wait Timer......... 153 Note on Operating in PLL Clock Mode ....33 Operation of the Watch Timer ......148 Note on Specifying Two or More Sectors ... 562 Operation of Undefined Instruction Exception ..
Page 653 INDEX Output Compare Module Register PCSR Output Compare Module Registers ....432 Configuration of PPG Cycle Setting Register (PCSR) ..........307 Output Control Register Output Control Register (OCS0 to OCS7) ..434 Port Data Registers (PDR) .........234 Output Pin Output Pin Function ......... 294 PDUT Configuration of PPG Duty Setting Register Overall Configuration...
Page 654 INDEX Power Supply Program Power Supply Pins ..........32 Program (Write)..........549 Power-On Program Counter Power-on............33 PC (Program Counter) ........61 Source Oscillation Input at Power-on ....33 Program Status Wait Time after Power-On ........ 106 PS (Program Status) ........... 57 Block Diagram of the PPG Timer (Overall PS (Program Status) ...........
Page 655 INDEX Setting of CS -> RD/WR Setup and of RD/WR -> CS Bit Configuration of the Hold Request Cancellation Request Register (HRCL) .....331 Hold (TYP[3:0]=0000 ,AWR=000B ............212 Bit Configuration of the Interrupt Control Register (ICR)..........329 Bit Search Module Registers......357 Ready/Busy Signal (RDY/BUSYX)....
Page 656 INDEX Data Direction Registers (DDR) ......235 Recommended ADCT Register Value....374 Register for the Delayed Interrupt Module..353 Data Internal RAM/Instruction Internal RAM Access Restriction Function Registers ....576 Register Overview of External Bus Interface ..167 Data Register (IDAR) ........462 Registers of the PPG Timer.......
Page 657 INDEX Reload/Compare Register Reload/Compare Register 0/1 (RCR 0/1).... 258 Save Reset Save/Restore Processing........362 INIT Pin Input (Settings Initialization Reset Pin) Scan Conversion Mode ............96 Scan Conversion Mode ........377 Normal Reset Operation ........102 Operation Initialization Reset (RST) ....95 SCR (System Condition Code Register)....60 Operation Initialization Reset (RST) Clear Serial Control Register (SCR) ......391...
Page 658 INDEX Serial Mode Register Simultaneous Occurrence Serial Mode Register (SMR) ......390 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request ....507 Serial Output Data Register Single Conversion Mode Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) .........
Page 659 INDEX SRCL Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) ......540 DMAC Interrupt Source Clear Register (SRCL) ............418 Configurations of Control Status Registers..303 Control Status Register (TMCSR) ......289 SRST Counter Status Register 0/1 (CSR0/1)....256 Software Reset (STCR: SRST Bit Writing) ..97 PS (Program Status)..........57 Serial Mode Control Status Register (SMCS) SSP (System Stack Pointer) ........
Page 660 INDEX Suppressing Temporary Stop Suppressing DMA ..........506 Starting from a Temporary Stop ......508 Switching Temporary Stopping Wait Time after Switching From the Subclock to the Optional Clear and Temporary Stopping of a Prefetch Main Clock......... 107 Access ..........219 Setting of Temporary Stopping by Writing to the Switching Shared Port Control Register (Set Independently for Each...
Page 661 Explanation of Terms Used in the Pin State Transfer Mode ..........493 Lists ...........597 Transfer Request Acceptance Pins Used for Fujitsu Standard Serial Onboard Transfer Request Acceptance and Transfer ..509 Writing ..........569 Transfer Sequence Specification of the -K lib Option when Character Selection of the Transfer Sequence ....
Page 662 INDEX Vector Table With External Wait EIT Vector Table ..........80 With External Wait )..216 (TYP[3:0]=0101 ,AWR=1008 Without External Wait Without External Wait Wait Time (TYP[3:0]=0100 and AWR=0008 Wait Time after Changing the PLL Multiply-by ............215 Rate ........... 106 Word Access Wait Time after Enabling a PLL ......
Page 663 CM71-10121-3E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91350A Series HARDWARE MANUAL November 2007 the third edition FUJITSU LIMITED Electronic Devices Published Edited Strategic Business Development Dept...

This manual is also suitable for:

Mb91350a series

Fujitsu FR60 Hardware Manual

Chapter 1 Overview

Chapter 2 Handling the Device

Chapter 3 Cpu and Control Units

Chapter 4 External Bus Interface

Chapter 5 I/O Port

CHAPTER 6 8/16-Bit Up/Down Counters/Timer and U-Timers

Chapter 7 16-Bit Free-Running Timer and 16-Bit Reload Timer

Chapter 8 Programmable Pulse Generator (Ppg) Timer

Chapter 9 Interrupt Controller

Chapter 10 External Interrupt and Nmi Controller

Chapter 11 Realos-Related Hardware

Chapter 12 A/D Converter

Chapter 13 8-Bit D/A Converter

Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, and Output Compare Module

Chapter 15 I 2 C Interface

Chapter 16 Dma Controller (Dmac)

Chapter 17 Flash Memory

Chapter 18 Mb91F355A/F353A/F356B/F357B Serial Programming Connection

Chapter 19 Data Internal Ram/Instruction Internal Ram

Appendix

APPENDIX A I/O Map

APPENDIX B Interrupt Vector

APPENDIX C Pin States in each CPU State

APPENDIX D Instruction Lists

Index

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Summary of Contents for Fujitsu FR60