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Fujitsu MB90480 Series Hardware Manual

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FUJITSU SEMICONDUCTOR

CM44-10121-5E

CONTROLLER MANUAL

2

F

MC-16LX

16-BIT MICROCONTROLLER

MB90480/485 Series

HARDWARE MANUAL

Table of Contents

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Summary of Contents for Fujitsu MB90480 Series

Page 1 FUJITSU SEMICONDUCTOR CM44-10121-5E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90480/485 Series HARDWARE MANUAL...
Page 3 Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Page 5 PREFACE ■ Purpose of This Manual and Intended Readers Thank you very much for purchasing FUJITSU products. MB90480/485 series is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90480/485 series functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VTRs.
Page 6 ■ Composition of This Manual This manual consists of the following 27 chapters and an appendix. CHAPTER 1 "OVERVIEW OF MB90480/485 SERIES" This chapter explains the features, block diagram, and functions to give basic specifications about the MB90480/485 series. CHAPTER 2 "CPU" This chapter provides basic information on the architecture, specifications, and instructions to help the reader understand the functions of the MB90480/485 series CPU core.
Page 7 CHAPTER 14 "16-BIT RELOAD TIMER" This chapter gives an overview of the 16-bit reload timer and explains the register configuration and functions and the 16-bit reload timer operation. CHAPTER 15 "8/16-BIT PPG TIMER" This chapter gives an overview of the 8/16-bit PPG timer and explains the register configuration and functions and the 8/16-bit PPG timer operation.
Page 8 CHAPTER 27 "I C INTERFACE" (only for MB90485 series) This chapter gives an overview of the I C interface and explains the register configuration and functions and the operation of the I C interface. APPENDIX The appendix gives information about the following parts: the I/O map, interrupt vectors, and list of instructions.
Page 9 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information.
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ............1 Features of MB90480/485 Series ......................2 Block Diagram of MB90480/485 Series ....................6 Package Dimensions ..........................7 Pin Assignment ............................9 Pin Functions ............................11 I/O Circuit Type ............................ 18 Handling the Device ..........................21 CHAPTER 2 CPU ......................
Page 12 3.7.5 Processing Time of the Extended Intelligent I/O Service (EI OS) ..........87 Exception Processing Interrupt ......................89 Stack Operation of Interrupt Processing ..................... 90 3.10 Sample Program of Interrupt Processing .................... 92 3.11 Delay Interrupt Generation Module ..................... 93 3.11.1 Operation of Delay Interrupt Generation Module ................
Page 13 7.5.3 Hold function ..........................174 CHAPTER 8 I/O PORT ....................177 Functions of I/O Port .......................... 178 Registers for I/O Port ......................... 179 8.2.1 Port registers (PDR0 to PDRA) ....................180 8.2.2 Port direction registers (DDR0 to DDRA) ..................181 8.2.3 Other registers ..........................
Page 14 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ........... 259 13.1 Overview of 8/16-bit Up/Down Counter Timer .................. 260 13.2 Configuration of 8/16-bit Up/Down Counter/Timer ................261 13.3 Configuration and Functions of Registers for 8/16-bit Up/Down Counter/Timer ....... 264 13.3.1 Counter control register (ch.0) upper (CCRH0) ................265 13.3.2 Counter control register (ch.1) upper (CCRH1) ................
Page 15 CHAPTER 17 8/10-BIT A/D CONVERTER ..............355 17.1 Overview of 8/10-Bit A/D Converter ....................356 17.2 Configuration of 8/10-Bit A/D Converter .................... 357 17.3 Configuration and Functions of 8/10-Bit A/D Converter Registers ............ 359 17.3.1 Control Status Register 1 (ADCS1) ....................360 17.3.2 Control Status Register 2 (ADCS2) ....................
Page 16 CHAPTER 20 CHIP SELECTION FACILITY ..............445 20.1 Overview of Chip Selection Facility ....................446 20.2 Configuration of Chip Selection Facility .................... 447 20.3 Configuration and Functions of Chip Selection Facility Registers ............ 449 20.3.1 Chip Select Area MASK Register (CMRx) ................... 450 20.3.2 Chip Selection Area Register (CARx) ..................
Page 17 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING CONNECTION ..........505 24.1 Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/ MB90F489B............................506 24.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply) ....... 510 24.3 Example of Minimum Connection with Flash Microcontroller Programmer (When Using the User Power Supply) ....................
Page 18 APPENDIX .......................... 577 APPENDIX A Memory Map ........................578 APPENDIX B I/O Map ..........................581 APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register ........589 APPENDIX D Instructions ........................... 591 Instruction Types ..........................592 Addressing ............................. 593 Direct Addressing ........................... 595 Indirect Addressing .........................
Page 19 → On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.) Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers is changed.
Page 20 Page Changes (For details, refer to main body.) Table 6.7-1 Pin states in single chip mode is changed. (*3: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. → *2: In the state of "Input cutoff", input A is masked and "L"...
Page 21 Page Changes (For details, refer to main body.) ■ Setting method other than program example is changed. (● Method to enable interrupt is added.) ■ Interrupt/DTP enable register (ENIR: Enable interrupt request register) is changed. (Note: is added.) ■ Interrupt/DTP source register (EIRR: External interrupt request register) in 16.2 Configuration and Func- tions of DTP/External Interrupt Unit Registers is changed.
Page 22 Page Changes (For details, refer to main body.) ❍ Clock setting in synchronous transfer is added 438 to 444 The whole description across 19.7 Program Example of UART is changed. The figure of bit configuration in ■ Chip selection control register (CSCR) is changed. (* : The initial value of this bit is "1"...
Page 23: Chapter 1 Overview Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES This chapter gives an overview of MB90480/485 series, including its basic features and basic specifications. 1.1 Features of MB90480/485 Series 1.2 Block Diagram of MB90480/485 Series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 I/O Circuit Type 1.7 Handling the Device...
Page 24: Features Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Features of MB90480/485 Series MB90480/485 series is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. ■ MB90480/485 series features The MB90480/485 series has the following features: ❍ Minimum instruction execution time 40.0 ns/6.25 MHz oscillation multiplied by 4 (25 MHz/3.3 V ±...
Page 25 2 channels of the 3 channels have the function of input compare. ❍ μPG: 1 channel (only for MB90485 series) *: I C license Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Rights to use, these components in an I C system provided that the system conforms to the I Standard Specification as defined by Philips.
Page 26 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ■ Product configuration Table 1.1-1 is an outline of the MB90480 series product configuration and Table 1.1-2 is an outline of the MB90485 series product configuration. Table 1.1-1 MB90480 series product configuration MB90V480B MB90F481B...
Page 27 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ■ Package of corresponding products ❍ Package Differences among packages are shown below. Table 1.1-3 MB90480/485 series package and correspondence of product Product MB90487B/488B MB90F481B/F482B MB90V480B Package MB90483B MB90F488B/F489B MB90V485B ❍ ❍ ✕ FPT-100P-M06 ❍...
Page 28: Block Diagram Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Block Diagram of MB90480/485 Series This section has a block diagram of the MB90480/485 series. ■ Block diagram of MB90480/485 series Figure 1.2-1 is a block diagram of the MB90480/485 series. Figure 1.2-1 Block diagram of MB90480/485 Series X0, X1, RST Clock control X0A, X1A...
Page 29: Package Dimensions
.059 –0.10 –.004 INDEX (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50±0.20 0.25(.010) (.020±.008) 0.60±0.15 (.024±.006) 0.50(.020) 0.20±0.05 0.145±0.055 0.08(.003) (.008±.002) (.0057±.0022) Dimensions in mm (inches). Note: The values in parentheses are ref erence values. 2003 FUJITSU LIMITED F100007S-c-4-6...
Page 30 –0.20 +.014 .118 –.008 (Mounting height) 0~8 ° 0.65(.026) 0.32±0.05 0.17±0.06 0.13(.005) (.013±.002) (.007±.002) 0.25±0.20 0.80±0.20 "A" (.010±.008) (.031±.008) (Stand off) 0.88±0.15 (.035±.006) Dimensions in mm (inches). 2002 FUJITSU LIMITED F100008S-c-5-5 Note: The values in parentheses are ref erence values.
Page 31: Pin Assignment
Figure 1.4-1 is a pin assignment diagram for the QFP-100 type. Figure 1.4-1 Pin assignment diagram of MB90480/485 series (QFP-100) (FPT-100P-M06) MB90480 series only • I C pin P77 and P76 are N-ch open drain pin (without P-ch). However, MB90V485B uses the N-ch open drain pin (with P-ch) .
Page 32 Figure 1.4-2 is a pin assignment diagram for the LQFP-100 type. Figure 1.4-2 Pin assignment diagram of MB90480/485 series (LQFP-100) (FPT-100P-M05) MB90480 series only • I C pin P77 and P76 are N-ch open drain pin (without P-ch). However, MB90V485B uses the N-ch open drain pin (with P-ch) .
Page 33: Pin Functions
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Pin Functions This section explains the pin functions of the MB90480/485 series. ■ Pin functions Table 1.5-1 explains the pin functions of MB90480/485 series. Table 1.5-1 Pin functions (1/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P-...
Page 34 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (2/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- General-purpose input/output port. Functions as the general-purpose input/output port in the P20 to P23 external bus mode if the bit corresponding to external address output control register (HACR) is set to "1".
Page 35 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (3/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- General-purpose input/output port Functions as an external address pin in the non-multiplex mode. (CMOS/H) ZIN1 8/16-bit up-down timer input pin (channel 1) General-purpose input/output port P36, P37 MB90480...
Page 36 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (4/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- P46, P47 General-purpose input/output port A14, A15 F(CMOS) Functions as an external address pin in the non-multiplex mode. OUT4, OUT5 Functions as the output pin for output compare events. General-purpose input/output port.
Page 37 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (5/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- General-purpose input/output port. Functions as the CLK pin in the external bus mode if the CKE bit of the EPCR register is set to "1".
Page 38 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (6/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- P80, P81 General-purpose input/output port (CMOS/H) IRQ0, IRQ1 Functions as the external interrupt input pin. P82 to P87 General-purpose input/output port (CMOS/H) IRQ2 to IRQ7 Functions as the external interrupt input pin.
Page 39 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (7/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- MD0 to MD2 Input pin name to specify the operation mode. (CMOS/H) ± Power supply pin (V 3) of 3.3V 0.3V Power supply pin for 3.3V (its tolerance is MB90480 -0.3V to +0.3V)
Page 40: I/O Circuit Type
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES I/O Circuit Type This section explains the I/O circuit type of MB90480/485 series pins. ■ I/O circuit type Table 1.6-1 summarizes the I/O circuit type of MB90480/485 series pins. Table 1.6-1 I/O circuit type (1/3) Class Circuit Description...
Page 41 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.6-1 I/O circuit type (2/3) Class Circuit Description • CMOS level input/output CMOS • Hysteresis input • CMOS level output CMOS • CMOS level input/output • Use of open-drain control Open-drain control signal CMOS •...
Page 42 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.6-1 I/O circuit type (3/3) Class Circuit Description • CMOS level input/output • Analog input CMOS Analog input • Hysteresis input • N-ch open drain output Digital output Hysteresis input (Flash product) • CMOS level input (Flash product) •...
Page 43: Handling The Device
As much as possible, the power supply source must be connected with V of this device at the lowest impedance. Fujitsu recommends placing a bypass condenser of 0.1 μF between V and V ❍ Crystal oscillation circuit Noise around the X0/X1 or X0A/X1A pins may cause an error during operation on this device.
Page 44 On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
Page 45: Chapter 2 Cpu
CHAPTER 2 This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90480/485 series functions. 2.1 Overview of CPU Specifications 2.2 Memory Space 2.3 CPU Registers 2.4 Prefix Codes...
Page 46: Overview Of Cpu Specifications
CHAPTER 2 CPU Overview of CPU Specifications This section gives an overview of the CPU specifications. ■ Overview of the CPU specifications The F MC-16LX CPU core is a 16-bit CPU designed for devices such as consumer devices that requires high-speed real-time processing. The F MC-16LX instruction set is designed for controller applications, providing high-speed and high-efficiency control processes.
Page 47: Memory Space
CHAPTER 2 CPU Memory Space The F MC-16LX CPU has a 16M bytes memory space, to which all input to and output from the F MC-16LX CPU controlled data program is allocated. CPU has a 24-bit address bus to access each resource. ■...
Page 48 CHAPTER 2 CPU ❍ Linear addressing (indirectly specified using 32-bit register) Figure 2.2-3 shows an example of linear addressing scheme indirectly specified using a 32-bit register. Figure 2.2-3 Linear addressing (indirectly specified using 32-bit register) MOV A, @RL1+7 090700 XXXX Old AL 240906F9 (Upper 8 bits are ignored)
Page 49 CHAPTER 2 CPU Table 2.2-1 Default Space Default space Addressing mode Program space PC indirect, program access, branch instruction Data space Addressing mode using @RW0, @RW1, @RW4, and @RW5; @A; addr16; dir Stack space Addressing mode using PUCHW, POPW, @RW3, and @RW7 Additional space Addressing mode using @RW2 and @RW6 Figure 2.2-4 shows an example of a memory space divided for a register bank.
Page 50 CHAPTER 2 CPU ■ Allocation for data of multi-byte length in memory space Figure 2.2-5 shows the configuration of data of a multi-byte length in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.2-5 Example for allocating data of multi-byte length in memory 1100110 11111111...
Page 51: Cpu Registers
CHAPTER 2 CPU CPU Registers The F MC-16LX registers are divided into special registers inside CPU and general- purpose registers on memory. The former is dedicated hardware inside the CPU, and its use is limited because of the CPU architecture. The latter shares CPU address spaces with RAM.
Page 52 CHAPTER 2 CPU ■ General-purpose register The F MC-16LX general-purpose register resides on the main memory addresses: 000180 00037F (maximum configuration). It uses a register bank register (RP) to indicate which part of addresses are currently used for register banks. Each bank has the three types of registers listed below.
Page 53: Accumulator (A)
CHAPTER 2 CPU 2.3.1 Accumulator (A) This section explains the accumulator (A) functions. ■ Accumulator (A) An accumulator (A) consists of two 16-bit arithmetic operation registers (AH/AL) that are used to store operation results and temporarily store data transfer results. For 32-bit data processing, AH is connected with AL.
Page 54: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) This section explains the functions of the user stack pointer (USP) and system stack pointer (SSP). ■ User stack pointer (USP) and system stack pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers indicating the push/pop instruction or the memory address to which data is saved or restored at subroutine execution.
Page 55: Processor Status (Ps)
CHAPTER 2 CPU 2.3.3 Processor Status (PS) This section explains the processor status (PS) functions. ■ Processor status (PS) Processor status (PS) consists of bits used to execute CPU operations and bits indicating the CPU state. As shown in Figure 2.3-6, the upper byte in the PS register consists of a register bank pointer (RP) and interrupt level mask register (ILM).
Page 56 CHAPTER 2 CPU ❍ Z: Zero flag If all operation results indicate "0", the Z-flag is set. Otherwise, it is cleared. ❍ V: Overflow flag If an overflow with a signed figure occurs as an operation execution result, the V-flag is set. Otherwise, it is cleared.
Page 57 CHAPTER 2 CPU Table 2.3-1 Level indicated by interrupt level mask register (ILM) ILM2 ILM1 ILM0 Level value Permitted interrupt level Interrupt prohibited "0" only Level value less than 1 Level value less than 2 Level value less than 3 Level value less than 4 Level value less than 5 Level value less than 6...
Page 58: Program Counter (Pc)
CHAPTER 2 CPU 2.3.4 Program Counter (PC) This section explains the program counter (PC) functions. ■ Program counter (PC) PC is a 16-bit counter indicating the lower 16 bits in the memory address of an instruction code to be executed by CPU. An upper 8-bit address is indicated with the program count bank register (PCB).
Page 59: Program Counter Bank Register (Pcb)
CHAPTER 2 CPU 2.3.5 Program Counter Bank Register (PCB) This section explains the program counter bank register (PCB) functions. ■ Program counter bank register (PCB) <Initial value: value in reset vector> The program counter bank register (PCB) consists of the following registers: •...
Page 60: Direct Page Register (Dpr)
CHAPTER 2 CPU 2.3.6 Direct Page Register (DPR) This section explains the direct page register (DPR) functions. ■ Direct page register (DPR) <Initial value: 01 > The direct page register (DPR) specifies, as shown in Figure 2.3-11, addresses 8 to 15 of an instruction operand in the direct addressing mode.
Page 61: General-Purpose Register (Register Bank)
CHAPTER 2 CPU 2.3.7 General-Purpose Register (Register Bank) This section explains the general-purpose register (register bank) functions. ■ General-purpose register (register bank) A register bank consists of 8 words and is used as a general-purpose register for arithmetic operation in the byte register (R0 to R7), word register (RW0 to RW7), and long-word register (RL0 to RL3).
Page 62: Prefix Codes
CHAPTER 2 CPU Prefix Codes By inserting a prefix code before an instruction, part of an instruction operation may change. Three types of prefix codes are provided: bank select prefixes, common register bank prefixes, and flag change suppress prefixes. ■ Bank select prefix (PCB, DTB, ADB, SPB) Memory space used in data access is determined according to the addressing mode.
Page 63 CHAPTER 2 CPU ❍ RETI SSB is used regardless of prefix. ■ Common register bank prefix (CMR) To facilitate data exchange between multiple tasks, the same register bank needs to be easily accessed regardless of each register bank pointer (RP) value. If CMR is inserted before an instruction that accesses a register bank, the instruction accesses the common bank with addresses ranging from 000180 to 00018F...
Page 64 CHAPTER 2 CPU ■ Interrupt suppress instruction No interrupt requests are sampled on ten types of instruction as follows. MOV ILM, #imm8/PCB/SPB/OR CCR, #imm8/NCC AND CCR, #imm8/ADB/CMR/POPW PS/DTB If an effective interrupt request is issued when any of above instructions is executed, an interrupt may be processed only if instructions other than the above are executed.
Page 65: Chapter 3 Interrupt
CHAPTER 3 INTERRUPT This chapter explains interrupts and direct memory access (DMA). 3.1 Overview of Interrupt 3.2 Interrupt Factor and Interrupt Vector 3.3 Interrupt Control Register and Peripheral Function 3.4 Hardware Interrupt 3.5 Software Interrupt 3.6 Interrupt by μDMAC 3.7 Interrupt by Extended Intelligent I/O Service (EI 3.8 Exception Processing Interrupt 3.9 Stack Operation of Interrupt Processing 3.10 Sample Program of Interrupt Processing...
Page 66: Overview Of Interrupt
CHAPTER 3 INTERRUPT Overview of Interrupt MC-16LX has the following four interrupt functions that temporarily stop processing currently being performed and make the control move to programs defined separately when certain events occur: • Hardware interrupt • Software interrupt • Interrupt by μDMAC •...
Page 67 CHAPTER 3 INTERRUPT ■ Overall flow of interrupt operation Four types of interrupt functions provide start and return processing, as shown in Figure 3.1-1. Figure 3.1-1 Overall flow of interrupt operation START Main program Valid hardware Interrupt start and return processing interrupt request String-type instruction being...
Page 68: Interrupt Factor And Interrupt Vector
FFFFC4 FFFFC5 FFFFC6 Unused Hardware interrupt #3 INT254 FFFC04 FFFC05 FFFC06 Unused #254 None INT255 FFFC00 FFFC01 FFFC02 Unused #255 None Reference: For interrupt vectors that are not used, Fujitsu recommends specifying such vectors for the address for exception processing.
Page 69 CHAPTER 3 INTERRUPT ■ Interrupt factors, interrupt vector, and interrupt control register Table 3.2-2 shows the relationship among interrupt factors excluding software interrupts, interrupt vectors, and interrupt control registers. Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (1 / 2) Interrupt control μDMAC Interrupt vector...
Page 70 CHAPTER 3 INTERRUPT Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (2 / 2) Interrupt control μDMAC Interrupt vector register Interrupt factor channel clear number Number Address Number Address ❍ × Output compare (ch.5) match FFFF78 ICR11 0000BB ❍...
Page 71: Interrupt Control Register And Peripheral Function
CHAPTER 3 INTERRUPT Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller, and they correspond to every peripheral function that has an interrupt function. This register controls interrupts. ■ List of interrupt control registers Table 3.3-1 lists interrupt control registers and the corresponding peripheral functions.
Page 72: Interrupt Control Register (Icr00 To Icr15)
CHAPTER 3 INTERRUPT 3.3.1 Interrupt Control Register (ICR00 to ICR15) The interrupt control register (ICR00 to ICR15) corresponds to every peripheral function that has interrupt functions for controlling processing during interrupt request generation. This register has different functions between write and read operations.
Page 73 CHAPTER 3 INTERRUPT ■ Function of each bit in interrupt control register (ICR00 to ICR15) ❍ Interrupt level setting bit (IL2 to IL0) This specifies the corresponding interrupt level in the peripheral function. A reset initializes the bit to level 7 (no interrupts). Table 3.3-2 lists the relationship between interrupt level setting bits and every interrupt level.
Page 74 CHAPTER 3 INTERRUPT ❍ Extended intelligent I/O service (EI OS) status bit (S1, S0) S1, S0 bits are read-only bits. Whether the state is operating or terminated can be read by confirming the S1, S0 bits value at the end of EI OS.
Page 75: Hardware Interrupt
CHAPTER 3 INTERRUPT Hardware Interrupt Hardware interrupt is a function to temporarily stop the execution of program being executed by the CPU in response to an interrupt request signal from the peripheral function. It then moves control to the interrupt processing program defined by a user. Also, μDMAC and external interrupt may be executed as a kind of hardware interrupt.
Page 76 CHAPTER 3 INTERRUPT ■ Configuration of hardware interrupt The hardware-interrupt mechanism is divided into four parts, as shown in Table 3.4-1. To use hardware interrupts, a program must contain settings for the four locations. Table 3.4-1 Hardware-interrupt mechanism Hardware-interrupt mechanism Function Interrupt enable bit, interrupt Control of interrupt request by peripheral...
Page 77 CHAPTER 3 INTERRUPT ❍ Suppressing hardware interrupts in the interrupt suppress instruction Of the ten types of hardware interrupt suppress instruction listed in Table 3.4-2, none can detect whether or not hardware interrupt requests are present, and none can ignore an interrupt request.
Page 78: Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.1 Hardware Interrupt Operation This section explains an operation starting from hardware interrupt request generation until completion of interrupt processing. ■ Starting hardware interrupt ❍ Operation of peripheral function (generating an interrupt request) The peripheral functions including hardware interrupt request functions have the "interrupt request flag"...
Page 79 CHAPTER 3 INTERRUPT ■ Hardware interrupt operation Figure 3.4-2 shows the operation from the generation of hardware interrupt until the completion of interrupt processing. Figure 3.4-2 Hardware interrupt operation Internal data bus PS,PC Microcode Check Comparator MC-16LX CPU Other peripheral function Peripheral function generating an interrupt request...
Page 80: Flow Of Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.2 Flow of Hardware Interrupt Operation If an interrupt request is generated by a peripheral function, the interrupt controller transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the instruction currently being executed is temporarily suspended to execute the interrupt processing routine or to start μDMAC.
Page 81: Procedure For Using Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4.3 Procedure for Using Hardware Interrupt To use hardware interrupts, necessary setup including the system stack area, peripheral functions, and interrupt control registers (ICR) must be performed. ■ Procedure for using hardware interrupt Figure 3.4-4 shows an example of a procedure for using hardware interrupts. Figure 3.4-4 Procedure for using hardware interrupt Start Setup of the system...
Page 82 CHAPTER 3 INTERRUPT (7) Interrupt processing hardware saves registers to branch to the interrupt processing program. (8) The interrupt processing program processes peripheral functions because of interrupt generation. (9) The interrupt request from peripheral function is canceled. (10) The interrupt return instruction is executed, and the program is restored to what it was before branching.
Page 83: Multiple Interrupts
CHAPTER 3 INTERRUPT 3.4.4 Multiple Interrupts Multiple hardware interrupt can be executed by specifying a different interrupt level for each interrupt level setting bit (IL0 to IL2) in the interrupt control register (ICR) in response to multiple interrupt request from the peripheral function. μDMACs cannot be started in duplicate, however.
Page 84 CHAPTER 3 INTERRUPT ❍ A/D interrupt generation When the A/D converter interrupt processing starts, the interrupt level mask register (ILM) is automatically set to the same interrupt level (i.e., 2 in this example) as that for the A/D converter (IL2 to IL0 in ICR). In this example, if an interrupt request of level 1 or 0 is generated, the interrupt with higher priority is executed first.
Page 85: Hardware Interrupt Processing Time
CHAPTER 3 INTERRUPT 3.4.5 Hardware Interrupt Processing Time The time period starting from generation of a hardware interrupt request until the execution of interrupt handling routine requires the time until the instruction currently being executed is completed plus the interrupt processing time. ■...
Page 86 CHAPTER 3 INTERRUPT ❍ Interrupt processing time (θ machine cycles) After the CPU accepts an interrupt request, the CPU saves the dedicated registers in the system stack and fetches the interrupt vector. The interrupt processing time is thus derived from the following formula: At interrupt start: θ...
Page 87: Software Interrupt
CHAPTER 3 INTERRUPT Software Interrupt Software interrupt is a function used to move control to the user-defined program for interrupt processing from a program that the CPU is being executed if a software interrupt instruction (INT instruction) is executed. A hardware interrupt is stopped while a software interrupt is executed.
Page 88 CHAPTER 3 INTERRUPT ■ Software interrupt operation Figure 3.5-1 shows the operation starting from software interrupt generation until interrupt processing completion. Figure 3.5-1 Software interrupt operation Internal data bus PS,PC (2) Microcode Queue Fetch PS : Processor status : Interrupt enable flag S : Stack flag IR : Instruction register 1.
Page 89: Interrupt By Μdmac
CHAPTER 3 INTERRUPT Interrupt by μDMAC The μDMAC controller is a simplified DMA that has the same function as EI OS. DMA transfers are set up using the DMA descriptor. μDMAC functions ■ μDMAC has the functions listed below. • Provides an automatic data transfer between a peripheral resource (I/O) and memory.
Page 90 CHAPTER 3 INTERRUPT μDMAC enable register (DER) has the bit functions listed below. ENx bit Function Outputs an interrupt request from a resource to the interrupt controller. (Initial value) (An interrupt request from a resource is not used as a DMA start request). An interrupt request output from a resource is used as a DMA start request.
Page 91 CHAPTER 3 INTERRUPT The functions of each bit in the μDMAC status register (DSR) is shown in the table below. DEx bit Function No DMA transfer has ended. (Initial value) If the DMA transfer ends, an interrupt request is output to the interrupt controller.
Page 92: Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.1 DMA Descriptor The DMA descriptor is located in internal RAM within a range from "000100 " to "00017F " consisting of 8 bytes x 16 channels. ■ DMA descriptor configuration The DMA descriptor consists of 8 bytes x 16 channels. Each DMA descriptor has the configuration shown in the Figure 3.6-2.
Page 93 CHAPTER 3 INTERRUPT Table 3.6-1 Relationship between channel number and descriptor address μDMAC enable Descriptor Channel Resource interrupt request register address 000100 INT0 000108 PWC0 (Only MB90485 series) 000110 PPG0/PPG1 counter borrow 000118 PPG2/PPG3 counter borrow 000120 PPG4/PPG5 counter borrow 000128 Input capture (channel 0) load 000130...
Page 94: Individual Registers Of Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.2 Individual Registers of DMA Descriptor Each DMA descriptor consists of the following registers: • Data counter (DCT) • I/O register address pointer (IOA) • DMA control status register (DMACS) • Buffer address pointer (BAP) The registers must be initialized because their initial values become undefined when they are reset.
Page 95 CHAPTER 3 INTERRUPT ■ DMA control status register (DMACS) The DMA control status register (DMACS) has a length of 8 bits that indicate the update or fixed state, transfer data format (byte/word), and transfer directions for the buffer address pointer (BAP) and I/O register address pointer (IOA).
Page 96 CHAPTER 3 INTERRUPT ■ Buffer address pointer (BAP) The buffer address pointer (BAP) has a length of 24 bits, containing the address used in the next DMA transfer. BAP is independent from each DMA channel, so each DMA channel can transfer data between any of 16M bytes addresses and I/O.
Page 97: Μdmac Processing Procedure
CHAPTER 3 INTERRUPT μDMAC Processing Procedure 3.6.3 If an interrupt request is generated by a peripheral resource (I/O) and the corresponding μDMAC enable register (DER) has a setting of DMA start, then a DMA transfer is performed. If a data transfer ends at the specified count, an interrupt request is output to the interrupt controller.
Page 98: Μdmac Processing Time
CHAPTER 3 INTERRUPT μDMAC Processing Time 3.6.4 Time consumed in μDMAC processing varies with the following factors: • Settings of DMA control status register (DMACS) • Address (area) indicated by the I/O register address pointer (IOA) • Address (area) indicated by the buffer address pointer (BAP) •...
Page 99 CHAPTER 3 INTERRUPT Note: B indicates a byte data transfer, 8 indicates a word transfer with an external bus width of 8 bits, even indicates word transfer of an even-numbered address, and odd indicates a word transfer of an odd-numbered address. ❍...
Page 100: Interrupt By Extended Intelligent I/O Service (Ei Os)
CHAPTER 3 INTERRUPT Interrupt by Extended Intelligent I/O Service (EI Extended Intelligent I/O Services (EI OS) are a function that automatically transfers data between the peripheral function (I/O) and RAM. After completion of the data transfer, hardware interruptions will occur. ■...
Page 101 CHAPTER 3 INTERRUPT ■ Operation of EI Figure 3.7-1 Operation of EI Memory Space Peripheral function (Resource) by I/OA Resource Resource register register Interrupt request by ICS Interrupt Control Register (ICR) Interrupt controller by BAP Buffer Count by DCT : EI OS descriptor I/OA : I/O address pointer...
Page 102: Ei 2 Os Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.7.1 OS descriptor (ISD) OS descriptor (ISD) which is in 000100 to 00017F of built-in RAM is consists of 8- byte x 16 channels. ■ Configuration of EI OS Descriptor (ISD) ISD comprises 8-byte x 16 channels. Figure 3.7-2 Configuration of EI OS Descriptor (ISD) Data counter upper 8bit (DCTH)
Page 103 CHAPTER 3 INTERRUPT Table 3.7-1 Relation between channel number and descriptor address Channel Descriptor address* 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 *:The address of ISD indicates the first address of 8-byte.
Page 104: Each Register Of Ei 2 Os Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.7.2 Each Register of EI OS Descriptor (ISD) Extended intelligent I/O service (EI OS) descriptor (ISD) is configurated by following 4 types of 8-byte registers. • Data counter (DCT: 2 bytes) • I/O register address pointer (IOA: 2 bytes) •...
Page 105 CHAPTER 3 INTERRUPT ■ OS Status Register (ISCS) OS status register (ISCS) is 8-bit register. The methods to renew the buffer address pointer and I/O address pointer, the transfer data type (byte/word) and the transfer direction can be specified. Figure 3.7-5 Configuration of EI OS Status Register (ISCS) Initial value XXXXXXXX...
Page 106 CHAPTER 3 INTERRUPT ■ Buffer address pointer (BAP) Buffer address pointer (BAP) is 24-bit register. EI OS operation set the memory address of the data transferring source. Buffer address pointer exists in each channel. So, the data can be transferring between the 16M-byte memory address and the peripheral function (resource) address.
Page 107: Operation Of Ei 2 Os
CHAPTER 3 INTERRUPT 3.7.3 Operation of EI CPU transfers the data by EI OS, when the interrupt request is output from the peripheral function (resource) and the interrupt control register has been set to the start of EI OS. When the EI OS operation ends, hardware interrupt is done.
Page 108: Procedure For Use Of Ei
CHAPTER 3 INTERRUPT 3.7.4 Procedure for Use of EI The setting of extended intelligent I/O service (EI OS) is set by the system stack area, the extended intelligent I/O service (EI OS) descriptor, the peripheral function (resource), and the interrupt control register (ICR). ■...
Page 109: Processing Time Of The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.7.5 Processing Time of the Extended Intelligent I/O Service The time required for processing the extended intelligent I/O service (EI OS) depends on setting of the extended intelligent I/O service descriptor (ISD). • EI OS status register (ISCS) setting •...
Page 110 CHAPTER 3 INTERRUPT ● When the data counter (DCT) count terminates (final data transfer) Because the hardware interrupt is activated when data transfer by EI OS terminates, the interrupt handling time is added. The EI OS processing time when counting terminates is calculated with the following formula : OS processing time when data is transferred (21 + 6 ×...
Page 111: Exception Processing Interrupt
CHAPTER 3 INTERRUPT Exception Processing Interrupt In the F MC-16LX, the execution of an undefined instruction results in exception processing. Exception processing is basically the same as an interrupt. When the generation of an exception processing is detected on the instruction boundary, ordinary processing is interrupted and exception processing is executed.
Page 112: Stack Operation Of Interrupt Processing
CHAPTER 3 INTERRUPT Stack Operation of Interrupt Processing If an interrupt is accepted, contents of the dedicated registers are automatically saved in the system stack before branching to interrupt processing. Return from the stack is also automatically performed when interrupt processing is completed. ■...
Page 113 CHAPTER 3 INTERRUPT ■ Stack area ❍ Assigning the stack area The stack area is used for storage and return of the program counter (PC) required for executing interrupt processing, subroutine call instruction (CALL) and vector call instruction (CALLV), as well as temporary save and return of registers executed by using the PUSHW and POPW instructions.
Page 114: Sample Program Of Interrupt Processing
CHAPTER 3 INTERRUPT 3.10 Sample Program of Interrupt Processing A sample program for interrupt processing is shown below. ■ Sample program for interrupt processing ❍ Processing specification An example of an interrupt program using external interrupt 0 (INT0) is shown. Sample coding from the program is shown below.
Page 115: Delay Interrupt Generation Module
"0" clears the delay interrupt request. Resetting causes the factor clear state. Either "0" or "1" can be written to the reserve bit area. For future expansion, however, Fujitsu recommends using the set bit or clear bit instructions to access this register.
Page 116: Operation Of Delay Interrupt Generation Module
CHAPTER 3 INTERRUPT 3.11.1 Operation of Delay Interrupt Generation Module If CPU writes "1" to the relevant DIRR bit with software, the request latch in the delay interrupt generation module is set to generate an interrupt request to the interrupt controller.
Page 117: Chapter 4 Reset
CHAPTER 4 RESET This chapter explains reset for the MB90480/485 series. 4.1 Overview of Reset 4.2 Reset Factors and Oscillation Stabilization Wait Time 4.3 External-Reset Pin 4.4 Resetting 4.5 Reset-Factor Bits 4.6 Condition of Pins as Result of Reset...
Page 118: Overview Of Reset
CHAPTER 4 RESET Overview of Reset If a reset factor occurs, the CPU immediately stops the processing currently in progress and stands by for cancellation of the reset. After the reset is canceled, processing starts at the address specified by the reset vector. A reset is triggered by the following four factors: •...
Page 119 CHAPTER 4 RESET ❍ External reset An external reset is triggered by input of the "L" level to the external-reset pin (pin RST). More than 16 machine cycles (16/φ) is required for the "L" level input time to pin RST. An external reset (pin RST input reset) does not require the oscillation stabilization wait time.
Page 120: Reset Factors And Oscillation Stabilization Wait Time
CHAPTER 4 RESET Reset Factors and Oscillation Stabilization Wait Time The four types of reset factors can occur in the MB90480/485 series devices. The oscillation stabilization wait time during a reset varies depending on the reset factor. ■ Reset factors and oscillation stabilization wait time Table 4.2-1 summarizes the reset factors and the oscillation stabilization wait time.
Page 121 CHAPTER 4 RESET Figure 4.2-1 shows the oscillation stabilization wait time for evaluation devices, flash memory devices, and mask ROM devices during a power-on reset. Figure 4.2-1 Waiting times to stable oscillation for evaluation devices/flash memory devices and mask ROM devices during power-on reset Evaluation device/FLASH device /HCLK /HCLK...
Page 122: External-Reset Pin
CHAPTER 4 RESET External-Reset Pin The external-reset pin (pin RST) is a pin dedicated for the input of resets, and it triggers an internal reset by input of the "L" level. The MB90480/485 series devices have resets synchronized to the CPU operation clock. However, only external pins (e.g., ports) change asynchronously to a reset state.
Page 123: Resetting
CHAPTER 4 RESET Resetting After the cancellation of a reset, a read from operation of mode data and the reset vector can be selected by setting the mode pin to perform mode fetching. Mode fetching determines the CPU operation mode and the start address of execution after the end of a reset.
Page 124 ROM or external memory. If the external vector mode is specified with a mode pin, however, external memory and not internal ROM is accessed to read reset vectors and mode data. Fujitsu recommends specifying the internal vector mode with a mode pin when the single- chip mode and internal ROM external bus mode are used.
Page 125: Reset-Factor Bits
CHAPTER 4 RESET Reset-Factor Bits Reset factors can be determined by reading the watchdog timer control register (WDTC). ■ Reset-factor bits As shown in the Figure 4.5-1, each reset factor has a corresponding flip-flop assigned to it. This information can be obtained by reading the watchdog timer control register (WDTC). If a reset factor must be determined after a reset cancellation, run software to process the read value of the WDTC register, and branch to an appropriate program.
Page 126 CHAPTER 4 RESET ■ Correspondence between reset-factor bits and reset factors Figure 4.5-2 shows the configuration of the reset-factor bits for the watchdog timer control register (WDTC). Table 4.5-1 shows the correspondence between reset-factor bits and reset factors. For details, refer to Section "10.2 Watchdog Timer Control Register (WDTC)". Figure 4.5-2 Configuration of reset-factor bits (watchdog timer control register) 15 - - - - - - - 8 0000A8...
Page 127: Condition Of Pins As Result Of Reset
CHAPTER 4 RESET Condition of Pins as Result of Reset This section explains the states of pins after a reset. ■ Pin states during a reset States of the pins during a reset are determined by the settings of mode pins (MD2 to MD0). ❍...
Page 128 CHAPTER 4 RESET...
Page 129: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter describes the clocks of the MB90480/485 series. 5.1 Overview of Clocks 5.2 Block Diagram of Clock Generator 5.3 Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) 5.4 Clock Modes 5.5 Oscillation Stabilization Wait Time 5.6 Connecting Oscillator to External Clock...
Page 130: Overview Of Clocks
CHAPTER 5 CLOCKS Overview of Clocks The clock generator controls the operations of internal clocks, which are the operation clocks of the CPU and peripheral functions. In this document, the clocks are called as follows according to clock type: • Machine clock: Defined as an internal clock. •...
Page 131 CHAPTER 5 CLOCKS ■ Clock supply map Machine clocks generated by the clock generator are supplied as operation clocks of the CPU and peripheral functions. Therefore, operations of the CPU and peripheral functions are affected by changes between the main clock and PLL clock (clock mode) and by changes in the PLL clock multiplication rate.
Page 132: Block Diagram Of Clock Generator
CHAPTER 5 CLOCKS Block Diagram of Clock Generator The clock generator consists of the following five blocks: • System clock generator circuit/sub-clock generator circuit • PLL multiplier circuit • Clock selector • Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) •...
Page 133 CHAPTER 5 CLOCKS ❍ System clock generator circuit This circuit generates an oscillation clock (HCLK) by using an oscillator connected to the high- speed oscillation pin. Also, an external clock can be input to it. ❍ Sub-clock generator circuit This circuit generates a sub-clock (SCLK) by using an oscillator connected to the low-speed oscillation pin.
Page 134: Clock Selection Register (Ckscr) And Pll Output Selection Register (Pllos)
CHAPTER 5 CLOCKS Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) The clock selection register (CKSCR) switches among the main clock, sub-clock, and PLL clock, and it selects the oscillation stabilization wait time and PLL clock multiplication rate. The PLL output selection register (PLLOS) must be set for the PLL to be used when a machine clock is used at a frequency of 20 to 25 MHz.
Page 135 CHAPTER 5 CLOCKS Note: When reset, the machine clock selection (MCS) bit is initialized to the main clock selection. Table 5.3-1 Functions of bits in clock selection register (CKSCR) (1/2) Bit name Function This bit displays whether the main clock or sub-clock is selected as a machine clock.
Page 136 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) (2/2) Bit name Function This bit specifies selection of the main clock or sub-clock as a machine clock. • If this bit is "0", the sub-clock is selected. If "1", the main clock is selected.
Page 137 CHAPTER 5 CLOCKS ■ Configuration of PLL output selection register (PLLOS) Figure 5.3-2 shows the configuration of the PLL output selection register (PLLOS). Table 5.3-2 explains the functions of the bits for the PLL output selection register. Figure 5.3-2 Configuration of PLL output selection register (PLLOS) Address Initial value DIV2 PLL2...
Page 138 CHAPTER 5 CLOCKS Table 5.3-2 Functions of bits for PLL output selection register (PLLOS) Bit name Function Undefined Not used bit15 to bit10 bits • This bit selects dividing of input clock to PLL or input as it • It is initialized to "0" by all reset sources. •...
Page 139: Clock Modes
CHAPTER 5 CLOCKS Clock Modes The clock modes are the main clock, PLL clock, and sub-clock modes. ■ Main clock mode, PLL clock mode, and sub-clock mode ❍ Main clock mode The main clock mode uses a clock obtained by dividing the oscillation clock by two as the operation clock of the CPU and peripheral resources.
Page 140 CHAPTER 5 CLOCKS ❍ Change from the PLL clock mode to the sub-clock mode Rewriting the sub-clock selection bit (SCS) of the clock selection register (CKSCR) from "1" to "0" in the PLL clock mode changes the PLL clock to the sub-clock. ❍...
Page 141 CHAPTER 5 CLOCKS Figure 5.4-1 State transition diagram of machine clock selection Main→Sub MCS=1 MCM=1 Main SCS=0 (10) MCS=1 SCM=1 MCS=1 MCM=1 CS1,CS0=xx MCM=1 (16) SCS=1 SCS=0 SCM=1 Sub→Main (10) (11) SCM=0 CS1,CS0=xx MCS=1 CS1,CS0=xx MCM=1 SCS=1 SCM=0 Main→PLLx Sub→PLL CS1,CS0=xx (12) MCS=0...
Page 142 CHAPTER 5 CLOCKS (1) MCS bit "0" write (2) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 00 (3) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 01 (4) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 10 (5) Waiting for PLL clock oscillation stability is complete.
Page 143: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCKS Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released, or switching from the sub- clock to the main clock or from sub-clock to the PLL clock occurs, an oscillation stabilization wait time is required after oscillation begins because the oscillation clock is stopped.
Page 144: Connecting Oscillator To External Clock
CHAPTER 5 CLOCKS Connecting Oscillator to External Clock Devices in the MB90480/485 series contain a system clock generator circuit and generate clocks using an externally connected oscillator. Also, an external clock can be input to it. ■ Connection of oscillator and external clock ❍...
Page 145: Chapter 6 Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of the MB90480/485 series. 6.1 Overview of Low-Power Consumption Mode 6.2 Block Diagram of Low-Power Consumption Control Circuit 6.3 Low-Power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Transition Diagram 6.7 Pin State in Standby Mode, Hold, and Reset...
Page 146: Overview Of Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Overview of Low-Power Consumption Mode The following CPU operation modes are available on the MB90480/485 series devices by selecting a suitable operation clock and by controlling clock operation. • Clock modes (Main clock mode, and sub-clock mode) •...
Page 147 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Clock modes ❍ Main clock mode This mode operates the CPU and peripheral functions by using the clock of the oscillation clock (HCLK) divided by two. The PLL multiplier circuit stops its operation in the main clock mode. ❍...
Page 148: Block Diagram Of Low-Power Consumption Control Circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE Block Diagram of Low-Power Consumption Control Circuit The low-power consumption control circuit is composed of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU-clock control circuit • Peripheral clock control circuit •...
Page 149 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ CPU intermittent operation selector The CPU intermittent operation selector selects the number of pause clocks in the CPU intermittent operation mode. ❍ Standby control circuit The standby control circuit controls the CPU-clock control circuit and peripheral clock control circuit for resetting and changing to the low-power consumption mode.
Page 150: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW-POWER CONSUMPTION MODE Low-Power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs functions including changing the current mode to the low-power consumption mode, canceling from the low-power consumption mode, and specifying the number of CPU-clock pause cycles in the CPU intermittent operation mode.
Page 151 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.3-1 Functions of bits in low-power consumption mode control register (LPMCR) Bit name Function This bit instructs a change to the stop mode. • Write "1" in this bit to change the mode to the stop mode. STP: bit7 •...
Page 152 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Accessing low-power consumption mode control register Writing in the low-power consumption mode control register executes a change to the standby mode (stop, sleep, timebase timer and watch modes). Use the instructions listed in Table 6.3-2. The low-power consumption mode transition instruction in Table 6.3-2 must always be followed by an array of instructions highlighted by a line below.
Page 153: Cpu Intermittent Operation Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE CPU Intermittent Operation Mode The CPU intermittent operation mode reduces power consumption by intermittently operating the CPU while operating external buses and peripheral functions at high speeds. ■ CPU intermittent operation mode To delay activation of the internal bus cycle, the CPU intermittent operation mode stops clocks supplied to the CPU for a preset period for each instruction during access to registers, embedded memory (ROM or RAM), I/O, peripheral functions, and external buses.
Page 154: Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Standby Mode The standby mode is divided into four modes, namely, the sleep (PLL sleep, main sleep, and sub sleep), timebase timer, watch, and stop modes. ■ Operational states in standby mode Table 6.5-1 lists operational states in the standby mode. Table 6.5-1 Operational states in standby mode Change Machine...
Page 155: Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.1 Sleep Mode The sleep mode stops CPU operation clocks, allowing devices other than the CPU to continue operation. ■ Change to sleep mode Writing "1" in the sleep mode bit (SLP), "1" in the watch/timebase timer mode bit (TMD), and "0" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) changes the mode to the sleep mode.
Page 156 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Canceling the sleep mode The low-power consumption control circuit cancels the sleep mode by input of a reset or by an interrupt. ❍ Restore by a reset Reset initializes to the main clock mode. ❍...
Page 157: Timebase Timer Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.2 Timebase Timer Mode The timebase timer mode stops operations except for source oscillation, timebase timer and watch timer. All functions except the timebase timer and watch timer are stopped. ■ Change to timebase timer mode To change the mode to the timebase timer mode, write "0"...
Page 158 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the timebase timer mode is normally executed first before an interrupt request is processed. If a change to the timebase timer mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed.
Page 159: Watch Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.3 Watch Mode The watch mode stops operations other than those of the sub-clock and watch timer. Almost all functions on the chip are stopped. ■ Change to watch mode To change the mode to the watch mode, write "0" in watch/timebase timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) in the sub-clock mode (sub-clock display bit (SCS) = 0 of the clock selection register (CKSCR)).
Page 160 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Return by interrupt The watch mode is canceled by the low-power consumption control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0=111 of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the watch mode.
Page 161: Stop Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.4 Stop Mode The stop mode stops source oscillation and stops all functions, thereby enabling retention of data with the lowest consumption of power. ■ Change to stop mode Write "1" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) to change the mode to the stop mode.
Page 162 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Restore by interrupt The stop mode is canceled by the low-power consumption control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0=111 of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the stop mode.
Page 163: State Transition Diagram
CHAPTER 6 LOW-POWER CONSUMPTION MODE State Transition Diagram This section explains the transition of operational states for the MB90480/485 series and describes the transition conditions. ■ State transition diagram Figure 6.6-1 illustrates the transition of operational states for the MB90480/485 series and the transition conditions.
Page 164 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Operational state in low-power consumption mode Table 6.6-1 lists operational states in the low-power consumption mode. Table 6.6-1 Operational states in low-power consumption mode Main Sub- Timebase Clock Operational state PLL clock Peripheral Watch clock clock timer...
Page 165: Pin State In Standby Mode, Hold, And Reset
CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in Standby Mode, Hold, and Reset The states of the pins in the standby mode and in the hold and reset states are described for each memory access mode. ■ Pin state in single chip mode Table 6.7-1 lists the pin states in the single-chip mode.
Page 166 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode Table 6.7-2 summarizes pin states in the external bus 16-bit data bus mode and multiplex 16-bit external bus mode. Table 6.7-2 Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode When stopped Internal ROM...
Page 167 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode Table 6.7-3 lists pin states in the external bus 8-bit data bus mode and multiplex 8-bit external bus mode. Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode When stopped Internal ROM...
Page 168 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode Table 6.7-4 lists pin states in the external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode. Table 6.7-4 Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode When stopped Internal ROM...
Page 169 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode Table 6.7-5 summarizes pin states in the external bus 8-bit data bus mode and non-multiplex 8- bit external bus mode. Table 6.7-5 Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode When stopped Internal ROM...
Page 170: Caution On Using Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Caution on Using Low-Power Consumption Mode When operating in the low-power consumption mode, exercise reasonable care concerning the following: • Change to the standby mode and interrupts • Cancellation of standby mode by interrupt • Cancellation of stop mode •...
Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Oscillation stabilization wait time ❍ Oscillation stabilization wait time of oscillation clock The oscillator for source oscillation is stopped in the stop mode, and a oscillation stabilization wait time must be provided. Specify the oscillation stabilization wait time selected with the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR).
Page 172 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode • To access the low-power consumption mode control register (LPMCR) with assembler language - To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2.
Page 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I: _IO_LPMCR,#H'98 /* Set LPMCR STP bit to "1" */ /* Jump to next instruction */ #pragma endasm...
Page 174 CHAPTER 6 LOW-POWER CONSUMPTION MODE...
Page 175: Chapter 7 Mode Setting
CHAPTER 7 MODE SETTING This chapter explains mode setting, mode pins, mode data, external memory access and its operation. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data 7.4 External Memory Access 7.5 Operation of Each Mode for Mode Setting...
Page 176: Mode Setting
CHAPTER 7 MODE SETTING Mode Setting The F MC-16LX has different modes in each access system and access area. Each mode is set according to a mode pin at the reset state and according to mode data obtained by mode-fetch. ■...
Page 177: Mode Pins (Md2 To Md0)
CHAPTER 7 MODE SETTING Mode Pins (MD2 to MD0) Mode pins are three external pins (MD2 to MD0) that specify the reset vector and mode data fetching method. ■ Settings of mode pins (MD2 to MD0) Mode pins (MD2 to MD0) are used to select the source, either the external or internal data bus when reset vectors are read and stored, and to select the bus width when the external data bus is used.
Page 178: Mode Data
CHAPTER 7 MODE SETTING Mode Data Mode data stored at address FFFFDF in memory specifies the operation immediately after the reset sequence. Mode data is read and stored in the CPU automatically by mode fetching. ■ Mode data During the reset sequence, mode data at address FFFFDF is sent to the mode register in the CPU core.
Page 179 CHAPTER 7 MODE SETTING ■ Bus mode setting bits (M1, M0) Bits M1 and M0 specify the operation mode that is set after completion of the reset sequence. Table 7.3-2 lists the contents of the settings for bits M1 and M0. Table 7.3-2 Contents of bit M1 and M0 settings Functions Single-chip mode...
Page 180 CHAPTER 7 MODE SETTING ■ Relationship between mode pins and mode data (an example showing recommended relationship) Table 7.3-3 shows the relationship between mode pins and mode data. Table 7.3-3 Relationship between mode pins and mode data Mode Single chip Internal ROM external bus mode, 8-bit (address data multiplex) Internal ROM external bus mode, 16-bit...
Page 181 CHAPTER 7 MODE SETTING ■ Operation of external pins in each mode Table 7.3-4 shows the operation of each external pin in the non-multiplex mode and multiplex mode. Table 7.3-4 Operation of external pins in each mode Functions Non-multiplex mode Multiplex mode External address control External address control...
Page 182: External Memory Access
CHAPTER 7 MODE SETTING External Memory Access This section contains block diagrams about external memory access, the configuration and functions of registers, and operation of external memory access. ■ I/O signal pins for external memory access For accessing external memory and peripheral devices, the F MC-16LX supplies the following address, data, and control signals: •...