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Fujitsu FR Series Application Note

32-bit microcontroller
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Fujitsu Microelectronics Europe
MCU-AN-300021-E-V10
Application Note
FR FAMILY
32-BIT MICROCONTROLLER
MB91460 SERIES
START91460.ASM
APPLICATION NOTE

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  • Page 1 Fujitsu Microelectronics Europe MCU-AN-300021-E-V10 Application Note FR FAMILY 32-BIT MICROCONTROLLER MB91460 SERIES START91460.ASM APPLICATION NOTE...

  • Page 2: Revision History

    Start91460.asm Revision History Revision History Date Issue 2007-03-30 First draft This document contains 29 pages. MCU-AN-300021-E-V10 - 2 - © Fujitsu Microelectronics Europe GmbH...

  • Page 3: Warranty And Disclaimer

    Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer´s use or the transport.

  • Page 4: Table Of Contents

    CAN clock (PSCLOCKSOURCE, PSDVC, CANCLOCK) ........21 Voltage Regulator (REGULATORCTRL, REGULATORSEL) ......... 23 Memory Controller (FLASHCONTROL, FLASHREADT, FLASHMWT2) ....25 4 SECTION AND DATA DECLARATION ................28 Default Sections ...................... 28 Additional Sections....................29 MCU-AN-300021-E-V10 - 4 - © Fujitsu Microelectronics Europe GmbH...

  • Page 5: Introduction

    - Configuration part for easy step by step set-up of the startup code - Startup code for pre-setting of core and external bus registers - Startup code for memory initialization according to FCC911-compiler sections - Startup file is linkage order independent © Fujitsu Microelectronics Europe GmbH - 5 - MCU-AN-300021-E-V10...

  • Page 6: Settings Of The Start91460.Asm

    Note: If the device MB91469G is selected, the section SECURITY_VECTORS is located from 0x24:8000 – 0x24:800F. Note: If the ROMless device MB91461R is selected no section SECURITY_VECTORS is reserved. MCU-AN-300021-E-V10 - 6 - © Fujitsu Microelectronics Europe GmbH...

  • Page 7: Stack Type And Stack Size (Stackuse

    For estimating necessary stack size the compiler offers the “-INF stack” option. With it the compiler generates stack information files (extension “stk”), which list the number of bytes necessary to execute each function. These stack information files are already available for © Fujitsu Microelectronics Europe GmbH - 7 - MCU-AN-300021-E-V10...

  • Page 8: Stack_Fill, Stack_Pattern

    The segment CODE has to be renamed to IRAM for the code, which should be copied the the instruction RAM during the startup. To rename the segment CODE to IRAM, the following pragma instruction can be used. MCU-AN-300021-E-V10 - 8 - © Fujitsu Microelectronics Europe GmbH...

  • Page 9: Low-Level Library Interface (Clibinit)

    If using C++ sources, activate this function to create the section EXT_CTOR_DTOR. Available settings for CPLUSPLUS: - ON - OFF Example: C++ is not used. #set CPLUSPLUS ; <<< activate if c++ files are used © Fujitsu Microelectronics Europe GmbH - 9 - MCU-AN-300021-E-V10...

  • Page 10: Clock Configuration

    = 4 MHz, PLL is activated CPU clock (CLKB) = 80 MHZ Peripheral clock (CLKP) = 20 MHZ Ext. bus clock (CLKT) = 40 MHZ CAN clock (CLKCAN) = 20 MHz, using PLLx MCU-AN-300021-E-V10 - 10 - © Fujitsu Microelectronics Europe GmbH...

  • Page 11: Select Clock Modulator (Clomo, Cmpr)

    The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. Available settings for CLOMO: - ON - OFF © Fujitsu Microelectronics Europe GmbH - 11 - MCU-AN-300021-E-V10...
  • Page 12 The clock modulator should be enabled and the value of the CMPR should be set to 0x026F. #set CLOMO ; <<< Enable /disable clock modulator #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR MCU-AN-300021-E-V10 - 12 - © Fujitsu Microelectronics Europe GmbH...

  • Page 13: External Bus Interface (Extbus)

    MEMORY SETTING REGISTER for extend type - A for SDRAM/FCRAM auto Refresh control register - RCR - TCR Pin/Timing Control Register - CHER Cache Enable Register - PFR0 – 10 Port Function Register 0-7 © Fujitsu Microelectronics Europe GmbH - 13 - MCU-AN-300021-E-V10...

  • Page 14: User Clock Settings (Clockspeed == Clock_User)

    The clock modulator is not part of the user clock settings, but part of the general settings. The user clock settings can be found in the startup91460.asm in the chapter ”5.1 CLOCKSPEED == CLOCK_USER”. MCU-AN-300021-E-V10 - 14 - © Fujitsu Microelectronics Europe GmbH...

  • Page 15: Clock Source (Clocksource, Enable_Subclock)

    - OFF Sub clock is not enabled Example: The PLL should be used and the sub clock should not be enabled. #set CLOCKSOURCE MAINPLLCLOCK ;<<< Clocksource #set ENABLE_SUBCLOCK OFF ;<<< Subclock: ON/OFF © Fujitsu Microelectronics Europe GmbH - 15 - MCU-AN-300021-E-V10...

  • Page 16: Pll Ratio (Pllspeed)

    0x0111 72 MHz PLLx19 0x0112 76 MHz PLLx20 0x0113 80 MHz PLLx21 0x0114 84 MHz Not: MB91V460A, MB91464A, MB91465K, MB91463N, MB91467R PLLx22 0x0115 88 MHz Not: MB91V460A, MB91464A, MB91465K, MB91463N, MB91467R MCU-AN-300021-E-V10 - 16 - © Fujitsu Microelectronics Europe GmbH...
  • Page 17 Note: Never exceed the maximum operation frequency. Check the corresponding data sheet. Example: The PLL should be set to 4 MHz x 16 = 64 MHz. #set PLLSPEED 0x010F ;<<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz © Fujitsu Microelectronics Europe GmbH - 17 - MCU-AN-300021-E-V10...

  • Page 18: Pll Auto Gear-Up And -Down (Div_G, Mul_G)

    0x0F PLLx17 0x0F 0x0F PLLx18 0x0F 0x13 PLLx19 0x0F 0x13 PLLx20 0x0F 0x13 PLLx21 0x0F 0x13 Not: MB91V460A, MB91464A, MB91465K, MB91463N, MB91467R PLLx22 0x0F 0x17 Not: MB91V460A, MB91464A, MB91465K, MB91463N, MB91467R MCU-AN-300021-E-V10 - 18 - © Fujitsu Microelectronics Europe GmbH...
  • Page 19 Note: MUL_G corresponds to the register PLLMULG at the addresses 0x48Fh. Example: The PLL should be set to 4 MHz x 16 = 64 MHz. #set DIV_G 0x0F ;<<< 0x48Eh: PLLDIVG; #set MUL_G 0x0F ;<<< 0x48Fh: PLLMULG; © Fujitsu Microelectronics Europe GmbH - 19 - MCU-AN-300021-E-V10...

  • Page 20: Clock Divider (Cpuclock, Perclock, Extbusclock)

    Note: PERCLOCK corresponds to the register DIV0R_P at the addresses 0x486h. Note: EXTBUSCLOCK corresponds to the register DIV1R_T at the addresses 0x487h. Note: Never exceed the maximum operation frequency. Check the corresponding data sheet. MCU-AN-300021-E-V10 - 20 - © Fujitsu Microelectronics Europe GmbH...

  • Page 21: Can Clock (Psclocksource, Psdvc, Canclock)

    128 MHz 4 MHz PLLx9 36 MHz 144 MHz 4 MHz PLLx10 40 MHz 160 MHz 4 MHz PLLx11 44 MHz 88 MHz 4 MHz PLLx12 48 MHz 96 MHz 4 MHz © Fujitsu Microelectronics Europe GmbH - 21 - MCU-AN-300021-E-V10...
  • Page 22 CAN is not influenced by the clock modulation. If the CLKCAN source is set core clock CLKB then the clock for the CAN is also modulated (if the clock modulator is enabled). MCU-AN-300021-E-V10 - 22 - © Fujitsu Microelectronics Europe GmbH...

  • Page 23: Voltage Regulator (Regulatorctrl, Regulatorsel)

    | | | | |___________ Reserved | | | |_____________ MSTBO (read only) | | |_______________ Reserved | |_________________ Reserved |___________________ Reserved BIT[7:5]: Reserved BIT[4]: MSTBO - Main regulator Standby output flag. (read only) © Fujitsu Microelectronics Europe GmbH - 23 - MCU-AN-300021-E-V10...
  • Page 24 Main and flash operation mode should be 1.8 V and the sub regulator voltage should be set to 1.8 V, too. #set REGULATORCTRL 0x00 ;<<< 0x4CFh: REGCTR; #set REGULATORSEL 0x06 ;<<< 0x4CEh: REGSEL; MCU-AN-300021-E-V10 - 24 - © Fujitsu Microelectronics Europe GmbH...

  • Page 25: Memory Controller (Flashcontrol, Flashreadt, Flashmwt2)

    - 1 - Memory mapped TAG RAM access enabled BIT[7]: FLUSH - Flush instruction cache entries 0 - Flushing the instruction cache entries has been completed 1 - Actually flushing the instruction cache entries © Fujitsu Microelectronics Europe GmbH - 25 - MCU-AN-300021-E-V10...
  • Page 26 - Wait cycles for F-Bus general purpose RAM memory access ATD[2:0]: - Duration of the ATDIN signal for FLASH memory access EQ[3:0]: - Duration of the EQIN signal for FLASH memory access MCU-AN-300021-E-V10 - 26 - © Fujitsu Microelectronics Europe GmbH...
  • Page 27 The memory controller should be configured for the MB91F467D. The core frequency should be 64 MHz. #set FLASHCONTROL 0x032 ;<<< 0x7002h: FCHCR; #set FLASHREADT 0xC413 ;<<< 0x7004h: FMWT; #set FLASHMWT2 0x10 ;<<< 0x7006h: FMWT2; © Fujitsu Microelectronics Europe GmbH - 27 - MCU-AN-300021-E-V10...

  • Page 28: Section And Data Declaration

    #pragma intvect. The default section name is INTVECT. C++ Init section: This section is where tables for indicating the entry of functions constituting and destroying static objects are stored. It must be used at startup. MCU-AN-300021-E-V10 - 28 - © Fujitsu Microelectronics Europe GmbH...

  • Page 29: Additional Sections

    User stack: This section is where the user stack is located. The size of the user stack can be defined in the startup code. Security vectors: This section stores the security vectors. Instruction RAM Section: This section stores the code, which should be executed in the IRAM. © Fujitsu Microelectronics Europe GmbH - 29 - MCU-AN-300021-E-V10...

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Mb91460 seriesStart91460.asm

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