Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) - Intel PXA255 Developer's Manual

Figure 6-23. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)
CLK_MEM
nCS[0]
MA[25:2]
MA[1:0]
nWE
nOE
RDnWR
MD[31:0]
DQM[3:0]
nADV(nSDCAS)
* A command and data write to Flash
In Figure 6-23
•
tAS = Address setup to nCS = 1 MEMCLK
•
tCES = nCS setup to nWE = 2 MEMCLKs
•
tASW = Address setup time to nWE asserted = 3 MEMCLKs
•
tDSWH = Write data, DQM setup to nWE deasserted = (RDF+2) MEMCLKs
•
tDH = Data, DQM hold after nWE deasserted = 1 MEMCLKs
•
tCEH = nCS held asserted after nWE deasserted = 1 MEMCLK
•
tAH = Address hold after nWE deasserted = 1 MEMCLKs
Intel® PXA255 Processor Developer's Manual
0ns 50ns
tAS
command address
'0'
tCES
tASW
RDF+1 RDF+1
tDSWH
MSC0:RDF0 = 2, RRR0 = 2
some of the parameters are defined as follows:
100ns
RRR*2+1 RRR*2+1
tCEH
tAH
tDH
CMD
"00"
tAS = Address Setup to nCS asserted = 1 clk_mem
tAH = Address Hold from nWE deasserted = 2 clk_mem
tASW = Address Setup to nWE asserted = 3 clk_mem
tCES = nCS setup to nWE asserted = 2 clk_mems
tCEH = nCS hold from nWE deasserted = 1 clk_mem
tDSWH = MD/DQM setup to nWE deasserted = RDF+2 clk_mems
tDH = MD/DQM hold from nWE deasserted = 1 clk_mem
Memory Controller
150ns
tAS
data address
'0'
tCES
tASW tAH
RDF+1 RDF+1
tDH
tDSWH
DATA
"00"
200ns
tCEH
6-59