Mode 3 32-Bit Write Transfer - Intel IXP28XX Manual

IXP28XX Network Processor
Slowport
Figure 85.
Note: The IXP28XX CSR Transmit Enable Register (SP_TXE) can be used to delay the data and relevant
140
Downloaded from Elcodis.com electronic components distributor

Mode 3 32-Bit Write Transfer

SP_ACK_L
SP_AD[7:0]
SP_ALE_L
SP_CLK
SP_CP
SP_CS_L[1:0]
SP_DIR
SP_OE_L
SP_RD_L
SP_WR_L
To pack the 32-bit write data, the IXP28XX network processor drives a byte of write data onto the
SP_AD bus in four cycles that are qualified with the rising edge of the SP_CP signal, with the
SP_OE_L && SP_DIR signal being active, i.e., SP_OE_L = 0 and SP_DIR = 1. On every rising
edge of the SP_CP signal with SP_OE_L && SP_DIR asserted, the data is shifted into a register
implemented in the glue logic device – from least significant byte (LSB) through most significant
byte (MSB).
Slowport signals in relation to the SP_CLK. For programming information, refer to the Intel®
IXP2800 Network Processor Hardware Reference Manual.
40 2 0 3 0
3 1
Hardware Design Guide
3
B0600-01