Burst Mode Details; Adding Wait States To Burst Cycles - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4.3.4

Burst Mode Details

4.3.4.1

Adding Wait States to Burst Cycles

Burst cycles need not return data on every clock. The Intel486 processor strobes data into the chip
only when either RDY# or BRDY# is asserted. Deasserting BRDY# and RDY# adds a wait state
to the transfer. A burst cycle where two clocks are required for every burst item is shown in
Figure 4-17.
Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
A3–A2
BE3#–BE0#
RDY#
BRDY#
KEN#
BLAST#
DATA
†
To Processor
4-26
T1 T2 T2
†
Figure 4-17. Slow Burst Cycle
T2 T2 T2
† †
T2 T2 T2
†
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