intel 855GME Manuals

Manuals and User Guides for intel 855GME. We have 2 intel 855GME manuals available for free PDF download: Design Manual

Intel 855GME Design Manual

Intel 855GME Design Manual (362 pages)

Chipset Platform

Brand: Intel | Category: Computer Hardware | Size: 5.56 MB

Table of Contents

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intel 855GME Design Manual

intel 855GME Design Manual (320 pages)

Chipset, ICH Embedded Platform

Brand: intel | Category: Computer Hardware | Size: 4.92 MB

Table of Contents

Table of Contents
3
Introduction

21
- Conventions and Terminology
  21
  - Reference Documents
    23
System Overview

25
General Design Considerations

33
- Nominal Board Stack-Up
  33
- Recommended Board Stack-Up Dimensions
  34
  - Alternate Stack-Ups
    35
4 Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines

37
System Memory Design Guidelines (DDR-SDRAM)

123
- Introduction
  123
- Length Matching and Length Formulas
  124
- Package Length Compensation
  124
- Length Matching Formulas
  124
  - Topologies and Routing Guidelines
    125
    
    Clock Signals - SCK[5:0], SCK[5:0]
    125
    
    Clock Topology Diagram
    125
    
    DDR Clock Routing Guidelines
    126
- DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#)
  126
  - Clock Length Matching Requirements
    127
  - Clock Reference Lengths
    128
  - Clock Length Package Table
    130
  - Data Signals - SDQ[71:0], SDM[8:0], SDQS[8:0]
    130
    
    Data Bus Topology
    131
- Data Signal Routing Topology
  131
- Control Signal to DIMM Mapping
  138
- Control Signal to Clock Trace Length Matching Diagram
  141
  - Control Group Package Length Table
    142
  - Command Signals - SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE
    142
    
    Command Signal Routing Topology
    142
- Control Group Package Lengths
  142
- Command Group Package Lengths
  146
- Control Signal to DIMM Mapping
  146
  - CPC Signal Routing Topology
    147
- CPC Control Signal Routing Topology
  147
  - CPC Signal Routing Guidelines
    148
  - CPC to Clock Length Matching Requirements
    148
- CPC Control Signal Routing Guidelines
  148
  - CPC Group Package Length Table
    150
  - Feedback - RCVENOUT#, RCVENIN
    150
  - ECC Guidelines
    150
    
    GMCH ECC Functionality
    150
- CPC Group Package Lengths
  150
  - DRAM Clock Flexibility
    151
Integrated Graphics Display Port

153
- Analog RGB/CRT Guidelines
  153
  - Ramdac/Display Interface
    153
  - Reference Resistor (RSET)
    153
  - RAMDAC Board Design Guidelines
    154
  - DAC Routing Guidelines
    155
- Recommended GMCH DAC Components
  156
  - DAC Power Requirements
    157
  - HSYNC and VSYNC Design Considerations
    158
  - DDC and I C Design Considerations
    158
  - LVDS Transmitter Interface
    158
    
    Length Matching Constraints
    159
    
    Package Length Compensation
    159
    
    LVDS Routing Guidelines
    160
  - Digital Video out Port
    161
    
    DVO Interface Signal Groups
    162
    
    DVO/I2C to AGP Pin Mapping
    162
    
    DVOB and DVOC Port Interface Routing Guidelines
    163
    
    Length Mismatch Requirements
    163
    
    Package Length Compensation
    164
    
    DVOB and DVOC Routing Guidelines
    165
- Rset Placement
  156
- DVOB and DVOC Routing Guideline Summary
  165
- DVOB and DVOC Simulations Model
  167
- GVREF Reference Voltage
  171
AGP Port Design Guidelines

173
- AGP Interface
  173
  - Agp 2.0
    173
  - AGP Interface Signal Groups
    174
- AGP Routing Guidelines
  175
  - Timing Domain Routing Guidelines
    175
    
    Trace Length Mismatch
    175
    
    Trace Length Requirements for AGP 1X
    175
    
    Trace Spacing Requirements
    175
  - 2X/4X Timing Domain Routing Guidelines
    175
    
    Trace Length Requirements for AGP 2X/4X
    175
    
    Trace Spacing Requirements
    176
- Layout Guidelines for AGP 2X/4X Signals
  176
  - Trace Length Mismatch Requirements
    177
  - AGP Clock Skew
    177
  - AGP Signal Noise Decoupling Guidelines
    178
  - AGP Interface Package Lengths
    178
  - AGP Routing Ground Reference
    179
  - Pull-Ups
    180
  - AGP VDDQ and VCC
    181
  - VREF Generation for AGP 2.0 (2X and 4X)
    181
    
    AGP Compensation
    181
    
    AGP Interface (2X/4X)
    181
    
    PM_SUS_CLK/AGP_PIPE# Design Consideration
    181
- DPMS Circuit
  182
Hub Interface

183
Intel ® 6300ESB Design Guidelines

191
- Serial ATA Interface
  191
  - Layout Guidelines
    191
    
    General Routing and Placement
    191
    
    Serial ATA Trace Separation
    191
    
    SATA BIAS Connections
    192
    
    Serial ATA Trace Length Guidelines
    192
    
    Serial ATA Trace Length Pair Matching
    192
- SATA Routing Summary
  192
  - SATALED# Implementation
    193
- Serial ATA Trace Spacing Recommendation
  192
- SATA BIAS Connections
  193
- SATA BIAS Routing Summary
  193
- SATALED# Circuitry Example
  193
- IDE Interface
  194
  - Cabling
    194
- IDE Routing Summary
  194
- IDE Signal Groups
  194
- Cable Detection for Ultra ATA/66 and Ultra ATA/100
  195
  - Combination Host-Side/Device-Side Cable Detection
    195
  - Device-Side Cable Detection
    196
- Combination Host-Side/Device-Side IDE Cable Detection
  196
- Device Side IDE Cable Detection
  197
  - Primary IDE Connector Requirements
    198
- Connection Requirements for Primary IDE Connector
  198
  - Secondary IDE Connector Requirements
    199
- Connection Requirements for Secondary IDE Connector
  199
- 6300ESB AC'97 - Codec Connection
  200
- AC'97 AC_BIT_CLK Routing Summary
  201
- 6300ESB AC'97 - AC_SDIN Topology
  202
- 6300ESB AC'97 - AC_SDOUT/AC_SYNC Topology
  202
- AC'97 AC_SDOUT/AC_SYNC Routing Summary
  202
  - AC'97 Routing
    203
- AC'97 AC_SDIN Routing Summary
  203
  - Motherboard Implementation
    204
    
    Valid Codec Configurations
    205
  - SPKR Pin Consideration
    205
- Supported Codec Configurations
  205
  - AC_SDOUT Pin Consideration
    206
  - SIU0_DTR# Pin Consideration
    206
- Communication Network Riser
  206
  - AC'97 Audio Codec Detect Circuit and Configuration Options
    207
    
    CNR 1.2 AC'97 Disable and Demotion Rules for the Motherboard
    207
- CNR Interface
  207
- Signal Descriptions
  207
- Motherboard AC'97 CNR Implementation with a Single Codec down on Board
  208
  - CNR Routing Summary
    209
- Motherboard AC'97 CNR Implementation Without Codec down on Board
  209
- Usb 2.0
  210
  - Layout Guidelines
    210
    
    General Routing and Placement
    210
    
    USB 2.0 Trace Separation
    211
    
    USB BIAS Connections
    211
- Recommended General USB Trace Spacing (55 Ω ± 10%)
  211
  - USB 2.0 Termination
    212
  - USB 2.0 Trace Length Pair Matching
    212
  - USB 2.0 Trace Length Guidelines
    212
- Trace Routing
  211
- USB 2.0 Back Panel Trace Length Guidelines
  212
  - Plane Splits, Voids and Cut-Outs (Anti-Etch)
    213
    
    VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
    213
- USB BIAS Connections
  212
- USB BIAS Routing Summary
  212
- USB 2.0 CNR Trace Length Guidelines
  213
- USB 2.0 Front Panel Trace Length Guidelines
  213
  - GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
    214
  - USB Power Line Layout Topology
    214
  - EMI Considerations
    214
    
    Common-Mode Chokes
    215
  - Esd
    215
- Common-Mode Choke
  215
  - Front Panel Solutions
    216
    
    Conductor Resistance (Table 6-6 from USB 2.0 Specification)
    216
    
    Internal USB Cables
    216
    
    Motherboard/Pcb Mating Connector
    217
- Front Panel Header Pin-Out
  217
  - Front Panel Connector Card
    218
- Front Panel Header Schematic
  218
- Low Pin Count (LPC) Interface
  219
  - General Routing and Placement
    220
  - LPC Trace Length Matching
    220
  - LPC Interface Routing Guidelines
    220
- LPC Interface Routing Summary
  221
  - Smbus Architecture & Design Considerations
    222
    
    General Design Issues / Notes
    222
    
    Smbus Design Considerations
    222
- Smbus 2.0/Smlink Interface
  221
- SMBUS 2.0/Smlink Interface
  222
  - High Power/Low Power Mixed Architecture
    223
  - Calculating the Physical Segment Pull-Up Resistor
    223
- Bus Capacitance Reference Chart
  224
- Bus Capacitance/Pull-Up Resistor Relationship
  224
- Pci
  224
  - PCI Routing Summary
    224
- PCI Bus Layout Example
  225
- PCI Bus Layout Example with IDSEL
  225
- PCI 33 Mhz Clock Signals Routing Summary
  226
  - PIRQ Routing Example
    227
- PCI Data Signals Routing Summary
  226
- IOAPIC Interrupt Inputs 16 through 23 Usage
  227
- PCI-X Design Guidelines
  228
- PCI-X Frequencies
  228
  - 66 Mhz Topologies and Trace Length
    229
- PCI-X Routing Summary
  228
- PCI-X Slot/Device Configurations
  228
- 66 Mhz PCI-X, One down Device Configuration
  229
- 66 Mhz PCI-X, Two Slots, Two down Devices Configuration
  229
- 66 Mhz PCI-X, Two Slots, Two down Devices Routing Length Parameters
  229
- 66 Mhz PCI-X, One down Device Routing Length Parameters
  230
- 66 Mhz PCI-X, Three Slot Configuration
  230
- 66 Mhz PCI-X, Three Slot Configuration Routing Length Parameters
  230
  - PCI-X Clock Length Matching Guidelines
    231
  - IDSEL Series Resistor
    231
- 66 Mhz Clock Signal Configuration
  231
  - PCI-X Secondary Bus Reset
    232
    
    Issues with Sharing PME
    232
    
    PME# Signal Sharing
    232
    
    Secondary Bus Reset Not Utilized
    232
- IDSEL to PXAD Bit Assignment
  232
  - Rtc
    233
- RTCX1 and SUSCLK Relationship in 6300ESB
  233
  - RTC Crystal
    234
- External Circuitry for the 6300ESB RTC
  234
  - External Capacitors
    235
- External Circuitry in the 6300ESB Without Use of Internal RTC
  234
- RTC Routing Summary
  235
  - RTC Layout Considerations
    236
  - RTC External Battery Connection
    236
- Diode Circuit to Connect RTC External Battery
  237
  - RTC External RTCRST# Circuit
    238
  - VBIAS DC Voltage and Noise Measurements
    238
- RTCRST# External Circuit for the 6300ESB RTC
  238
  - Susclk
    239
  - RTC-Well Input Strap Requirements
    239
  - Serial I/O
    239
    
    Serial I/O Interface Not Utilized
    239
  - Fwh
    240
    
    FWH Decoupling
    240
    
    FWH INIT# Voltage Compatibility
    240
    
    FWH Vendors
    240
    
    In-Circuit FWH Programming
    240
    
    FWH VPP Design Guidelines
    241
  - GPIO Summary
    242
  - Power Management
    244
    
    Power-Well Isolation Control Strap Requirements
    244
    
    PWRBTN# Usage Model
    244
    
    SYS_RESET# Usage Model
    244
- SYS_RESET# and PWRBTN# Connection
  244
- RTC Power Well Isolation Control
  245

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