intel 855GME Manuals

Manuals and User Guides for intel 855GME. We have 1 intel 855GME manual available for free PDF download: Design Manual

intel 855GME Design Manual

intel 855GME Design Manual (320 pages)

Chipset, ICH Embedded Platform

Brand: intel | Category: Computer Hardware | Size: 4.92 MB

Table of Contents

- 3
  Table of Contents
21
Introduction
- 21
  Conventions and Terminology
  - 23
    Reference Documents
25
System Overview
33
General Design Considerations
- 33
  Nominal Board Stack-Up
- 34
  Recommended Board Stack-Up Dimensions
  - 35
    Alternate Stack-Ups
37
Intel ® Pentium ® M/Celeron ® M Processor FSB Design and Power Delivery Guidelines
123
System Memory Design Guidelines (DDR-SDRAM)
- 123
  Introduction
- 124
  Length Matching and Length Formulas
- 124
  Package Length Compensation
- 124
  Length Matching Formulas
  - 125
    Topologies and Routing Guidelines
    - 125
      Clock Signals - SCK[5:0], SCK[5:0]
    - 125
      Clock Topology Diagram
    - 126
      DDR Clock Routing Guidelines
- 126
  DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#)
  - 127
    Clock Length Matching Requirements
  - 128
    Clock Reference Lengths
  - 130
    Clock Length Package Table
  - 130
    Data Signals - SDQ[71:0], SDM[8:0], SDQS[8:0]
    - 131
      Data Bus Topology
- 131
  Data Signal Routing Topology
- 138
  Control Signal to DIMM Mapping
- 141
  Control Signal to Clock Trace Length Matching Diagram
  - 142
    Control Group Package Length Table
  - 142
    Command Signals - SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE
    - 142
      Command Signal Routing Topology
- 142
  Control Group Package Lengths
- 146
  Command Group Package Lengths
- 146
  Control Signal to DIMM Mapping
  - 147
    CPC Signal Routing Topology
- 147
  CPC Control Signal Routing Topology
  - 148
    CPC Signal Routing Guidelines
  - 148
    CPC to Clock Length Matching Requirements
- 148
  CPC Control Signal Routing Guidelines
  - 150
    CPC Group Package Length Table
  - 150
    Feedback - RCVENOUT#, RCVENIN
  - 150
    ECC Guidelines
    - 150
      GMCH ECC Functionality
- 150
  CPC Group Package Lengths
  - 151
    DRAM Clock Flexibility
153
Integrated Graphics Display Port
- 153
  Analog RGB/CRT Guidelines
  - 153
    Ramdac/Display Interface
  - 153
    Reference Resistor (RSET)
  - 154
    RAMDAC Board Design Guidelines
  - 155
    DAC Routing Guidelines
- 156
  Recommended GMCH DAC Components
  - 157
    DAC Power Requirements
  - 158
    HSYNC and VSYNC Design Considerations
  - 158
    DDC and I C Design Considerations
  - 158
    LVDS Transmitter Interface
    - 159
      Length Matching Constraints
      - 159
        Package Length Compensation
    - 160
      LVDS Routing Guidelines
  - 161
    Digital Video Out Port
    - 162
      DVO Interface Signal Groups
      - 162
        DVO/I2C to AGP Pin Mapping
    - 163
      DVOB and DVOC Port Interface Routing Guidelines
      - 163
        Length Mismatch Requirements
      - 164
        Package Length Compensation
      - 165
        DVOB and DVOC Routing Guidelines
- 156
  Rset Placement
- 165
  DVOB and DVOC Routing Guideline Summary
- 167
  DVOB and DVOC Simulations Model
- 171
  GVREF Reference Voltage
173
AGP Port Design Guidelines
- 173
  AGP Interface
  - 173
    Agp 2.0
  - 174
    AGP Interface Signal Groups
- 175
  AGP Routing Guidelines
  - 175
    Timing Domain Routing Guidelines
    - 175
      Trace Length Requirements for AGP 1X
    - 175
      Trace Spacing Requirements
    - 175
      Trace Length Mismatch
  - 175
    2X/4X Timing Domain Routing Guidelines
    - 176
      Trace Spacing Requirements
- 176
  Layout Guidelines for AGP 2X/4X Signals
  - 177
    Trace Length Mismatch Requirements
  - 177
    AGP Clock Skew
  - 178
    AGP Signal Noise Decoupling Guidelines
  - 178
    AGP Interface Package Lengths
  - 179
    AGP Routing Ground Reference
  - 180
    Pull-Ups
  - 181
    AGP VDDQ and VCC
  - 181
    VREF Generation for AGP 2.0 (2X and 4X)
    - 181
      AGP Interface (2X/4X)
    - 181
      AGP Compensation
    - 181
      PM_SUS_CLK/AGP_PIPE# Design Consideration
- 182
  DPMS Circuit
183
Hub Interface
191
Intel ® 6300ESB Design Guidelines
- 191
  Serial ATA Interface
  - 191
    Layout Guidelines
    - 191
      General Routing and Placement
    - 191
      Serial ATA Trace Separation
    - 192
      Serial ATA Trace Length Pair Matching
    - 192
      Serial ATA Trace Length Guidelines
    - 192
      SATA BIAS Connections
- 192
  SATA Routing Summary
  - 193
    SATALED# Implementation
- 192
  Serial ATA Trace Spacing Recommendation
- 193
  SATA BIAS Connections
- 193
  SATA BIAS Routing Summary
- 193
  SATALED# Circuitry Example
- 194
  IDE Interface
  - 194
    Cabling
- 194
  IDE Routing Summary
- 194
  IDE Signal Groups
- 195
  Cable Detection for Ultra ATA/66 and Ultra ATA/100
  - 195
    Combination Host-Side/Device-Side Cable Detection
  - 196
    Device-Side Cable Detection
- 196
  Combination Host-Side/Device-Side IDE Cable Detection
- 197
  Device Side IDE Cable Detection
  - 198
    Primary IDE Connector Requirements
- 198
  Connection Requirements for Primary IDE Connector
  - 199
    Secondary IDE Connector Requirements
- 199
  Connection Requirements for Secondary IDE Connector
- 200
  6300ESB AC'97 - Codec Connection
- 201
  AC'97 AC_BIT_CLK Routing Summary
- 202
  6300ESB AC'97 - AC_SDIN Topology
- 202
  6300ESB AC'97 - AC_SDOUT/AC_SYNC Topology
- 202
  AC'97 AC_SDOUT/AC_SYNC Routing Summary
  - 203
    AC'97 Routing
- 203
  AC'97 AC_SDIN Routing Summary
  - 204
    Motherboard Implementation
    - 205
      Valid Codec Configurations
  - 205
    SPKR Pin Consideration
- 205
  Supported Codec Configurations
  - 206
    AC_SDOUT Pin Consideration
  - 206
    SIU0_DTR# Pin Consideration
- 206
  Communication Network Riser
  - 207
    AC'97 Audio Codec Detect Circuit and Configuration Options
    - 207
      CNR 1.2 AC'97 Disable and Demotion Rules for the Motherboard
- 207
  CNR Interface
- 207
  Signal Descriptions
- 208
  Motherboard AC'97 CNR Implementation with a Single Codec Down On Board
  - 209
    CNR Routing Summary
- 209
  Motherboard AC'97 CNR Implementation Without Codec Down On Board
- 210
  Usb 2.0
  - 210
    Layout Guidelines
    - 210
      General Routing and Placement
    - 211
      USB 2.0 Trace Separation
    - 211
      USB BIAS Connections
- 211
  Recommended General USB Trace Spacing (55 Ω ± 10%)
  - 212
    USB 2.0 Termination
  - 212
    USB 2.0 Trace Length Pair Matching
  - 212
    USB 2.0 Trace Length Guidelines
- 211
  Trace Routing
- 212
  USB 2.0 Back Panel Trace Length Guidelines
  - 213
    Plane Splits, Voids and Cut-Outs (Anti-Etch)
    - 213
      VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
- 212
  USB BIAS Connections
- 212
  USB BIAS Routing Summary
- 213
  USB 2.0 CNR Trace Length Guidelines
- 213
  USB 2.0 Front Panel Trace Length Guidelines
  - 214
    GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
  - 214
    USB Power Line Layout Topology
  - 214
    EMI Considerations
    - 215
      Common-Mode Chokes
  - 215
    Esd
- 215
  Common-Mode Choke
  - 216
    Front Panel Solutions
- 217
  Front Panel Header Pin-Out
  - 218
    Front Panel Connector Card
- 218
  Front Panel Header Schematic
- 219
  Low Pin Count (LPC) Interface
  - 220
    General Routing and Placement
  - 220
    LPC Trace Length Matching
  - 220
    LPC Interface Routing Guidelines
- 221
  LPC Interface Routing Summary
  - 222
    Smbus Architecture & Design Considerations
    - 222
      Smbus Design Considerations
    - 222
      General Design Issues / Notes
- 221
  Smbus 2.0/Smlink Interface
- 222
  SMBUS 2.0/Smlink Interface
  - 223
    High Power/Low Power Mixed Architecture
  - 223
    Calculating the Physical Segment Pull-Up Resistor
- 224
  Bus Capacitance Reference Chart
- 224
  Bus Capacitance/Pull-Up Resistor Relationship
- 224
  Pci
  - 224
    PCI Routing Summary
- 225
  PCI Bus Layout Example
- 225
  PCI Bus Layout Example with IDSEL
- 226
  PCI 33 Mhz Clock Signals Routing Summary
  - 227
    PIRQ Routing Example
- 226
  PCI Data Signals Routing Summary
- 227
  IOAPIC Interrupt Inputs 16 Through 23 Usage
- 228
  PCI-X Design Guidelines
- 228
  PCI-X Frequencies
  - 229
    66 Mhz Topologies And Trace Length
- 228
  PCI-X Routing Summary
- 228
  PCI-X Slot/Device Configurations
- 229
  66 Mhz PCI-X, One Down Device Configuration
- 229
  66 Mhz PCI-X, Two Slots, Two Down Devices Configuration
- 229
  66 Mhz PCI-X, Two Slots, Two Down Devices Routing Length Parameters
- 230
  66 Mhz PCI-X, One Down Device Routing Length Parameters
- 230
  66 Mhz PCI-X, Three Slot Configuration
- 230
  66 Mhz PCI-X, Three Slot Configuration Routing Length Parameters
  - 231
    PCI-X Clock Length Matching Guidelines
  - 231
    IDSEL Series Resistor
- 231
  66 Mhz Clock Signal Configuration
  - 232
    PCI-X Secondary Bus Reset
    - 232
      Secondary Bus Reset Not Utilized
    - 232
      PME# Signal Sharing
      - 232
        Issues with Sharing PME
- 232
  IDSEL to PXAD Bit Assignment
  - 233
    Rtc
- 233
  RTCX1 and SUSCLK Relationship in 6300ESB
  - 234
    RTC Crystal
- 234
  External Circuitry for the 6300ESB RTC
  - 235
    External Capacitors
- 234
  External Circuitry in the 6300ESB Without Use of Internal RTC
- 235
  RTC Routing Summary
  - 236
    RTC Layout Considerations
  - 236
    RTC External Battery Connection
- 237
  Diode Circuit to Connect RTC External Battery
  - 238
    RTC External RTCRST# Circuit
  - 238
    VBIAS DC Voltage and Noise Measurements
- 238
  RTCRST# External Circuit for the 6300ESB RTC
  - 239
    Susclk
  - 239
    Rtc-Well Input Strap Requirements
  - 239
    Serial I/O
    - 239
      Serial I/O Interface Not Utilized
  - 240
    Fwh
    - 240
      FWH Vendors
    - 240
      FWH Decoupling
    - 240
      In-Circuit FWH Programming
    - 240
      FWH INIT# Voltage Compatibility
    - 241
      FWH VPP Design Guidelines
  - 242
    GPIO Summary
  - 244
    Power Management
    - 244
      SYS_RESET# Usage Model
    - 244
      PWRBTN# Usage Model
    - 244
      Power-Well Isolation Control Strap Requirements
- 244
  SYS_RESET# and PWRBTN# Connection
- 245
  RTC Power Well Isolation Control
247
Miscellaneous Logic
- 247
  Glue Chip 4
- 248
  Discrete Logic
- 249
  Individual Clock Breakdown
  - 251
    Clock Group Topologies and Routing Constraints
    - 251
      Host Clock Group
249
Platform Clock Routing Guidelines
- 249
  System Clock Groups
- 251
  Source Shunt Termination Topology
- 252
  Host Clock Group Routing Constraints
  - 253
    Host Clock Group General Routing Guidelines
  - 253
    Clock-To-Clock Length Matching and Compensation
  - 253
    EMI Constraints
  - 254
    CLK66 Clock Group
- 254
  CLK66 Clock Group Routing Constraints
  - 255
    CLK33 Clock Group
- 254
  CLK66 Clock Group Topology
- 255
  CLK33 Clock Group Routing Constraints
  - 256
    PCI Clock Group
  - 257
    CLK14 Clock Group
- 255
  CLK33 Group Topology
- 257
  CLK14 Clock Group Routing Constraints
  - 258
    DOTCLK Clock Group
- 257
  CLK14 Clock Group Topology
- 258
  DOTCLK Clock Topology
  - 259
    SSCCLK Clock Group
  - 260
    USBCLK Clock Group
- 260
  USBCLK Clock Topology
  - 261
    SRC Clock Group
    - 261
      SRC Clock Topology
- 261
  SCR/SCR# Routing Guidelines
- 261
  Source Shunt Termination
- 262
  Trace Spacing for SRC Clocks
  - 263
    SRC General Routing Guidelines
265
Schematic Checklist Summary
- 265
  Intel ® Pentium ® M/Celeron ® M Processor Checklist
  - 265
    Connection Recommendations
- 267
  Routing Illustration for INIT
  - 268
    In Target Probe (ITP)
- 268
  Voltage Translation Circuit for PROCHOT
  - 269
    Decoupling Recommendations
    - 269
      Vccp (I/O)
    - 269
      Vcca (Pll)
    - 269
      VCC (Core)
- 269
  VCC (CORE) Decoupling Recommendations
  - 270
    CK409 Clock Checklist
    - 270
      Connection Recommendations
  - 272
    Intel ® 855GME Chipset GMCH (82855GME) Checklist
    - 272
      System Memory
      - 272
        GMCH System Memory Interface Checklist
      - 274
        DDR DIMM Interface Checklist
- 274
  Reference Voltage Level for SMVREF
  - 275
    DIMM Decoupling Recommendation Checklist
  - 275
    Frontside Bus (FSB) Checklist
- 275
  FSB Checklist
  - 277
    Hub Interface Checklist
  - 277
    Voltage Generation Circuit
    - 278
      Graphics Interfaces Checklist
      - 278
        Low Voltage Digital Signalling (LVDS) Checklist
      - 278
        Digital Video Out (DVO) Checklist
- 278
  DVO Checklist
  - 280
    Digital-To-Analog Converter (DAC) Checklist
- 278
  LVDS Checklist
- 280
  DAC Checklist
  - 281
    Miscellaneous Signal Checklist
    - 281
      Intel ® Pentium ® M/Celeron ® M Processor GST[2:0] Configurations
    - 281
      GMCH Decoupling Recommendations Checklist
- 281
  GST[2:0] Configurations
- 282
  GMCH Decoupling Recommendations Checklist
  - 283
    Intel ® 6300ESB Checklist
    - 283
      PCI-X Interface Checklist
    - 285
      PCI Interface Checklist
    - 288
      Hub Interface Checklist
    - 288
      FWH/LPC Interface Checklist
    - 289
      GPIO Checklist
    - 290
      USB Checklist
    - 290
      Power Management Checklist
    - 291
      CPU Signals Checklist
    - 292
      System Management Checklist
    - 292
      RTC Checklist
    - 293
      UART Checklist
    - 294
      AC'97 Checklist
    - 294
      Miscellaneous Signals
- 294
  Miscellaneous Signals Checklist
  - 295
    Serial ATA Checklist
  - 295
    IDE Checklist
  - 297
    Power Checklist
299
Layout Checklist
- 299
  Processor Checklist
- 307
  Intel ® 855GME Chipset GMCH (82855GME) Layout Checklist
- 308
  Intel ® 855GME Chipset GMCH Layout Checklist
  - 312
    Intel ® 6300ESB Layout Checklist
- 315
  AC'97 Layout Checklist
  - 315
    RTC Layout Checklist
- 316
  FWH Decoupling Layout Checklist
- 316
  PCI Layout Checklist
- 316
  PCI-X Layout Checklist
- 317
  Power Delivery Checklist

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