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80960HA
Intel 80960HA Manuals
Manuals and User Guides for Intel 80960HA. We have
1
Intel 80960HA manual available for free PDF download: Datasheet
Intel 80960HA Datasheet (104 pages)
32-Bit High-Performance Superscalar Processor
Brand:
Intel
| Category:
Computer Hardware
| Size: 1.02 MB
Table of Contents
Product Features
1
Table of Contents
3
Removed Operating Frequency of 16/32 (Bus/Core) from 80960HD
6
July 1998
7
About this Document
9
Intel 80960Hx Processor
9
80960Hx Block Diagram
9
80960Hx Product Description
9
The I960 ® Processor Family
10
Key 80960Hx Features
10
Execution Architecture
10
Pipelined, Burst Bus
10
On-Chip Caches and Data RAM
11
Priority Interrupt Controller
11
Guarded Memory Unit
11
Dual Programmable Timers
12
Processor Self Test
12
Fail Codes for bist (Bit 7 = 1)
12
Remaining Fail Codes (Bit 7 = 0)
12
Instruction Set Summary
13
80960Hx Instruction Set
13
Package Information
14
80960HA/HD/HT Package Types and Speeds
14
Pin Descriptions
15
Pin Description Nomenclature
15
80960Hx Processor Family Pin Descriptions
16
80960Hx DC Characteristics
19
80960Hx Mechanical Data
20
80960Hx PGA Pinout
20
80960Hx 168-Pin PGA Pinout-View from Top (Pins Facing Down)
20
80960Hx 168-Pin PGA Pinout-View from Bottom (Pins Facing Up)
21
80960Hx 168-Pin PGA Pinout-Signal Name Order
23
80960Hx 168-Pin PGA Pinout-Pin Number Order
25
80960Hx PQ4 Pinout
26
80960Hx 208-Pin PQ4 Pinout
26
80960Hx PQ4 Pinout-Signal Name Order
27
80960Hx PQ4 Pinout-Pin Number Order
29
Package Thermal Specifications
31
Measuring 80960Hx PGA Case Temperature
31
80960Hx 168-Pin PGA Package Thermal Characteristics
32
Maximum T a at Various Airflows in °C (PGA Package Only)
32
80960Hx 208-Pin PQ4 Package Thermal Characteristics
33
Maximum T a at Various Airflows in °C (PQ4 Package Only)
33
Heat Sink Adhesives
34
Powerquad4 Plastic Package
34
Stepping Register Information
34
80960Hx Device Identification Register
34
80960Hx Device ID Model Types
35
Device ID Version Numbers for Different Steppings
35
Fields of 80960Hx Device ID
35
Sources for Accessories
36
Electrical Specifications
37
Absolute Maximum Ratings
37
Operating Conditions
37
Recommended Connections
38
VCC5 Pin Requirements (VDIFF )
38
VCC5 Current-Limiting Resistor
38
VCCPLL Pin Requirements
39
DC Specifications
40
AC Specifications
42
Hx AC Characteristics
42
80960Hx Boundary Scan Test Signal Timings
44
AC Characteristics Notes
44
AC Test Conditions
45
AC Timing Waveforms
46
CLKIN Waveform
46
Output Delay Waveform
46
Output Float Waveform
47
Input Setup and Hold Waveform
47
NMI, XINT7:0 Input Setup and Hold Waveform
47
Hold Acknowledge Timings
48
Bus Backoff (BOFF) Timings
48
TCK Waveform
49
Output Delay or Hold Vs. Load Capacitance
52
Output Delay Vs. Temperature
53
Output Hold Times Vs. Temperature
53
Bus Waveforms
54
V DIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
54
Non-Burst, Non-Pipelined Requests Without Wait States
57
Non-Burst, Non-Pipelined Read Request with Wait States
58
Non-Burst, Non-Pipelined Write Request with Wait States
59
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus
60
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus
61
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus
62
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus
63
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus
64
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus
65
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
66
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
67
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
68
Burst, Pipelined Read Request with Wait States, 32-Bit Bus
69
Burst, Pipelined Read Request with Wait States, 8-Bit Bus
70
Burst, Pipelined Read Request with Wait States, 16-Bit Bus
71
Using External READY
72
Terminating a Burst with BTERM
73
BREQ and BSTALL Operation
74
BOFF Functional Timing. BOFF Occurs During a Burst or Non-Burst Data Cycle
75
HOLD Functional Timing
76
LOCK Delays HOLDA Timing
77
FAIL Functional Timing
77
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions
78
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)
79
A Summary of Aligned and Unaligned Transfers for 16-Bit Bus
80
A Summary of Aligned and Unaligned Transfers for 8-Bit Bus
81
Idle Bus Operation
82
Bus States
83
80960Hx Boundary Scan Chain
84
Boundary Scan Description Language Example
88
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