E-8 Encoding Of 32-Bit Address Mode With "Mod R/M" Byte (No S-I-B Byte Present) - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table E-8. Encoding of 32-bit Address Mode with "mod r/m" Byte (No s-i-b Byte Present)
mod r/m
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
E-28
Effective Address
DS:[EAX]
DS:[ECX]
SS:[EDX]
SS:[EBX]
s-i-b is present
DS:[d32]
DS:[ESI]
DS:[EDI]
DS:[EAX + d8]
DS:[ECX + d8]
SS:[EDX + d8]
SS:[EBX + d8]
s-i-b is present
SS:[EBP + d8]
DS:[ESI + d8]
DS:[EDI + d8]
mod r/m Effective Address
10 000 DS:[EAX + d32]
10 001 DS:[ECX + d32]
10 010 SS:[EDX + d32]
10 011 SS:[EBX + d32]
10 100 s-i-b is present
10 101 SS:[EBP + d32]
10 110 SS:[ESI + d32]
10 111 DS:[EDI + d32]
11 000 register - see tables below
11 001 register - see tables below
11 010 register - see tables below
11 011 register - see tables below
11 100 register - see tables below
11 101 register - see tables below
11 110 register - see tables below
11 111
register - see tables below
Register Specified by r/m
During 16-bit Data Operations
Function of w Field
mod r/m
(when w = 0)
11 000 AL
11 001 CL
11 010 DL
11 011 BL
11 100 AH
11 101 CH
11 110 DH
11 111 BH
Register Specified by r/m
During 32-bit Data Operations
Function of w Field
mod r/m
(when w = 0)
11 000 AL
11 001 CL
11 010 DL
11 011 BL
11 100 AH
11 101 CH
11 110 DH
11 111 BH
(when w = 1)
AX
CX
DX
BX
SP
BP
SI
DI
(when w = 1)
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI