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Intel 80960MC Manuals
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Intel 80960MC manual available for free PDF download: Manual
Intel 80960MC Manual (39 pages)
EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
Brand:
Intel
| Category:
Computer Hardware
| Size: 1.12 MB
Table of Contents
Table of Contents
3
1 THE I960 ® MC PROCESSOR
5
Figure 1. 80960MC Programming Environment
5
Key Performance Features
6
Table 1. 80960MC Instruction Set
7
Data Types
8
Figure 2. Instruction Formats
8
Large Register Set
8
Memory Space and Addressing Modes
8
Table 2. Memory Addressing Modes
8
Instruction Cache
9
Multiple Register Sets
9
Register Scoreboarding
9
Figure 3. Multiple Register Sets Are Stored On-Chip
10
Floating-Point Arithmetic
10
Memory Management and Protection
10
High Bandwidth Local Bus
11
Multiple Processor Support
11
Multitasking Support
11
Synchronization and Communication
11
Table 3. Sample Floating-Point Execution Times (Μs) at 25 Mhz
11
Debug Features
12
Fault Detection
12
Interrupt Handling
12
Built-In Testability
13
Chmos
13
Compatibility with 80960K-Series
13
Inter-Agent Communications (IAC)
13
Table 4. 80960MC Pin Description: L-Bus Signals
13
Table 5. 80960MC Pin Description: Support Signals
15
2 Electrical Specifications
17
Power and Grounding
17
Power Decoupling Recommendations
17
Connection Recommendations
17
Characteristic Curves
17
Figure 4. Connection Recommendations for Low Current Drive Network
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Figure 5. Connection Recommendations for High Current Drive Network
17
Figure 6. Typical Supply Current Vs. Case Temperature
18
Figure 7. Typical Current Vs. Frequency (Room Temp)
18
Figure 8. Typical Current Vs. Frequency (Hot Temp)
19
Figure 9. Worst-Case Voltage Vs. Output Current on Open-Drain Pins
19
Figure 10. Capacitive Derating Curve
19
Test Load Circuit
20
Figure 11. Test Load Circuit for Three-State Output Pins
20
Figure 12. Test Load Circuit for Open-Drain Output Pins
20
DC Characteristics
21
Absolute Maximum Ratings
21
Table 6. DC Characteristics
21
AC Specifications
22
Figure 13. Drive Levels and Timing Relationships for 80960MC Signals
22
Figure 14. Timing Relationship of L-Bus Signals
23
Figure 15. System and Processor Clock Relationship
23
Table 7. 80960MC AC Characteristics (25 Mhz)
24
Figure 16. Processor Clock Pulse (CLK2)
25
Figure 17. RESET Signal Timing
25
Design Considerations
26
3 Mechanical Data
26
Packaging
26
Pin Assignment
26
Figure 18. HOLD Timing
26
Figure 19. 132-Lead Pin-Grid Array (PGA) Package
27
Figure 20. 80960MC PGA Pinout-View from Bottom (Pins Facing Up)
28
Figure 21. 80960MC PGA Pinout-View from Top (Pins Facing Down)
29
Pinout
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Table 8. 80960MC PGA Pinout - in Pin Order
30
Table 9. 80960MC PGA Pinout - in Signal Order
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Package Thermal Specification
32
Table 10. 80960MC PGA Package Thermal Characteristics
32
Figure 22. 25 Mhz Maximum Allowable Ambient Temperature
33
4 Waveforms
34
Figure 23. Non-Burst Read and Write Transactions Without Wait States
34
Figure 24. Burst Read and Write Transaction Without Wait States
34
Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States
34
Figure 26. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)
34
Figure 27. Interrupt Acknowledge Transaction
34
Figure 28. Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master)
34
5 Revision History
39
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