Intel 460GX Manuals

Manuals and User Guides for Intel 460GX. We have 1 Intel 460GX manual available for free PDF download: Software Developer’s Manual

Intel 460GX Software Developer’s Manual

Intel 460GX Software Developer’s Manual (294 pages)

Chipset System

Brand: Intel | Category: Computer Hardware | Size: 2.89 MB

Table of Contents

Table of Contents
3
1 Introduction

13
- System Overview
  13
- Diagram of a Typical Intel® 460GX Chipset-Based System with AGP
  13
  - Component Overview
    14
- Intel® 460GX Chipset Components
  14
  - Product Features
    15
  - Itanium™ Processor System Bus Support
    15
  - DRAM Interface Support
    16
  - I/O Support
    16
    
    PXB Features
    16
    
    WXB Features
    17
    
    GXB Features
    17
  - RAS Features
    17
  - Other Platform Components
    18
    
    I/O & Firmware Bridge (IFB)
    18
    
    Programmable Interrupt Device (PID)
    18
  - Reference Documents
    18
  - Revision History
    19
2 Register Descriptions

21
- Access Mechanism
  21
- Access Restrictions
  22
  - Partitioning
    22
- Device Mapping on Bus CBN
  22
  - Register Attributes
    23
  - Reserved Bits Defined in Registers
    23
  - Reserved or Undefined Register Locations
    23
  - Default Upon Reset
    23
  - Consistency
    24
  - GART Programming Region
    24
  - I/O Mapped Registers
    24
    
    CONFIG_ADDRESS: Configuration Address Register
    24
    
    CONFIG_DATA: Configuration Data Register
    25
  - Error Handling Registers
    25
    
    Sac
    25
    
    Sdc
    31
    
    Mac
    41
    
    Pxb
    42
    
    Gxb
    44
    
    Wxb
    47
    
    Data Register
    50
  - Performance Monitor Registers
    50
    
    Sac
    50
    
    Sdc
    54
    
    Pxb
    56
    
    Gxb
    58
    
    Wxb
    63
  - Interrupt Related Registers
    64
    
    Sac
    64
    
    PID PCI Memory-Mapped Registers
    65
- Memory-Mapped Register Summary
  65
- I/O Select Register Format
  65
  - PID Indirect Access Registers
    66
- I/O Window Register Format
  66
- X)Apic EOI Register Format
  66
- Memory-Mapped Register Summary
  67
- I/O APIC ID Register Format
  69
- I/O (X)Apic Version Register Format
  69
- I/O (X)Apic Arbitration ID Register Format
  70
- I/O (X)Apic RTE Format
  70
3 System Architecture

73
- Coherency
  73
  - Processor Coherency
    73
  - PCI Coherency
    74
  - AGP Coherency
    74
- Ordering
  74
- Processor to PCI Traffic and PCI to PCI (Peer-To-Peer) Traffic
  75
- WXB Arbitration
  75
- Big-Endian Support
  76
- Indivisible Operations
  76
  - Processor Locks
    76
  - Inbound PCI Locks
    77
  - Atomic Writes
    77
  - Atomic Reads
    77
  - Locks with AGP Non-Coherent Traffic
    77
- Interrupt Delivery
  78
- WXB PCI Hot-Plug Support
  78
  - Slot Power-Up and Enable
    79
  - Slot Power-Down and Disable
    79
4 System Address Map

81
5 Memory Subsystem

91
- Organization
  91
- General Memory Characteristics
  91
  - Maximum Memory Configuration Using Two Cards
    92
    
    DIMM Types
    93
- Minimum/Maximum Memory Size Per Configuration
  93
  - Interleaving/Configurations
    94
  - Address Interleaving
    94
    
    Summary of Configuration Rules
    95
    
    Non-Uniform Memory Configurations
    95
  - Bandwidth
    95
  - Memory Subsystem Clocking
    96
  - Supporting Features
    96
    
    Auto Detection
    96
    
    Removing a Bad Row
    96
- Required DRAM Parameters
  96
  - Hardware Initialization
    97
  - Memory Scrubbing
    97
- Scrubbing Time
  97
6 Data Integrity and Error Handling

99
- Integrity
  99
  - System Bus
    99
  - Dram
    100
  - Expander Buses
    100
  - PCI Buses
    100
  - Agp
    100
  - Private Bus between SAC and SDC
    100
- Memory ECC Routing
  101
- Data Poisoning
  101
- Usage of First-Error and Next-Error
  101
  - Masked Bits
    102
  - BERR#/BINIT# Generation
    102
  - Intreq
    102
  - Xbinit
    103
  - Xserr
    103
- SAC/SDC Errors
  103
  - Data ECC or Parity Errors
    103
  - System Bus Errors
    104
  - SAC to SDC Interface Errors
    104
  - SAC to MAC Interface Errors
    105
  - Sdc/Memory Card Interface Errors
    105
  - Sdc/System Bus Errors
    106
  - SDC Internal Errors
    106
- Error Determination
  106
  - SAC Address on an Error
    107
  - SDC Logging Registers
    108
- Clearing Errors
  109
  - SAC/SDC Error Clearing
    109
- Multiple Errors
  109
  - SDC Multiple Errors
    110
  - SAC Multiple Errors
    111
  - Single Errors with Multiple Reporting
    111
  - Error Anomalies
    111
- Data Flow Errors
  112
- SAC Error Flow on Data
  112
- Error Conditions
  113
  - Table of Errors
    113
- SDC Error Data Flow
  113
- Error Cases
  114
  - PCI Integrity
    118
    
    PCI Bus Monitoring
    118
    
    PXB as Master
    118
    
    PXB as Target
    119
    
    GXB Error Flow
    120
  - GXB Error Flow
    123
  - WXB Data Integrity and Error Handling
    124
    
    Integrity
    124
    
    Data Parity Poisoning
    124
    
    Usage of First Error and Next Error Registers
    124
    
    Error Mask Bits
    125
    
    Error Steering/Signaling
    125
- List of WXB Error Sources Selectively Routable to XBINIT#, SERR_OUT#, and P(A/B)INTRQ
  125
- Supported Error Escalation to XBINIT
  125
- Supported Error Escalation to SERR_OUT
  126
- Supported Error Escalation to P(A/B)INTRQ
  126
  - INTRQ# Interrupt
    127
  - Error Determination and Logging
    127
  - Error Conditions
    128
7 AGP Subsystem

131
- Graphics Address Relocation Table (GART)
  131
- GART Table Usage for 4K
  132
- GART Table Usage for 4 MB
  132
  - GART Implementation
    133
- GART Entry Format for 4Kb
  133
- GART Entry Format for 4 MB
  133
  - Programming GART
    134
  - GART Implementation
    135
  - Coherency
    135
- GART SRAM Timings
  135
  - Interrupt Handling
    136
  - AGP Traffic
    136
    
    Addresses Used by the Graphics Card
    136
    
    Traffic Priority
    137
    
    Coherency, Translation and Types of AGP Traffic
    137
    
    Ordering Rules
    138
    
    Processor Locks and AGP Traffic
    138
- Coherency for AGP/PCI Streams
  138
  - Address Alignment and Transfer Sizes
    139
  - PCI Semantics Traffic
    139
- Delayed Read Matching Criteria
  141
  - Bandwidth
    143
- Burst Write Combining Modes
  143
- Burst Write Combining Examples with 3 Writes in 1X Transfer Mode
  143
  - Inbound Read Prefetching
    144
  - Latency
    144
  - GXB Address Map
    144
- Bandwidth Estimates for Various Request Sizes
  144
8 WXB Hot-Plug

147
- IHPC Configuration Registers
  147
- IHPC Configuration Register Space
  148
  - Page Number List for the IHPC PCI Register Descriptions
    149
  - VID: Vendor Identification Register
    149
  - DID: Device Identification Register
    149
  - PCICMD: PCI Command Register
    150
  - PCISTS: PCI Status Register
    151
  - RID: Revision Identification Register
    151
  - CLASS: Class Register
    152
  - CLS: Cache Line Size
    152
  - MLT: Master Latency Timer Register
    152
  - HDR: Header Register
    152
  - Base Address
    153
  - SVID: Subsystem Vendor Identification
    153
  - SID: Subsystem ID
    153
  - Interrupt Line
    153
  - Interrupt Pin
    154
  - Hot-Plug Slot Identifier
    154
  - Miscellaneous Hot-Plug Configuration
    154
  - Hot-Plug Features
    155
  - Switch Change SERR Status
    155
  - Power Fault SERR Status
    155
  - Arbiter SERR Status
    156
  - Memory Access Index
    156
  - Memory Mapped Register Access Port
    156
  - IHPC Memory Mapped Registers
    156
- IHPC Memor Mapped Register Space
  157
  - Page Number List for IHPC Memory Mapped Register Descriptions
    158
  - Slot Enable
    158
  - Hot-Plug Miscellaneous
    159
  - LED Control
    159
  - Hot-Plug Interrupt Input and Clear
    160
  - Hot-Plug Interrupt Mask
    161
  - Serial Input Byte Data
    162
  - Serial Input Byte Pointer
    163
  - General Purpose Output
    163
  - Hot-Plug Non-Interrupt Inputs
    163
  - Hot-Plug Slot Identifier
    163
  - Hot-Plug Switch Interrupt Redirect Enable
    164
  - Slot Power Control
    164
  - Extended Hot-Plug Miscellaneous
    164
9 IFB Register Mapping

165
10 IFB Usage Considerations

171
11 LPC/FWH Interface Configuration

191
- PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)
  191
- PCI to LPC I/O Space Registers
  205
  - DMA Registers
    205
  - Interrupt Controller Registers
    210
  - Counter/Timer Registers
    215
  - NMI Registers
    218
  - Real Time Clock Registers
    219
  - Advanced Power Management (APM) Registers
    220
  - ACPI Registers
    221
  - SMI Registers
    225
  - General Purpose I/O Registers
    227
12 IDE Configuration

233
13 Universal Serial Bus (USB) Configuration

245
14 SM Bus Controller Configuration

259
15 PCI/LPC Bridge Description

271
- PCI Interface
  271
  - Transaction Termination
    271
  - Parity Support
    271
  - PCI Arbitration
    271
- Interrupt Controller
  271
  - Programming the Interrupt Controller
    272
  - End of Interrupt Operation
    273
  - Modes of Operation
    274
  - Cascade Mode
    275
  - Edge and Level Triggered Mode
    276
  - Interrupt Masks
    276
  - Reading the Interrupt Controller Status
    277
  - Interrupt Steering
    277
- Serial Interrupts
  278
  - Protocol
    278
- SERIRQ Frames
  279
  - Timer/Counters
    280
    
    Programming the Interval Timer
    280
    
    Read Operations
    282
  - Real Time Clock
    283
    
    RTC Registers and RAM
    284
- RTC (Standard) RAM Bank
  284
  - RTC Update Cycle
    287
  - RTC Interrupts
    287
  - Lockable RAM Ranges
    287
16 IFB Power Management

289
- Overview
  289
- IFB Power States and Consumption
  289
  - IFB Power Planes
    290
    
    Power Plane Descriptions
    290
    
    SMI# Generation
    290
- Causes of SMI
  290
  - SCI Generation
    291
  - Sleep States
    291
- Causes of SCI
  291
  - ACPI Bits Not Implemented by IFB
    292
  - Entry/Exit for the S4 and S5 States
    292
- ACPI Bits Not Implemented in IFB
  292
  - Handling of Power Failures in IFB
    293

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