Memory Ordering Rules - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

purpose. Memory updates by DMA devices are coherent with respect to instruction and
data accesses of processors. The consistency between instruction and data caches of
processors with respect to memory updates by DMA devices is provided by the
hardware. In case a program modifies its own instructions, the sync.i and srlz.i
instructions are used to ensure that prior coherency actions are observed by a given
point in the program. Refer to the description sync.i on
Intel® Itanium® Instruction Set Reference
4.4.7 Memory Access Ordering
Memory data access ordering must satisfy read-after-write (RAW), write-after-write
(WAW), and write-after-read (WAR) data dependencies to the same memory location.
In addition, memory writes and flushes must observe control dependencies. Except for
these restrictions, reads, writes, and flushes may occur in an order different from the
specified program order. Note that no ordering exists between instruction accesses and
data accesses or between any two instruction accesses. The mechanisms described
below are defined to enforce a particular memory access order. In the following
discussion, the terms "previous" and "subsequent" are used to refer to the program
specified order. The term "visible" is used to refer to all architecturally visible effects of
performing a memory access (at a minimum this involves reading or writing memory).
Memory accesses follow one of four memory ordering semantics: unordered, release,
acquire or fence. Unordered data accesses may become visible in any order. Release
data accesses guarantee that all previous data accesses are made visible prior to being
made visible themselves. Acquire data accesses guarantee that they are made visible
prior to all subsequent data accesses. Fence operations combine the release and
acquire semantics into a bi-directional fence, i.e., they guarantee that all previous data
accesses are made visible prior to any subsequent data accesses being made visible.
Explicit memory ordering takes the form of a set of instructions: ordered load and
ordered check load (ld.acq, ld.c.clr.acq), ordered store (st.rel), semaphores
(cmpxchg, xchg, fetchadd), and memory fence (mf). The ld.acq and ld.c.clr.acq
instructions follow acquire semantics. The st.rel follows release semantics. The mf
instruction is a fence operation. The xchg, fetchadd.acq, and cmpxchg.acq
instructions have acquire semantics. The cmpxchg.rel, and fetchadd.rel instructions
have release semantics. The semaphore instructions also have implicit ordering. If
there is a write, it will always follow the read. In addition, the read and write will be
performed atomically with no intervening accesses to the same memory region.
Table 4-20
ordering semantics. "O" indicates that the first and second reference are performed in
order with respect to each other. A "-" indicates that no ordering is implied other than
data dependencies (and control dependencies for writes and flushes).
Table 4-20.
First Reference
fence
acquire
release
unordered
Volume 1, Part 1: Application Programming Model
illustrates the ordering interactions between memory accesses with different

Memory Ordering Rules

Fence
O
O
O
O
page 3:259
for an example of self-modifying code.
Second Reference
Acquire Release
O O
O O
– O
– O
in Volume 3:
Unordered
O
O
–
–
1:73