Memory Ordering Instructions; Branch Types - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

Table 4-21
definitions of the ordering rules related to non-cacheable memory, cache
synchronization, and privileged instructions, refer to
Attribute and Ordering" on page
Table 4-21.
ld.acq, ld.c.clr.acq
st.rel
xchg
cmpxchg.acq, cmpxchg.rel
fetchadd.acq,fetchadd.rel
mf
4.5 Branch Instructions
Branch instructions effect a transfer of control flow to a new address. Branch targets
are bundle-aligned, which means control is always passed to the first instruction slot of
the target bundle (slot 0). Branch instructions are not required to be the last instruction
in an instruction group. In fact, an instruction group can contain arbitrarily many
branches (provided that the normal RAW and WAW dependency requirements are met).
If a branch is taken, only instructions up to the taken branch will be executed. After a
taken branch, the next instruction executed will be at the target of the branch.
There are three categories of branches: IP-relative branches, long branches, and
indirect branches. IP-relative branches specify their target with a signed 21-bit
displacement, which is added to the IP of the bundle containing the branch to give the
address of the target bundle. The displacement allows a branch reach of 16MBytes.
Long branches are IP-relative with a 60-bit displacement, allowing the target to be
anywhere in the 64-bit address space. Because of the long immediate, long branches
occupy two instruction slots. Indirect branches use the branch registers to specify the
target address.
There are several branch types, as shown in
br.cond or br is a branch which is taken if the specified predicate is 1, and not-taken
otherwise. The conditional call branch br.call does the same thing, and in addition,
writes a link address to a specified branch register and adjusts the general register
stack (see
same thing as an indirect conditional branch, plus it adjusts the general register stack.
Unconditional branches, calls and returns are executed by specifying PR 0 (which is
always 1) as the predicate for the branch instruction. The long branches, brl.cond or
brl, and brl.call are identical to br.cond or br, and br.call, respectively, except for
their longer displacement.
Table 4-22.
Mnemonic
br.cond or br
br.call
br.ret
1:74
summarizes memory ordering instructions related to cacheable memory. For
2:82.

Memory Ordering Instructions

Mnemonic
"Register Stack" on page

Branch Types

Function
Conditional branch
Conditional procedure call
Conditional procedure return
Section 4.4.7, "Sequentiality
Operation
Ordered load and ordered check load
Ordered store
Exchange memory and general register
Conditional exchange of memory and general register
Add immediate to memory
Memory ordering fence
Table 4-22. The conditional branch
1:47). The conditional return br.ret does the
Branch Condition
Qualifying predicate
Qualifying predicate
Qualifying predicate
Volume 1, Part 1: Application Programming Model
Target Address
IP-rel or Indirect
IP-rel or Indirect
Indirect